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riscv: Add indirect CSRs for CLIC

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Add indirect CSR registers for RISC-V Core-Local Interrupt Controller (CLIC) Privileged Architecture Extensions.

Refer to: https://github.com/riscv/riscv-fast-interrupt

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2024-06-15 11:06:51 +08:00 committed by Xiang Xiao
parent e5ee04a902
commit 384610b253
1 changed files with 9 additions and 0 deletions
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9
arch/risc-v/include/csr.h
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@ -376,6 +376,15 @@
#define CSR_UINTTHRESH 0x047 /* Interrupt-level threshold */
#define CSR_USCRATCHCSWL 0x049 /* Conditional scratch swap on level change */
/* CLIC Indirect CSRs */
#define MISELECT_CLICCFG 0x14a0 /* MIREG */
#define MISELECT_CLICINTCTL 0x1000 /* MIREG */
#define MISELECT_CLICINTATTR 0x1000 /* MIREG2 */
#define MISELECT_CLICINTIP 0x1400 /* MIREG */
#define MISELECT_CLICINTIE 0x1400 /* MIREG2 */
#define MISELECT_CLICINTTRIG 0x1480 /* MIREG */
/* In mstatus register */
#define MSTATUS_UIE (0x1 << 0) /* User Interrupt Enable */