Add c5471 Ethernet driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@423 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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2f42bcb174
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@ -37,7 +37,7 @@ HEAD_ASRC = up_nommuhead.S
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CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S
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CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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up_createstack.c up_dataabort.c up_mdelay.c up_udealy.c up_doirq.c \
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up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c up_doirq.c \
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up_exit.c up_idle.c up_initialize.c up_initialstate.c \
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up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
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up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
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@ -45,4 +45,5 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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up_undefinedinsn.c up_usestack.c
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CHIP_ASRCS = c5471_lowputc.S c5471_vectors.S
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CHIP_CSRCS = c5471_irq.c c5471_serial.c c5471_timerisr.c c5471_watchdog.c
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CHIP_CSRCS = c5471_irq.c c5471_serial.c c5471_timerisr.c c5471_watchdog.c \
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c5471_ethernet.c
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1976
arch/arm/src/c5471/c5471_ethernet.c
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1976
arch/arm/src/c5471/c5471_ethernet.c
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File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
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/************************************************************
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/****************************************************************************
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* c5471/chip.h
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*
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* Copyright (C) 2007 Gregory Nutt. All rights reserved.
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@ -31,20 +31,61 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************/
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****************************************************************************/
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#ifndef __C5471_CHIP_H
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#define __C5471_CHIP_H
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/************************************************************
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/****************************************************************************
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* Included Files
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************************************************************/
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****************************************************************************/
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/************************************************************
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/****************************************************************************
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* Definitions
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************************************************************/
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****************************************************************************/
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/* UARTs ****************************************************/
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#define EIM_RAM_START 0xffd00000
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/* Ethernet Interface Module (EIM) ******************************************/
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#define EIM_CTRL 0xffff0000 /* ESM control register */
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#define EIM_STATUS 0xffff0004 /* ESM status register */
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#define EIM_CPU_TXBA 0xffff0008 /* CPU TX descriptors base address */
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#define EIM_CPU_RXBA 0xffff000c /* CPU RX descriptors base address */
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#define EIM_BUFSIZE 0xffff0010 /* Packet buffer size register */
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#define EIM_CPU_FILTER 0xffff0014 /* CPU filtering contol registers */
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#define EIM_CPU_DAHI 0xffff0018 /* CPU destination address (HI) */
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#define EIM_CPU_DALO 0xffff001c /* CPU destination address (LO) */
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#define EIM_MFVHI 0xffff0020 /* Multicast filter valid (HI) */
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#define EIM_MFVLO 0xffff0024 /* Multicast filter valid (LO) */
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#define EIM_MFMHI 0xffff0028 /* Multicast filter mask (HI) */
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#define EIM_MFMLO 0xffff002c /* Multicast filter mask (LO) */
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#define EIM_RXTH 0xffff0030 /* RX threshold register */
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#define EIM_CPU_RXREADY 0xffff0034 /* CPU RX ready register */
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#define EIM_INTEN 0xffff0038 /* ESM interrupt enable register */
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#define EIM_ENET0_TXDESC 0xffff0040 /* ENET0 TX Queue pointer */
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#define EIM_ENET0_RXDESC 0xffff0044 /* ENET0 RX Queue pointer */
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#define EIM_CPU_TXDESC 0xffff0050 /* CPU TX Queue pointer */
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#define EIM_CPU_RXDESC 0xffff0054 /* CPU RX Queue pointer */
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#define ENET0_MODE 0xffff0100 /* Mode register */
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#define ENET0_BOFFSEED 0xffff0104 /* Backoff seed register */
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#define ENET0_BCOUNT 0xffff0108 /* Backoff count register */
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#define ENET0_FLWPAUSE 0xffff010c /* TX flow pause count register */
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#define ENET0_FLWCONTROL 0xffff0110 /* Flow control register */
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#define ENET0_VTYPE 0xffff0114 /* VTYPE tag register */
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#define ENET0_SEISR 0xffff0118 /* System error int status register */
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#define ENET0_TXBUFRDY 0xffff011c /* TX descripter buffer ready */
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#define ENET0_TDBA 0xffff0120 /* TX descriptor base address */
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#define ENET0_RDBA 0xffff0124 /* RX descriptor base address */
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#define ENET0_PARHI 0xffff0128 /* Dest phys address match (HI) */
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#define ENET0_PARLO 0xffff012c /* Dest phys address match (LO) */
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#define ENET0_LARHI 0xffff0130 /* Log address hash filter (HI) */
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#define ENET0_LARLO 0xffff0134 /* Log address hash filter (LO) */
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#define ENET0_ADRMODE_EN 0xffff0138 /* Address mode enable register */
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#define ENET0_DRP 0xffff013c /* Desc ring poll interval count */
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/* UARTs ********************************************************************/
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#define UART_IRDA_BASE 0xffff0800
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#define UART_MODEM_BASE 0xffff1000
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@ -110,7 +151,7 @@
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#define UART_MODEM_RDPTR_UTX 0xffff1064 /* TX FIFO Read Pointer Register */
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#define UART_MODEM_WRPTR_UTX 0xffff1068 /* TX FIFO Write Pointer Register */
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/* UART Settings ********************************************/
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/* UART Settings ************************************************************/
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/* Miscellaneous UART settings. */
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@ -164,13 +205,13 @@
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#define MDR_AUTOBAUDING_MODE 0x00000002 /* Modem UART only */
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#define MDR_RESET_MODE 0x00000007 /* Both IrDA and Modem UARTs */
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/* SPI ******************************************************/
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/* SPI **********************************************************************/
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#define MAX_SPI 3
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#define SPI_REGISTER_BASE 0xffff2000
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/* GIO ******************************************************/
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/* GIO **********************************************************************/
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#define MAX_GIO (35)
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@ -211,7 +252,7 @@
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#define KBGPIO_EN 0xffff2914 /* Selects register for muxed
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* KBGPIOs */
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/* Timers ***************************************************/
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/* Timers *******************************************************************/
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#define C5471_TIMER0_CTRL 0xffff2a00
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#define C5471_TIMER0_CNT 0xffff2a04
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@ -241,8 +282,8 @@
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#define ILR_IRQ3_REG 0xffff2d28 /* 3-GPIO0 */
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#define ILR_IRQ4_REG 0xffff2d2c /* 4-Ethernet */
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#define ILR_IRQ5_REG 0xffff2d30 /* 5-KBGPIO[7:0] */
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#define ILR_IRQ6_REG 0xffff2d34 /* 6-Uart serial */
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#define ILR_IRQ7_REG 0xffff2d38 /* 7-Uart IRDA */
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#define ILR_IRQ6_REG 0xffff2d34 /* 6-Uart serial */
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#define ILR_IRQ7_REG 0xffff2d38 /* 7-Uart IRDA */
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#define ILR_IRQ8_REG 0xffff2d3c /* 8-KBGPIO[15:8] */
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#define ILR_IRQ9_REG 0xffff2d40 /* 9-GPIO3 */
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#define ILR_IRQ10_REG 0xffff2d44 /* 10-GPIO2 */
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@ -252,11 +293,22 @@
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#define ILR_IRQ14_REG 0xffff2d54 /* 14-GPIO[19:4] */
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#define ILR_IRQ15_REG 0xffff2d58 /* 15-API */
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/* I2C ******************************************************/
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/* CLKM *********************************************************************/
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#define CLKM 0xffff2f00
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#define CLKM_CTL_RST 0xffff2f10
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#define CLKM_RESET 0xffff2f18
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#define CLKM_RESET_EIM 0x00000008
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#define CLKM_EIM_CLK_STOP 0x00000010
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#define CLKM_CTL_RST_LEAD_RESET 0x00000000
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#define CLKM_CTL_RST_EXT_RESET 0x00000002
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/* I2C **********************************************************************/
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#define MAX_I2C 1
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/* API ******************************************************/
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/* API **********************************************************************/
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#define DSPRAM_BASE 0xffe00000 /* DSPRAM base address */
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#define DSPRAM_END 0xffe03fff
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@ -308,12 +360,12 @@
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#define DSPMEM_ARM_TO_DSP(addr) \
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((((__u32)(addr) - DSPMEM_ARM_START) >> 1) + DSPMEM_DSP_START)
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/************************************************************
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/****************************************************************************
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* Inline Functions
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************************************************************/
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****************************************************************************/
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/************************************************************
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/****************************************************************************
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* Public Function Prototypes
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************************************************************/
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****************************************************************************/
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#endif /* __C5471_CHIP_H */
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