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arch/arm/src/stm32f7/: Apply fix introduced by 0947b31fbb for STM32F7[6/7]XX to STM32F7[2/3/4/5]XX.

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In RCC configuration, STM32_RCC_DCKCFGR2 has nothing to do with PLLI2S; PLLI2S is not dependent on LTDC, instead on SAICLK1/2 generated from PLLI2S
This commit is contained in:
Björn Brandt 2020-01-08 07:09:49 -06:00 committed by Gregory Nutt
parent 3e45517599
commit 38b043da9f
2 changed files with 34 additions and 30 deletions
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32
arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c
View File

@ -866,7 +866,7 @@ static void stm32_stdclockconfig(void)
#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI)
/* Configure PLLSAI */
/* Configure PLLSAI */
regval = getreg32(STM32_RCC_PLLSAICFGR);
regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
@ -918,8 +918,10 @@ static void stm32_stdclockconfig(void)
{
}
#endif
#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S)
#if defined(CONFIG_STM32F7_PLLI2S) || \
(STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \
(STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1))
/* Configure PLLI2S */
regval = getreg32(STM32_RCC_PLLI2SCFGR);
@ -937,6 +939,19 @@ static void stm32_stdclockconfig(void)
| STM32_RCC_PLLI2SCFGR_PLLI2SR);
putreg32(regval, STM32_RCC_PLLI2SCFGR);
/* Enable PLLI2S */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLI2SON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLLI2S is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
{
}
#endif
regval = getreg32(STM32_RCC_DCKCFGR2);
regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK
| RCC_DCKCFGR2_USART2SEL_MASK
@ -978,19 +993,6 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_DCKCFGR2);
/* Enable PLLI2S */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLI2SON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLLI2S is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
{
}
#endif
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK)
/* Low speed internal clock source LSI */

32
arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
View File

@ -863,7 +863,7 @@ static void stm32_stdclockconfig(void)
#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI)
/* Configure PLLSAI */
/* Configure PLLSAI */
regval = getreg32(STM32_RCC_PLLSAICFGR);
regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
@ -905,8 +905,10 @@ static void stm32_stdclockconfig(void)
{
}
#endif
#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S)
#if defined(CONFIG_STM32F7_PLLI2S) || \
(STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \
(STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1))
/* Configure PLLI2S */
regval = getreg32(STM32_RCC_PLLI2SCFGR);
@ -920,6 +922,19 @@ static void stm32_stdclockconfig(void)
| STM32_RCC_PLLI2SCFGR_PLLI2SR);
putreg32(regval, STM32_RCC_PLLI2SCFGR);
/* Enable PLLI2S */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLI2SON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLLI2S is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
{
}
#endif
regval = getreg32(STM32_RCC_DCKCFGR2);
regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK
| RCC_DCKCFGR2_USART2SEL_MASK
@ -955,19 +970,6 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_DCKCFGR2);
/* Enable PLLI2S */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLI2SON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLLI2S is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
{
}
#endif
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK)
/* Low speed internal clock source LSI */