Merged in juniskane/nuttx_stm32l4/stm32l4_dfsdm_pr (pull request #486)
STM32L4 DFSDM: add peripheral, DAC, TIM: small changes
* STM32L4 DAC: do not configure output pin if it is not used
* STM32L4 TIM: fix compilation of timers with complementary outputs when not PWM_MULTICHAN
* STM32L4 DFSDM: peripheral for digital filters for sigma-delta ADCs
Initial version. Timer trigger support is not completed and there is
some issue with DMA.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Juha Niskanen
Gregory Nutt
parent
d33857002a
commit
38f44a627b
@ -837,6 +837,10 @@ config STM32L4_DAC
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bool
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default n
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config STM32L4_DFSDM
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bool
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default n
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config STM32L4_DMA
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bool
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default n
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@ -3382,6 +3386,42 @@ config STM32L4_DAC2_OUTPUT_ADC
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endmenu
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menu "DFSDM Configuration"
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depends on STM32L4_DFSDM1
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config STM32L4_DFSDM1_FLT0
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bool "DFSDM1 Filter 0"
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default n
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select STM32L4_DFSDM
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config STM32L4_DFSDM1_FLT1
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bool "DFSDM1 Filter 1"
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default n
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select STM32L4_DFSDM
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config STM32L4_DFSDM1_FLT2
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bool "DFSDM1 Filter 2"
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default n
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depends on !STM32L4_STM32L4X3
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select STM32L4_DFSDM
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config STM32L4_DFSDM1_FLT3
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bool "DFSDM1 Filter 3"
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default n
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depends on !STM32L4_STM32L4X3
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select STM32L4_DFSDM
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config STM32L4_DFSDM1_DMA
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bool "DFSDM1 DMA"
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depends on STM32L4_DFSDM
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default n
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---help---
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If DMA is selected, then the DFSDM may be configured to support
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DMA transfer, which is necessary if multiple channels are read
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or if very high trigger frequencies are used.
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endmenu
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config STM32L4_HAVE_USART1
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bool
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default n
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@ -135,6 +135,10 @@ ifeq ($(CONFIG_STM32L4_DAC),y)
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CHIP_CSRCS += stm32l4_dac.c
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endif
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ifeq ($(CONFIG_STM32L4_DFSDM),y)
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CHIP_CSRCS += stm32l4_dfsdm.c
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endif
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ifeq ($(CONFIG_STM32L4_DMA),y)
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CHIP_CSRCS += stm32l4_dma.c
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endif
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@ -59,7 +59,7 @@ LPUART : TODO (Low power UART working with LSE at low baud rates)
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LPTIM : Code written, to be tested (Low power TIMER)
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OPAMP : TODO (Analog operational amplifier)
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COMP : There is some code (Analog comparators)
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DFSDM : TODO (Digital Filter and Sigma-Delta Modulator)
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DFSDM : There is some code (Digital Filter for Sigma-Delta Modulators)
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LCD : TODO (Segment LCD controller)
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SAIPLL : works (PLL For Digital Audio interfaces, and other things)
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SAI : There is some code (Digital Audio interfaces, I2S, SPDIF, etc)
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427
arch/arm/src/stm32l4/chip/stm32l4_dfsdm.h
Normal file
427
arch/arm/src/stm32l4/chip/stm32l4_dfsdm.h
Normal file
@ -0,0 +1,427 @@
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/************************************************************************************
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* arch/arm/src/stm32l4/chip/stm32l4_dfsdm.h
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*
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* Copyright (C) 2017 Haltian Ltd. All rights reserved.
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* Author: Juha Niskanen <juha.niskanen@haltian.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_DFSDM_H
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#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_DFSDM_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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/* Register Offsets for the DFSDM. */
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/* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */
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#define STM32L4_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y))
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#define STM32L4_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */
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#define STM32L4_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */
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#define STM32L4_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */
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#define STM32L4_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */
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#ifndef CONFIG_STM32L4_STM32L4X3
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# define STM32L4_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */
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# define STM32L4_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */
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# define STM32L4_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */
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# define STM32L4_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */
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#endif
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#define STM32L4_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y))
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#define STM32L4_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */
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#define STM32L4_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */
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#define STM32L4_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */
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#define STM32L4_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */
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#ifndef CONFIG_STM32L4_STM32L4X3
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# define STM32L4_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */
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# define STM32L4_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */
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# define STM32L4_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */
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# define STM32L4_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */
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#endif
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#define STM32L4_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y))
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#define STM32L4_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */
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#define STM32L4_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */
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#define STM32L4_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */
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#define STM32L4_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */
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#ifndef CONFIG_STM32L4_STM32L4X3
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# define STM32L4_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */
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# define STM32L4_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */
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# define STM32L4_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */
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# define STM32L4_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */
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#endif
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#define STM32L4_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y))
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#define STM32L4_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */
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#define STM32L4_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */
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#define STM32L4_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */
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#define STM32L4_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */
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#ifndef CONFIG_STM32L4_STM32L4X3
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#define STM32L4_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */
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#define STM32L4_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */
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#define STM32L4_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */
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#define STM32L4_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */
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#endif
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#define STM32L4_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */
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#define STM32L4_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 channel data input register */
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#define STM32L4_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 channel data input register */
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#define STM32L4_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 channel data input register */
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#define STM32L4_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 channel data input register */
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#ifndef CONFIG_STM32L4_STM32L4X3
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# define STM32L4_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 channel data input register */
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# define STM32L4_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 channel data input register */
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# define STM32L4_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 channel data input register */
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# define STM32L4_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 channel data input register */
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#endif
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/* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */
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#define STM32L4_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */
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#define STM32L4_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */
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#define STM32L4_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */
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#define STM32L4_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */
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#define STM32L4_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */
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#define STM32L4_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */
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#define STM32L4_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */
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#define STM32L4_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */
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#define STM32L4_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */
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#define STM32L4_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */
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#define STM32L4_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */
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#define STM32L4_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */
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#define STM32L4_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */
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#define STM32L4_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */
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#define STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */
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/* Register Addresses ***************************************************************/
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/* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */
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#define STM32L4_DFSDM_CHCFGR1(y) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_CHCFGR1_OFFSET(y))
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#define STM32L4_DFSDM_CH0CFGR1 (STM32L4_DFSDM_BASE+STM32L4_DFSDM_CH0CFGR1_OFFSET)
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#define STM32L4_DFSDM_CHCFGR2(y) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_CHCFGR2_OFFSET(y))
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#define STM32L4_DFSDM_CHAWSCDR(y) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_CHAWSCDR_OFFSET(y))
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#define STM32L4_DFSDM_CHWDATR(y) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_CHWDATR_OFFSET(y)
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#define STM32L4_DFSDM_CHDATINR(y) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_CHDATINR_OFFSET(y))
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/* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */
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#define STM32L4_DFSDM_FLTCR1(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTCR1_OFFSET(x))
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#define STM32L4_DFSDM_FLTCR2(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTCR2_OFFSET(x))
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#define STM32L4_DFSDM_FLTISR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTISR_OFFSET(x))
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#define STM32L4_DFSDM_FLTICR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTICR_OFFSET(x))
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#define STM32L4_DFSDM_FLTJCHGR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTJCHGR_OFFSET(x))
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#define STM32L4_DFSDM_FLTFCR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTFCR_OFFSET(x))
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#define STM32L4_DFSDM_FLTJDATAR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTJDATAR_OFFSET(x))
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#define STM32L4_DFSDM_FLTRDATAR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTRDATAR_OFFSET(x))
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#define STM32L4_DFSDM_FLTAWHTR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTAWHTR_OFFSET(x))
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#define STM32L4_DFSDM_FLTAWLTR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTAWLTR_OFFSET(x))
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#define STM32L4_DFSDM_FLTAWSR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTAWSR_OFFSET(x))
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#define STM32L4_DFSDM_FLTAWCFR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTAWCFR_OFFSET(x))
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#define STM32L4_DFSDM_FLTEXMAX(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTEXMAX_OFFSET(x))
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#define STM32L4_DFSDM_FLTEXMIN(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTEXMIN_OFFSET(x))
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#define STM32L4_DFSDM_FLTCNVTIMR(x) (STM32L4_DFSDM_BASE+STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x))
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/* Register Bitfield Definitions ****************************************************/
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/* DFSDM channel configuration y register (DFSDM_CHyCFGR1) */
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/* Bits that are present only in DFSDM_CH0CFGR1 register (channel y=0) */
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#define DFSDM_CH0CFGR1_CKOUTDIV_SHIFT (16) /* Bits 16-23: Output serial clock divider */
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#define DFSDM_CH0CFGR1_CKOUTDIV_MASK (0xff << DFSDM_CH0CFGR1_CKOUTDIV_SHIFT)
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# define DFSDM_CH0CFGR1_CKOUTDIV_NONE (0 << DFSDM_CH0CFGR1_CKOUTDIV_SHIFT) /* Output clock generation disabled */
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# define DFSDM_CH0CFGR1_CKOUTDIV(n) ((n) << DFSDM_CH0CFGR1_CKOUTDIV_SHIFT) /* Divider = CKOUTDIV+1, n=1..255 */
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#define DFSDM_CH0CFGR1_CKOUTSRC (1 << 30) /* Bit 30: Output serial clock source selection */
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#define DFSDM_CH0CFGR1_DFSDMEN (1 << 31) /* Bit 31: Global enable for DFSDM */
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/* Bits that are present in all DFSDM_CHyCFGR1 registers */
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#define DFSDM_CHCFGR1_SPICKSEL_SHIFT (2) /* Bits 2-3: SPI clock select for channel y */
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#define DFSDM_CHCFGR1_SPICKSEL_MASK (3 << DFSDM_CHCFGR1_SPICKSEL_SHIFT)
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# define DFSDM_CHCFGR1_SPICKSEL_EXT (0 << DFSDM_CHCFGR1_SPICKSEL_SHIFT) /* clock coming from external CKINy input */
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# define DFSDM_CHCFGR1_SPICKSEL_CKOUT (1 << DFSDM_CHCFGR1_SPICKSEL_SHIFT) /* clock coming from internal CKOUT output, sampling from SITP[1:0] */
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# define DFSDM_CHCFGR1_SPICKSEL_CKOUTFALL (2 << DFSDM_CHCFGR1_SPICKSEL_SHIFT) /* clock coming from internal CKOUT input, sampling on falling edge */
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# define DFSDM_CHCFGR1_SPICKSEL_CKOUTRISE (3 << DFSDM_CHCFGR1_SPICKSEL_SHIFT) /* clock coming from internal CKOOUT input, sampling on rising edge */
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#define DFSDM_CHCFGR1_SITP_SHIFT (0) /* Bits 0-1: Serial interface type for channel y */
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#define DFSDM_CHCFGR1_SITP_MASK (3 << DFSDM_CHCFGR1_SITP_SHIFT)
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# define DFSDM_CHCFGR1_SITP_SPIRISE (0 << DFSDM_CHCFGR1_SITP_SHIFT) /* SPI with rising edge to strobe data */
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# define DFSDM_CHCFGR1_SITP_SPIFALL (1 << DFSDM_CHCFGR1_SITP_SHIFT) /* SPI with falling edge to strobe data */
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# define DFSDM_CHCFGR1_SITP_MANSEFALL (2 << DFSDM_CHCFGR1_SITP_SHIFT) /* Manchester coded input on DATINy pin with falling edge as logic 1 */
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# define DFSDM_CHCFGR1_SITP_MANSERISE (3 << DFSDM_CHCFGR1_SITP_SHIFT) /* Manchester coded input on DATINy pin with rising edge as logic 1 */
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#define DFSDM_CHCFGR1_SCDEN (1 << 5) /* Bit 5: Short-circuit detector enable on channel y */
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#define DFSDM_CHCFGR1_CKABEN (1 << 6) /* Bit 6: Clock absence detector enable on channel y */
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#define DFSDM_CHCFGR1_CHEN (1 << 7) /* Bit 7: Channel y enable */
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#define DFSDM_CHCFGR1_CHINSEL (1 << 8) /* Bit 8: Channel inputs selection */
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#define DFSDM_CHCFGR1_DATMPX_SHIFT (12) /* Bits 12-13: Input data multiplexer for channel y */
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#define DFSDM_CHCFGR1_DATMPX_MASK (3 << DFSDM_CHCFGR1_DATMPX_SHIFT)
|
||||
# define DFSDM_CHCFGR1_DATMPX_EXT (0 << DFSDM_CHCFGR1_DATMPX_SHIFT) /* External: Data to channel y are taken from external serial inputs as 1-bit values */
|
||||
# define DFSDM_CHCFGR1_DATMPX_ADC (1 << DFSDM_CHCFGR1_DATMPX_SHIFT) /* ADC: Data to channel y are taken from internal analog to digital converter ADC */
|
||||
# define DFSDM_CHCFGR1_DATMPX_DATINR (2 << DFSDM_CHCFGR1_DATMPX_SHIFT) /* DATINR: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write */
|
||||
/* 3: Reserved */
|
||||
#define DFSDM_CHCFGR1_DATPACK_SHIFT (14) /* Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. */
|
||||
#define DFSDM_CHCFGR1_DATPACK_MASK (3 << DFSDM_CHCFGR1_DATPACK_SHIFT)
|
||||
# define DFSDM_CHCFGR1_DATPACK_STD (0 << DFSDM_CHCFGR1_DATPACK_SHIFT) /* Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0] */
|
||||
# define DFSDM_CHCFGR1_DATPACK_INTER (1 << DFSDM_CHCFGR1_DATPACK_SHIFT) /* Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples INDAT0[15:0] and INDAT1[15:0] for channel y */
|
||||
# define DFSDM_CHCFGR1_DATPACK_DUAL (2 << DFSDM_CHCFGR1_DATPACK_SHIFT) /* Dual: input data in DFSDM_CHyDATINR register are stored as two samples INDAT0[15:0] and INDAT1[15:0] for channels y and y+1 */
|
||||
/* 3: Reserved */
|
||||
|
||||
/* DFSDM channel configuration y register (DFSDM_CHyCFGR2) */
|
||||
|
||||
#define DFSDM_CHCFGR2_DTRBS_SHIFT (3) /* Bits 3-7: Data right bit-shift for channel y */
|
||||
#define DFSDM_CHCFGR2_DTRBS_MASK (0x1f << DFSDM_CHCFGR2_DTRBS_SHIFT)
|
||||
# define DFSDM_CHCFGR2_DTRBS(n) ((n) << DFSDM_CHCFGR2_DTRBS_SHIFT) /* n = 0..31 */
|
||||
|
||||
#define DFSDM_CHCFGR2_OFFSET_SHIFT (8) /* Bits 8-31: 24-bit calibration offset for channel y */
|
||||
#define DFSDM_CHCFGR2_OFFSET_MASK (0xffffff << DFSDM_CHCFGR2_OFFSET_SHIFT)
|
||||
# define DFSDM_CHCFGR2_OFFSET(n) ((n) << DFSDM_CHCFGR2_OFFSET_SHIFT)
|
||||
|
||||
/* DFSDM channel analog watchdog and short-circuit detector register (DFSDM_CHyAWSCDR) */
|
||||
|
||||
#define DFSDM_CHAWSCDR_SCDT_SHIFT (0) /* Bits 0-7: short-circuit detector threshold */
|
||||
#define DFSDM_CHAWSCDR_SCDT_MASK (0xff << DFSDM_CHAWSCDR_SCDT_SHIFT)
|
||||
# define DFSDM_CHAWSCDR_SCDT(n) ((n) << DFSDM_CHAWSCDR_SCDT_SHIFT)
|
||||
#define DFSDM_CHAWSCDR_BKSCD_SHIFT (12) /* Bits 12-15: Break signal assignment for short-circuit detector */
|
||||
#define DFSDM_CHAWSCDR_BKSCD_MASK (0xf << DFSDM_CHAWSCDR_BKSCD_SHIFT)
|
||||
#define DFSDM_CHAWSCDR_AWFOSR_SHIFT (16) /* Bits 16-20: Analog watchdog filter oversampling ratio */
|
||||
#define DFSDM_CHAWSCDR_AWFOSR_MASK (0x1f << DFSDM_CHAWSCDR_AWFOSR_SHIFT)
|
||||
# define DFSDM_CHAWSCDR_AWFOSR(n) ((n) << DFSDM_CHAWSCDR_AWFOSR_SHIFT) /* n=0..31 */
|
||||
#define DFSDM_CHAWSCDR_AWFORD_SHIFT (22) /* Bits 22-24: Analog watchdog Sinc filter order */
|
||||
#define DFSDM_CHAWSCDR_AWFORD_MASK (3 << DFSDM_CHAWSCDR_AWFORD_SHIFT)
|
||||
# define DFSDM_CHAWSCDR_AWFORD_FASTSINC (0 << DFSDM_CHAWSCDR_AWFORD_SHIFT)
|
||||
# define DFSDM_CHAWSCDR_AWFORD_SINC1 (1 << DFSDM_CHAWSCDR_AWFORD_SHIFT)
|
||||
# define DFSDM_CHAWSCDR_AWFORD_SINC2 (2 << DFSDM_CHAWSCDR_AWFORD_SHIFT)
|
||||
# define DFSDM_CHAWSCDR_AWFORD_SINC3 (3 << DFSDM_CHAWSCDR_AWFORD_SHIFT)
|
||||
|
||||
/* DFSDM channel watchdog filter data register (DFSDM_CHyWDATR) */
|
||||
|
||||
#define DFSDM_CHWDATR_WDATA_SHIFT (0) /* Bits 0-15: channel watchdog data */
|
||||
#define DFSDM_CHWDATR_WDATA_MASK (0xffff << DFSDM_CHWDATR_WDATA_SHIFT)
|
||||
|
||||
/* DFSDM channel data input register (DFSDM_CHyDATINR) */
|
||||
|
||||
#define DFSDM_CHDATINR_INDAT0_SHIFT (0) /* Bits 0-15: input data 0 */
|
||||
#define DFSDM_CHDATINR_INDAT0_MASK (0xffff << DFSDM_CHDATINR_INDAT0_SHIFT)
|
||||
# define DFSDM_CHDATINR_INDAT0(n) ((n) << DFSDM_CHDATINR_INDAT0_SHIFT)
|
||||
#define DFSDM_CHDATINR_INDAT1_SHIFT (0) /* Bits 15-31: input data 1 */
|
||||
#define DFSDM_CHDATINR_INDAT1_MASK (0xffff << DFSDM_CHDATINR_INDAT1_SHIFT)
|
||||
# define DFSDM_CHDATINR_INDAT1(n) ((n) << DFSDM_CHDATINR_INDAT1_SHIFT)
|
||||
|
||||
/* DFSDM filter x module registers */
|
||||
/* DFSDM control register 1 (DFSDM_FLTxCR1) */
|
||||
|
||||
#define DFSDM_FLTCR1_DFEN (1 << 0) /* Bit 0: DFSDM_FLTx enable */
|
||||
#define DFSDM_FLTCR1_JSWSTART (1 << 1) /* Bit 1: Start a conversion of the injected group of channels */
|
||||
#define DFSDM_FLTCR1_JSYNC (1 << 3) /* Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger */
|
||||
#define DFSDM_FLTCR1_JSCAN (1 << 4) /* Bit 4: Scanning conversion mode for injected conversions */
|
||||
#define DFSDM_FLTCR1_JDMAEN (1 << 5) /* Bit 5: DMA channel enabled to read data for the injected channel group */
|
||||
/* Bits 6-7: Reserved */
|
||||
#define DFSDM_FLTCR1_JEXTSEL_SHIFT (8) /* Bits 8-10: External trigger selection for injected group */
|
||||
#define DFSDM_FLTCR1_JEXTSEL_MASK (0x7 << DFSDM_FLTCR1_JEXTSEL_SHIFT)
|
||||
# define DFSDM_FLTCR1_JEXTSEL(event) ((event) << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* Event = 0..7 */
|
||||
/* Bits 11-12: Reserved */
|
||||
#define DFSDM_FLTCR1_JEXTEN_SHIFT (13) /* Bits 13-14: Trigger enable and edge election for injected group */
|
||||
#define DFSDM_FLTCR1_JEXTEN_MASK (3 << DFSDM_FLTCR1_JEXTEN_SHIFT)
|
||||
# define DFSDM_FLTCR1_JEXTEN_NONE (0 << DFSDM_FLTCR1_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
# define DFSDM_FLTCR1_JEXTEN_RISING (1 << DFSDM_FLTCR1_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
|
||||
# define DFSDM_FLTCR1_JEXTEN_FALLING (2 << DFSDM_FLTCR1_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
|
||||
# define DFSDM_FLTCR1_JEXTEN_BOTH (3 << DFSDM_FLTCR1_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
|
||||
#define DFSDM_FLTCR1_RSWSTART (1 << 17) /* Bit 17: Software start of a conversion on the regular channel */
|
||||
#define DFSDM_FLTCR1_RCONT (1 << 18) /* Bit 18: Continuous mode selection for regular conversions */
|
||||
#define DFSDM_FLTCR1_RSYNC (1 << 19) /* Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 */
|
||||
#define DFSDM_FLTCR1_RDMAEN (1 << 21) /* Bit 21: DMA channel enabled to read data for the regular conversion */
|
||||
#define DFSDM_FLTCR1_RCH_SHIFT (24) /* Bits 24-26: Regular channel selection */
|
||||
#define DFSDM_FLTCR1_RCH_MASK (0x7 << DFSDM_FLTCR1_RCH_SHIFT)
|
||||
#define DFSDM_FLTCR1_RCH(ch) ((ch) << DFSDM_FLTCR1_RCH_SHIFT) /* Channel ch is selected as the regular channel */
|
||||
#define DFSDM_FLTCR1_FAST (1 << 29) /* Bit 29: Fast conversion mode selection for regular conversions */
|
||||
#define DFSDM_FLTCR1_AWFSEL (1 << 30) /* Bit 30: Analog watchdog fast mode select */
|
||||
|
||||
/* DFSDM control register 2 (DFSDM_FLTxCR2) */
|
||||
|
||||
/* Bits that are present only in DFSDM_FLT0CR2 register (filter x=0) */
|
||||
|
||||
#define DFSDM_FLT0CR2_SCDIE (1 << 5) /* Bit 5: Short-circuit detector interrupt enable */
|
||||
#define DFSDM_FLT0CR2_CKABIE (1 << 6) /* Bit 6: Clock absence interrupt enable */
|
||||
|
||||
/* Bits that are present in all DFSDM_FLTxCR2 registers */
|
||||
|
||||
#define DFSDM_FLTCR2_JEOCIE (1 << 0) /* Bit 0: Injected end of conversion interrupt enable */
|
||||
#define DFSDM_FLTCR2_REOCIE (1 << 1) /* Bit 1: Regular end of conversion interrupt enable */
|
||||
#define DFSDM_FLTCR2_JOWRIE (1 << 2) /* Bit 2: Injected data overrun interrupt enable */
|
||||
#define DFSDM_FLTCR2_ROWRIE (1 << 3) /* Bit 3: Regular data overrun interrupt enable
|
||||
*/
|
||||
#define DFSDM_FLTCR2_AWDIE (1 << 4) /* Bit 4: Analog watchdog interrupt enable */
|
||||
#define DFSDM_FLTCR2_EXCH_SHIFT (8) /* Bits 8-15: Extremes detector channel selection */
|
||||
#define DFSDM_FLTCR2_EXCH_MASK (0xff << DFSDM_FLTCR2_EXCH_SHIFT)
|
||||
#define DFSDM_FLTCR2_EXCH(ch) ((1 << (ch)) << DFSDM_FLTCR2_EXCH_SHIFT)
|
||||
#define DFSDM_FLTCR2_AWDCH_SHIFT (16) /* Bits 16-23: Analog watchdog channel selection */
|
||||
#define DFSDM_FLTCR2_AWDCH_MASK (0xff << DFSDM_FLTCR2_AWDCH_SHIFT)
|
||||
#define DFSDM_FLTCR2_AWDCH(ch) ((1 << (ch)) << DFSDM_FLTCR2_AWDCH_SHIFT)
|
||||
|
||||
/* DFSDM interrupt and status register (DFSDM_FLTxISR) */
|
||||
|
||||
/* Bits that are present only in DFSDM_FLT0ISR register (filter x=0) */
|
||||
|
||||
#define DFSDM_FLT0ISR_CKABF_SHIFT (16) /* Bits 16-23: short-circuit detector flag */
|
||||
#define DFSDM_FLT0ISR_CKABF_MASK (0xff << DFSDM_FLT0ISR_CKABF_SHIFT)
|
||||
#define DFSDM_FLT0ISR_SCDF_SHIFT (24) /* Bits 24-31: clock absence flag */
|
||||
#define DFSDM_FLT0ISR_SCDF_MASK (0xff << DFSDM_FLT0ISR_SCDF_SHIFT)
|
||||
|
||||
/* Bits that are present in all DFSDM_FLTxISR registers */
|
||||
|
||||
#define DFSDM_FLTISR_JEOCF (1 << 0) /* Bit 0: End of injected conversion flag */
|
||||
#define DFSDM_FLTISR_REOCF (1 << 1) /* Bit 1: End of regular conversion flag */
|
||||
#define DFSDM_FLTISR_JOVRF (1 << 2) /* Bit 2: Injected conversion overrun flag */
|
||||
#define DFSDM_FLTISR_ROVRF (1 << 3) /* Bit 3: Regular conversion overrun flag */
|
||||
#define DFSDM_FLTISR_AWDF (1 << 4) /* Bit 4: Analog watchdog */
|
||||
|
||||
#define DFSDM_FLTISR_JCIP (1 << 13) /* Bit 13: Injected conversion in progress status */
|
||||
#define DFSDM_FLTISR_RCIP (1 << 14) /* Bit 14: Regular conversion in progress status */
|
||||
|
||||
/* DFSDM interrupt flag clear register (DFSDM_FLTxICR) */
|
||||
|
||||
/* Bits that are present only in DFSDM_FLT0ICR register (filter x=0) */
|
||||
|
||||
#define DFSDM_FLT0ISR_CLRCKABF_SHIFT (16) /* Bits 16-23: Clear the short-circuit detector flag */
|
||||
#define DFSDM_FLT0ISR_CLRCKABF_MASK (0xff << DFSDM_FLT0ISR_CLRCKABF_SHIFT)
|
||||
#define DFSDM_FLT0ISR_CLRSCDF_SHIFT (24) /* Bits 24-31: clear the clock absence flag */
|
||||
#define DFSDM_FLT0ISR_CLRSCDF_MASK (0xff << DFSDM_FLT0ISR_CLRSCDF_SHIFT)
|
||||
|
||||
/* Bits that are present in all DFSDM_FLTxICR registers */
|
||||
|
||||
#define DFSDM_FLTICR_CLRJOVRF (1 << 2) /* Bit 2: Clear the injected conversion overrun flag */
|
||||
#define DFSDM_FLTICR_CLRROVRF (1 << 3) /* Bit 3: Clear the regular conversion overrun flag */
|
||||
|
||||
/* DFSDM injected channel group selection register (DFSDM_FLTxJCHGR) */
|
||||
|
||||
#define DFSDM_FLTJCHGR_JCHG_SHIFT (0) /* Bits 0-7: Injected channel group selection */
|
||||
#define DFSDM_FLTJCHGR_JCHG_MASK (0xff << DFSDM_FLTJCHGR_JCHG_SHIFT)
|
||||
|
||||
/* DFSDM filter control register (DFSDM_FLTxFCR) */
|
||||
|
||||
#define DFSDM_FLTFCR_FOSR_SHIFT (16) /* Bits 16-25: Sinc filter oversampling ratio) */
|
||||
#define DFSDM_FLTFCR_FOSR_MASK (0x3ff << DFSDM_FLTFCR_FOSR_SHIFT)
|
||||
# define DFSDM_FLTFCR_FOSR(n) ((n) << DFSDM_FLTFCR_FOSR_SHIFT) /* n=0..1023 */
|
||||
#define DFSDM_FLTFCR_FORD_SHIFT (29) /* Bits 29-31: Sinc filter order */
|
||||
#define DFSDM_FLTFCR_FORD_MASK (7 << DFSDM_FLTFCR_FORD_SHIFT)
|
||||
# define DFSDM_FLTFCR_FORD_FASTSINC (0 << DFSDM_FLTFCR_FORD_SHIFT)
|
||||
# define DFSDM_FLTFCR_FORD_SINC1 (1 << DFSDM_FLTFCR_FORD_SHIFT)
|
||||
# define DFSDM_FLTFCR_FORD_SINC2 (2 << DFSDM_FLTFCR_FORD_SHIFT)
|
||||
# define DFSDM_FLTFCR_FORD_SINC3 (3 << DFSDM_FLTFCR_FORD_SHIFT)
|
||||
# define DFSDM_FLTFCR_FORD_SINC4 (4 << DFSDM_FLTFCR_FORD_SHIFT)
|
||||
# define DFSDM_FLTFCR_FORD_SINC5 (5 << DFSDM_FLTFCR_FORD_SHIFT)
|
||||
#define DFSDM_FLTFCR_IOSR_SHIFT (0) /* Bits 0-7: Integrator oversampling ratio) */
|
||||
#define DFSDM_FLTFCR_IOSR_MASK (0xff << DFSDM_FLTFCR_IOSR_SHIFT)
|
||||
# define DFSDM_FLTFCR_IOSR(n) ((n) << DFSDM_FLTFCR_IOSR_SHIFT) /* n=0..255 */
|
||||
|
||||
/* DFSDM data register for injected group (DFSDM_FLTxJDATAR) */
|
||||
|
||||
#define DFSDM_FLTJDATAR_JDATACH_SHIFT (0) /* Bits 0-3: Injected channel most recently converted */
|
||||
#define DFSDM_FLTJDATAR_JDATACH_MASK (7 << DFSDM_FLTJDATAR_JDATACH_SHIFT)
|
||||
#define DFSDM_FLTJDATAR_JDATA_SHIFT (8) /* Bits 8-23: Injected group conversion data */
|
||||
#define DFSDM_FLTJDATAR_JDATA_MASK (0xffffff << DFSDM_FLTJDATAR_JDATA_SHIFT)
|
||||
|
||||
/* DFSDM data register for the regular channel (DFSDM_FLTxRDATAR) */
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX)
|
||||
# define DFSDM_FLTRDATAR_RDATACH_SHIFT (0) /* Bits 0-3: channel most recently converted */
|
||||
# define DFSDM_FLTRDATAR_RDATACH_MASK (7 << DFSDM_FLTRDATAR_RDATACH_SHIFT)
|
||||
#endif
|
||||
#define DFSDM_FLTRDATAR_RPEND (1 << 4 /* Bit 4: Regular channel has pending data */
|
||||
#define DFSDM_FLTRDATAR_RDATA_SHIFT (8) /* Bits 8-23: channel conversion data */
|
||||
#define DFSDM_FLTRDATAR_RDATA_MASK (0xffffff << DFSDM_FLTRDATAR_RDATA_SHIFT)
|
||||
|
||||
/* DFSDM analog watchdog high threshold register (DFSDM_FLTxAWHTR) */
|
||||
|
||||
#define DFSDM_AWHTR_BKAWH_SHIFT (0) /* Bits 0-3: Break signal assignment to analog watchdog high threshold event */
|
||||
#define DFSDM_AWHTR_BKAWH_MASK (0xf << DFSDM_AWHTR_BKAWH_SHIFT)
|
||||
/* Bits 4-7: Reserved */
|
||||
#define DFSDM_AWHTR_AWHT_SHIFT (8) /* Bits 8-31: Analog watchdog higher threshold */
|
||||
#define DFSDM_AWHTR_AWHT_MASK (0xffffff << DFSDM_AWHTR_AWHT_SHIFT)
|
||||
|
||||
/* DFSDM analog watchdog low threshold register (DFSDM_FLTxAWLTR) */
|
||||
|
||||
#define DFSDM_AWLTR_BKAWL_SHIFT (0) /* Bits 0-3: Break signal assignment to analog watchdog low threshold event */
|
||||
#define DFSDM_AWLTR_BKAWL_MASK (0xf << DFSDM_AWLTR_BKAWL_SHIFT)
|
||||
/* Bits 4-7: Reserved */
|
||||
#define DFSDM_AWLTR_AWLT_SHIFT (8) /* Bits 8-31: Analog watchdog lower threshold */
|
||||
#define DFSDM_AWLTR_AWLT_MASK (0xffffff << DFSDM_AWLTR_AWLT_SHIFT)
|
||||
|
||||
/* DFSDM analog watchdog status register (DFSDM_FLTxAWSR) */
|
||||
|
||||
#define DFSDM_AWSR_AWLTF_SHIFT (0) /* Bits 0-7: Analog watchdog low threshold flag */
|
||||
#define DFSDM_AWSR_AWLTF_MASK (0xff << DFSDM_AWSR_AWLTF_SHIFT)
|
||||
#define DFSDM_AWSR_AWHTF_SHIFT (8) /* Bits 8-15: Analog watchdog high threshold flag */
|
||||
#define DFSDM_AWSR_AWHTF_MASK (0xff << DFSDM_AWSR_AWHTF_SHIFT)
|
||||
|
||||
/* DFSDM analog watchdog clear flag register (DFSDM_FLTxAWCFR) */
|
||||
|
||||
#define DFSDM_AWCSR_CLRAWLTF_SHIFT (0) /* Bits 0-7: Clear analog watchdog low threshold flag */
|
||||
#define DFSDM_AWCSR_CLRAWLTF_MASK (0xff << DFSDM_AWCSR_CLRAWLTF_SHIFT)
|
||||
#define DFSDM_AWCSR_CLRAWHTF_SHIFT (8) /* Bits 8-15: Clear analog watchdog high threshold flag */
|
||||
#define DFSDM_AWCSR_CLRAWHTF_MASK (0xff << DFSDM_AWCSR_CLRAWHTF_SHIFT)
|
||||
|
||||
/* DFSDM Extremes detector maximum register (DFSDM_FLTxEXMAX) */
|
||||
|
||||
#define DFSDM_EXMAX_EXMAXCH_SHIFT (0) /* Bits 0-1: Extremes detector maximum data channel */
|
||||
#define DFSDM_EXMAX_EXMAXCH_MASK (7 << DFSDM_EXMAX_EXMAXCH_SHIFT)
|
||||
#define DFSDM_EXMAX_EXMAX_SHIFT (8) /* Bits 8-31: Extremes detector maximum value */
|
||||
#define DFSDM_EXMAX_EXMAX_MASK (0xffffff << DFSDM_EXMAX_EXMAX_SHIFT)
|
||||
|
||||
/* DFSDM Extremes detector minimum register (DFSDM_FLTxEXMIN) */
|
||||
|
||||
#define DFSDM_EXMIN_EXMINCH_SHIFT (0) /* Bits 0-1: Extremes detector minimum data channel */
|
||||
#define DFSDM_EXMIN_EXMINCH_MASK (7 << DFSDM_EXMIN_EXMINCH_SHIFT)
|
||||
#define DFSDM_EXMIN_EXMIN_SHIFT (8) /* Bits 8-31: Extremes detector minimum value */
|
||||
#define DFSDM_EXMIN_EXMIN_MASK (0xffffff << DFSDM_EXMIN_EXMIN_SHIFT)
|
||||
|
||||
/* DFSDM conversion timer register (DFSDM_FLTxCNVTIMR) */
|
||||
|
||||
#define DFSDM_CNVTIMR_CNVCNT_SHIFT (4) /* Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK */
|
||||
#define DFSDM_CNVTIMR_CNVCNT_MASK (~0xfu)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_DFSDM_H */
|
||||
@ -54,29 +54,30 @@
|
||||
#define STM32L4_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32L4_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
|
||||
/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5
|
||||
* TIM3 and 4 are 16-bit
|
||||
* TIM2 and 5 are 32-bit
|
||||
/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17.
|
||||
* TIM3 and 4 are 16-bit.
|
||||
* TIM2 and 5 are 32-bit.
|
||||
* TIM15, 16 and 17 are 16-bit.
|
||||
*/
|
||||
|
||||
#define STM32L4_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32L4_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit, TIM2-5 only) */
|
||||
#define STM32L4_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5 only) */
|
||||
#define STM32L4_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32L4_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */
|
||||
#define STM32L4_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32L4_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32L4_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32L4_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit) */
|
||||
#define STM32L4_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit, TIM2-5 only) */
|
||||
#define STM32L4_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */
|
||||
#define STM32L4_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */
|
||||
#define STM32L4_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */
|
||||
#define STM32L4_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit* or 32-bit STM3240 TIM2 and 5 only) */
|
||||
#define STM32L4_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32L4_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32L4_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
#define STM32L4_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit STM3240 TIM2/5 only) */
|
||||
#define STM32L4_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 or STM2 F3 TIM15 only) */
|
||||
#define STM32L4_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 only) */
|
||||
#define STM32L4_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 only) */
|
||||
#define STM32L4_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit, TIM2-5 only) */
|
||||
#define STM32L4_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit, TIM2-5 only) */
|
||||
#define STM32L4_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32L4_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32L4_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */
|
||||
#define STM32L4_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */
|
||||
#define STM32L4_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */
|
||||
#define STM32L4_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32L4_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
#define STM32L4_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */
|
||||
#define STM32L4_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */
|
||||
|
||||
@ -185,9 +186,10 @@
|
||||
#define STM32L4_TIM8_OR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR2_OFFSET)
|
||||
#define STM32L4_TIM8_OR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR3_OFFSET)
|
||||
|
||||
/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA.
|
||||
/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17.
|
||||
* TIM3 and 4 are 16-bit.
|
||||
* TIM2 and 5 are 32-bit
|
||||
* TIM2 and 5 are 32-bit.
|
||||
* TIM15, 16 and 17 are 16-bit.
|
||||
*/
|
||||
|
||||
#define STM32L4_TIM2_CR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CR1_OFFSET)
|
||||
@ -292,7 +294,6 @@
|
||||
#define STM32L4_TIM16_SR (STM32L4_TIM16_BASE+STM32L4_GTIM_SR_OFFSET)
|
||||
#define STM32L4_TIM16_EGR (STM32L4_TIM16_BASE+STM32L4_GTIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM16_CCMR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CCMR1_OFFSET)
|
||||
#define STM32L4_TIM16_CCMR2 (STM32L4_TIM16_BASE+STM32L4_GTIM_CCMR2_OFFSET)
|
||||
#define STM32L4_TIM16_CCER (STM32L4_TIM16_BASE+STM32L4_GTIM_CCER_OFFSET)
|
||||
#define STM32L4_TIM16_CNT (STM32L4_TIM16_BASE+STM32L4_GTIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM16_PSC (STM32L4_TIM16_BASE+STM32L4_GTIM_PSC_OFFSET)
|
||||
@ -310,7 +311,6 @@
|
||||
#define STM32L4_TIM17_SR (STM32L4_TIM17_BASE+STM32L4_GTIM_SR_OFFSET)
|
||||
#define STM32L4_TIM17_EGR (STM32L4_TIM17_BASE+STM32L4_GTIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM17_CCMR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CCMR1_OFFSET)
|
||||
#define STM32L4_TIM17_CCMR2 (STM32L4_TIM17_BASE+STM32L4_GTIM_CCMR2_OFFSET)
|
||||
#define STM32L4_TIM17_CCER (STM32L4_TIM17_BASE+STM32L4_GTIM_CCER_OFFSET)
|
||||
#define STM32L4_TIM17_CNT (STM32L4_TIM17_BASE+STM32L4_GTIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM17_PSC (STM32L4_TIM17_BASE+STM32L4_GTIM_PSC_OFFSET)
|
||||
@ -706,7 +706,7 @@
|
||||
# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
|
||||
# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
|
||||
# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
|
||||
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
|
||||
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */
|
||||
#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
|
||||
#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */
|
||||
#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */
|
||||
@ -885,15 +885,15 @@
|
||||
#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */
|
||||
#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */
|
||||
|
||||
/* Event generation register (TIM2-5 and TIM9-14) */
|
||||
/* Event generation register (TIM2-5, TIM15-17) */
|
||||
|
||||
#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */
|
||||
#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */
|
||||
#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */
|
||||
#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM2-5,15 only) */
|
||||
#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */
|
||||
#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */
|
||||
#define GTIM_EGR_COMIG (1 << 5) /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */
|
||||
#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */
|
||||
#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,16-17 only) */
|
||||
#define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */
|
||||
|
||||
/* Capture/compare mode register 1 - Output compare mode (TIM2-5) */
|
||||
@ -1057,7 +1057,7 @@
|
||||
# define GTIM_BDTR_LOCKOFF (0 << GTIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
|
||||
# define GTIM_BDTR_LOCK1 (1 << GTIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
|
||||
# define GTIM_BDTR_LOCK2 (2 << GTIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
|
||||
# define GTIM_BDTR_LOCK3 (3 << GTIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
|
||||
# define GTIM_BDTR_LOCK3 (3 << GTIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */
|
||||
#define GTIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
|
||||
#define GTIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */
|
||||
#define GTIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */
|
||||
|
||||
@ -344,8 +344,8 @@
|
||||
|
||||
/* DFSDM */
|
||||
|
||||
#define DMACHAN_DFSDM1_FLT0 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0)
|
||||
#define DMACHAN_DFSDM1_FLT1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0)
|
||||
#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0)
|
||||
#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0)
|
||||
|
||||
/* I2C */
|
||||
|
||||
|
||||
@ -386,7 +386,11 @@ uint16_t stm32l4_dac1_dmabuffer[CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE];
|
||||
static struct stm32_chan_s g_dac1priv =
|
||||
{
|
||||
.intf = 0,
|
||||
#ifdef CONFIG_STM32L4_DAC1_OUTPUT_ADC
|
||||
.pin = 0xffffffffU,
|
||||
#else
|
||||
.pin = GPIO_DAC1_OUT,
|
||||
#endif
|
||||
.dro = STM32L4_DAC_DHR12R1,
|
||||
.cr = STM32L4_DAC_CR,
|
||||
#ifdef CONFIG_STM32L4_DAC1_DMA
|
||||
@ -419,7 +423,11 @@ uint16_t stm32l4_dac2_dmabuffer[CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE];
|
||||
static struct stm32_chan_s g_dac2priv =
|
||||
{
|
||||
.intf = 1,
|
||||
#ifdef CONFIG_STM32L4_DAC2_OUTPUT_ADC
|
||||
.pin = 0xffffffffU,
|
||||
#else
|
||||
.pin = GPIO_DAC2_OUT,
|
||||
#endif
|
||||
.dro = STM32L4_DAC_DHR12R2,
|
||||
.cr = STM32L4_DAC_CR,
|
||||
#ifdef CONFIG_STM32L4_DAC2_DMA
|
||||
@ -1011,7 +1019,10 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
|
||||
* should first be configured to analog (AIN)".
|
||||
*/
|
||||
|
||||
stm32l4_configgpio(chan->pin);
|
||||
if (chan->pin != 0xffffffffU)
|
||||
{
|
||||
stm32l4_configgpio(chan->pin);
|
||||
}
|
||||
|
||||
/* DAC channel configuration:
|
||||
*
|
||||
@ -1036,24 +1047,14 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
|
||||
/* Enable output buffer or route DAC output to on-chip peripherals (ADC) */
|
||||
|
||||
clearbits = DAC_MCR_MODE1_MASK;
|
||||
#if defined(CONFIG_STM32L4_DAC1_OUTPUT_ADC)
|
||||
if (chan->intf == 0)
|
||||
{
|
||||
setbits = DAC_MCR_MODE_IN;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#if defined(CONFIG_STM32L4_DAC2_OUTPUT_ADC)
|
||||
if (chan->intf == 1)
|
||||
{
|
||||
setbits = DAC_MCR_MODE_IN;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if (chan->pin != 0xffffffffU)
|
||||
{
|
||||
setbits = DAC_MCR_MODE_EXTBUF;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
setbits = DAC_MCR_MODE_IN;
|
||||
}
|
||||
stm32l4_dac_modify_mcr(chan, clearbits, setbits);
|
||||
|
||||
#ifdef HAVE_DMA
|
||||
|
||||
1789
arch/arm/src/stm32l4/stm32l4_dfsdm.c
Normal file
1789
arch/arm/src/stm32l4/stm32l4_dfsdm.c
Normal file
File diff suppressed because it is too large
Load Diff
337
arch/arm/src/stm32l4/stm32l4_dfsdm.h
Normal file
337
arch/arm/src/stm32l4/stm32l4_dfsdm.h
Normal file
@ -0,0 +1,337 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32L4/stm32l4_dfsdm.h
|
||||
*
|
||||
* Copyright (C) 2017 Haltian Ltd. All rights reserved.
|
||||
* Authors: Juha Niskanen <juha.niskanen@haltian.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_DFSDM_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_STM32L4_DFSDM_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include "chip.h"
|
||||
#include "chip/stm32l4_dfsdm.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
/* Timer devices may be used for different purposes. One special purpose is to
|
||||
* control periodic ADC sampling. If CONFIG_STM32L4_TIMn is defined then
|
||||
* CONFIG_STM32L4_TIMn_DFSDM must also be defined to indicate that timer "n" is
|
||||
* intended to be used for that purpose. Timers 1,3,6 and 16 may be used on
|
||||
* STM32L4X3, while STM32L4X6 adds support for timers 4,7 and 8 as well.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_STM32L4_TIM1
|
||||
# undef CONFIG_STM32L4_TIM1_DFSDM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32L4_TIM3
|
||||
# undef CONFIG_STM32L4_TIM3_DFSDM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32L4_TIM4
|
||||
# undef CONFIG_STM32L4_TIM4_DFSDM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32L4_TIM6
|
||||
# undef CONFIG_STM32L4_TIM6_DFSDM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32L4_TIM7
|
||||
# undef CONFIG_STM32L4_TIM7_DFSDM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32L4_TIM8
|
||||
# undef CONFIG_STM32L4_TIM8_DFSDM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32L4_TIM16
|
||||
# undef CONFIG_STM32L4_TIM16_DFSDM
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_DFSDM)
|
||||
|
||||
/* DMA support */
|
||||
|
||||
#undef DFSDM_HAVE_DMA
|
||||
#if defined(CONFIG_STM32L4_DFSDM1_DMA)
|
||||
# define DFSDM_HAVE_DMA 1
|
||||
#endif
|
||||
|
||||
/* Timer configuration: If a timer trigger is specified, then get
|
||||
* information about the timer.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32L4_TIM1_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM1_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
|
||||
#elif defined(CONFIG_STM32L4_TIM3_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM3_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
|
||||
#elif defined(CONFIG_STM32L4_TIM4_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM4_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
|
||||
#elif defined(CONFIG_STM32L4_TIM6_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM6_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
|
||||
#elif defined(CONFIG_STM32L4_TIM7_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM7_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM7_CLKIN
|
||||
#elif defined(CONFIG_STM32L4_TIM8_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM8_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
|
||||
#elif defined(CONFIG_STM32L4_TIM16_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM16_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM16_CLKIN
|
||||
#else
|
||||
# undef DFSDM_HAVE_TIMER
|
||||
#endif
|
||||
|
||||
#ifdef DFSDM_HAVE_TIMER
|
||||
# ifndef CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY
|
||||
# error "CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY not defined"
|
||||
# endif
|
||||
# ifndef CONFIG_STM32L4_DFSDM_TIMTRIG
|
||||
# error "CONFIG_STM32L4_DFSDM_TIMTRIG not defined"
|
||||
# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* NOTE: The following assumes that all possible combinations of timers and
|
||||
* values are support JEXTSEL. That is not so and it varies from one STM32
|
||||
* to another. But this (wrong) assumptions keeps the logic as simple as
|
||||
* possible. If unsupported combination is used, an error will show up
|
||||
* later during compilation although it may be difficult to track it back
|
||||
* to this simplification.
|
||||
*/
|
||||
|
||||
#define DFSDM_JEXTSEL_T1CC1 DFSDM_FLTCR1_JEXTSEL_T1CC1
|
||||
#define DFSDM_JEXTSEL_T1CC2 DFSDM_FLTCR1_JEXTSEL_T1CC2
|
||||
#define DFSDM_JEXTSEL_T1CC3 DFSDM_FLTCR1_JEXTSEL_T1CC3
|
||||
#define DFSDM_JEXTSEL_T1CC4 DFSDM_FLTCR1_JEXTSEL_T1CC4
|
||||
#define DFSDM_JEXTSEL_T1TRGO DFSDM_FLTCR1_JEXTSEL_T1TRGO
|
||||
#define DFSDM_JEXTSEL_T1TRGO2 DFSDM_FLTCR1_JEXTSEL_T1TRGO2
|
||||
|
||||
#define DFSDM_JEXTSEL_T3CC1 DFSDM_FLTCR1_JEXTSEL_T3CC1
|
||||
#define DFSDM_JEXTSEL_T3CC2 DFSDM_FLTCR1_JEXTSEL_T3CC2
|
||||
#define DFSDM_JEXTSEL_T3CC3 DFSDM_FLTCR1_JEXTSEL_T3CC3
|
||||
#define DFSDM_JEXTSEL_T3CC4 DFSDM_FLTCR1_JEXTSEL_T3CC4
|
||||
#define DFSDM_JEXTSEL_T3TRGO DFSDM_FLTCR1_JEXTSEL_T3TRGO
|
||||
|
||||
#define DFSDM_JEXTSEL_T4CC1 DFSDM_FLTCR1_JEXTSEL_T4CC1
|
||||
#define DFSDM_JEXTSEL_T4CC2 DFSDM_FLTCR1_JEXTSEL_T4CC2
|
||||
#define DFSDM_JEXTSEL_T4CC3 DFSDM_FLTCR1_JEXTSEL_T4CC3
|
||||
#define DFSDM_JEXTSEL_T4CC4 DFSDM_FLTCR1_JEXTSEL_T4CC4
|
||||
#define DFSDM_JEXTSEL_T4TRGO DFSDM_FLTCR1_JEXTSEL_T4TRGO
|
||||
|
||||
#define DFSDM_JEXTSEL_T6CC1 DFSDM_FLTCR1_JEXTSEL_T6CC1
|
||||
#define DFSDM_JEXTSEL_T6CC2 DFSDM_FLTCR1_JEXTSEL_T6CC2
|
||||
#define DFSDM_JEXTSEL_T6CC3 DFSDM_FLTCR1_JEXTSEL_T6CC3
|
||||
#define DFSDM_JEXTSEL_T6CC4 DFSDM_FLTCR1_JEXTSEL_T6CC4
|
||||
#define DFSDM_JEXTSEL_T6TRGO DFSDM_FLTCR1_JEXTSEL_T6TRGO
|
||||
|
||||
#define DFSDM_JEXTSEL_T7CC1 DFSDM_FLTCR1_JEXTSEL_T7CC1
|
||||
#define DFSDM_JEXTSEL_T7CC2 DFSDM_FLTCR1_JEXTSEL_T7CC2
|
||||
#define DFSDM_JEXTSEL_T7CC3 DFSDM_FLTCR1_JEXTSEL_T7CC3
|
||||
#define DFSDM_JEXTSEL_T7CC4 DFSDM_FLTCR1_JEXTSEL_T7CC4
|
||||
#define DFSDM_JEXTSEL_T7TRGO DFSDM_FLTCR1_JEXTSEL_T7TRGO
|
||||
|
||||
#define DFSDM_JEXTSEL_T8CC1 DFSDM_FLTCR1_JEXTSEL_T8CC1
|
||||
#define DFSDM_JEXTSEL_T8CC2 DFSDM_FLTCR1_JEXTSEL_T8CC2
|
||||
#define DFSDM_JEXTSEL_T8CC3 DFSDM_FLTCR1_JEXTSEL_T8CC3
|
||||
#define DFSDM_JEXTSEL_T8CC4 DFSDM_FLTCR1_JEXTSEL_T8CC4
|
||||
#define DFSDM_JEXTSEL_T8TRGO DFSDM_FLTCR1_JEXTSEL_T8TRGO
|
||||
#define DFSDM_JEXTSEL_T8TRGO2 DFSDM_FLTCR1_JEXTSEL_T8TRGO2
|
||||
|
||||
#define DFSDM_JEXTSEL_T16CC1 DFSDM_FLTCR1_JEXTSEL_T16CC1
|
||||
#define DFSDM_JEXTSEL_T16CC2 DFSDM_FLTCR1_JEXTSEL_T16CC2
|
||||
#define DFSDM_JEXTSEL_T16CC3 DFSDM_FLTCR1_JEXTSEL_T16CC3
|
||||
#define DFSDM_JEXTSEL_T16CC4 DFSDM_FLTCR1_JEXTSEL_T16CC4
|
||||
#define DFSDM_JEXTSEL_T16TRGO DFSDM_FLTCR1_JEXTSEL_T16TRGO
|
||||
|
||||
#if defined(CONFIG_STM32L4_TIM1_DFSDM)
|
||||
# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC1
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC2
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC3
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC4
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1TRGO
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 5
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32L4_TIM3_DFSDM)
|
||||
# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC1
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC2
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC3
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC4
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32L4_TIM4_DFSDM)
|
||||
# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC1
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC2
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC3
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC4
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32L4_TIM6_DFSDM)
|
||||
# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC1
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC2
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC3
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC4
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32L4_TIM7_DFSDM)
|
||||
# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC1
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC2
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC3
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC4
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32L4_TIM8_DFSDM)
|
||||
# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC1
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC2
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC3
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC4
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8TRGO
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 5
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32L4_TIM16_DFSDM)
|
||||
# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC1
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC2
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC3
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC4
|
||||
# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
|
||||
# define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32l4_dfsdm_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the DFSDM.
|
||||
*
|
||||
* Input Parameters:
|
||||
* intf - Could be {0,1,2,3} for DFSDM FLT0, FLT1, FLT2, FLT3
|
||||
* chanlist - The list of channels
|
||||
* nchannels - Number of channels
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid ADC device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct adc_dev_s;
|
||||
struct adc_dev_s *stm32l4_dfsdm_initialize(int intf,
|
||||
FAR const uint8_t *chanlist,
|
||||
int nchannels);
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* CONFIG_STM32L4_DFSDM */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DFSDM_H */
|
||||
@ -126,9 +126,11 @@ enum stm32l4_chanmode_e
|
||||
struct stm32l4_pwmchan_s
|
||||
{
|
||||
uint8_t channel; /* Timer output channel: {1,..4} */
|
||||
uint32_t pincfg; /* Output pin configuration */
|
||||
enum stm32l4_chanmode_e mode;
|
||||
uint32_t npincfg; /* Complementary output pin configuration (only TIM1/8 CH1-3)*/
|
||||
uint32_t pincfg; /* Output pin configuration */
|
||||
uint32_t npincfg; /* Complementary output pin configuration
|
||||
* (only TIM1,8 CH1-3 and TIM15,16,17 CH1)
|
||||
*/
|
||||
};
|
||||
|
||||
/* This structure represents the state of one PWM timer */
|
||||
@ -136,8 +138,8 @@ struct stm32l4_pwmchan_s
|
||||
struct stm32l4_pwmtimer_s
|
||||
{
|
||||
FAR const struct pwm_ops_s *ops; /* PWM operations */
|
||||
uint8_t timid; /* Timer ID {1,...,17} */
|
||||
struct stm32l4_pwmchan_s channels[PWM_NCHANNELS];
|
||||
uint8_t timid; /* Timer ID {1,...,17} */
|
||||
uint8_t timtype; /* See the TIMTYPE_* definitions */
|
||||
enum stm32l4_timmode_e mode;
|
||||
#ifdef CONFIG_PWM_PULSECOUNT
|
||||
@ -1106,7 +1108,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
|
||||
|
||||
ccenable |= ATIM_CCER_CC1E;
|
||||
|
||||
/* Conditionnaly enable the complementary output */
|
||||
/* Conditionally enable the complementary output */
|
||||
|
||||
if (compout)
|
||||
{
|
||||
@ -1136,7 +1138,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
|
||||
|
||||
ccenable |= ATIM_CCER_CC2E;
|
||||
|
||||
/* Conditionnaly enable the complementary output */
|
||||
/* Conditionally enable the complementary output */
|
||||
|
||||
if (compout)
|
||||
{
|
||||
@ -1166,7 +1168,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
|
||||
|
||||
ccenable |= ATIM_CCER_CC3E;
|
||||
|
||||
/* Conditionnaly enable the complementary output */
|
||||
/* Conditionally enable the complementary output */
|
||||
|
||||
if (compout)
|
||||
{
|
||||
@ -1284,7 +1286,8 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
|
||||
stm32l4pwm_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, bdtr);
|
||||
}
|
||||
else
|
||||
#if defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM15_PWM)
|
||||
#if defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \
|
||||
defined(CONFIG_STM32L4_TIM17_PWM)
|
||||
if (priv->timtype == TIMTYPE_COUNTUP16)
|
||||
{
|
||||
|
||||
|
||||
@ -491,14 +491,17 @@
|
||||
# define CONFIG_STM32L4_TIM1_CHANNEL1 1
|
||||
# define CONFIG_STM32L4_TIM1_CH1MODE CONFIG_STM32L4_TIM1_CHMODE
|
||||
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
|
||||
# define PWM_TIM1_CH1NCFG 0
|
||||
# elif CONFIG_STM32L4_TIM1_CHANNEL == 2
|
||||
# define CONFIG_STM32L4_TIM1_CHANNEL2 1
|
||||
# define CONFIG_STM32L4_TIM1_CH2MODE CONFIG_STM32L4_TIM1_CHMODE
|
||||
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
|
||||
# define PWM_TIM1_CH2NCFG 0
|
||||
# elif CONFIG_STM32L4_TIM1_CHANNEL == 3
|
||||
# define CONFIG_STM32L4_TIM1_CHANNEL3 1
|
||||
# define CONFIG_STM32L4_TIM1_CH3MODE CONFIG_STM32L4_TIM1_CHMODE
|
||||
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
|
||||
# define PWM_TIM1_CH3NCFG 0
|
||||
# elif CONFIG_STM32L4_TIM1_CHANNEL == 4
|
||||
# define CONFIG_STM32L4_TIM1_CHANNEL4 1
|
||||
# define CONFIG_STM32L4_TIM1_CH4MODE CONFIG_STM32L4_TIM1_CHMODE
|
||||
@ -611,14 +614,17 @@
|
||||
# define CONFIG_STM32L4_TIM8_CHANNEL1 1
|
||||
# define CONFIG_STM32L4_TIM8_CH1MODE CONFIG_STM32L4_TIM8_CHMODE
|
||||
# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT
|
||||
# define PWM_TIM8_CH1NCFG 0
|
||||
# elif CONFIG_STM32L4_TIM8_CHANNEL == 2
|
||||
# define CONFIG_STM32L4_TIM8_CHANNEL2 1
|
||||
# define CONFIG_STM32L4_TIM8_CH2MODE CONFIG_STM32L4_TIM8_CHMODE
|
||||
# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT
|
||||
# define PWM_TIM8_CH2NCFG 0
|
||||
# elif CONFIG_STM32L4_TIM8_CHANNEL == 3
|
||||
# define CONFIG_STM32L4_TIM8_CHANNEL3 1
|
||||
# define CONFIG_STM32L4_TIM8_CH3MODE CONFIG_STM32L4_TIM8_CHMODE
|
||||
# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT
|
||||
# define PWM_TIM8_CH3NCFG 0
|
||||
# elif CONFIG_STM32L4_TIM8_CHANNEL == 4
|
||||
# define CONFIG_STM32L4_TIM8_CHANNEL4 1
|
||||
# define CONFIG_STM32L4_TIM8_CH4MODE CONFIG_STM32L4_TIM8_CHMODE
|
||||
@ -635,6 +641,7 @@
|
||||
# define CONFIG_STM32L4_TIM15_CHANNEL1 1
|
||||
# define CONFIG_STM32L4_TIM15_CH1MODE CONFIG_STM32L4_TIM15_CHMODE
|
||||
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
|
||||
# define PWM_TIM15_CH1NCFG 0
|
||||
# elif CONFIG_STM32L4_TIM15_CHANNEL == 2
|
||||
# define CONFIG_STM32L4_TIM15_CHANNEL2 1
|
||||
# define CONFIG_STM32L4_TIM15_CH2MODE CONFIG_STM32L4_TIM15_CHMODE
|
||||
@ -651,6 +658,7 @@
|
||||
# define CONFIG_STM32L4_TIM16_CHANNEL1 1
|
||||
# define CONFIG_STM32L4_TIM16_CH1MODE CONFIG_STM32L4_TIM16_CHMODE
|
||||
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
|
||||
# define PWM_TIM16_CH1NCFG 0
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_STM32L4_TIM16_CHANNEL"
|
||||
# endif
|
||||
@ -663,6 +671,7 @@
|
||||
# define CONFIG_STM32L4_TIM17_CHANNEL1 1
|
||||
# define CONFIG_STM32L4_TIM17_CH1MODE CONFIG_STM32L4_TIM17_CHMODE
|
||||
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
|
||||
# define PWM_TIM17_CH1NCFG 0
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_STM32L4_TIM17_CHANNEL"
|
||||
# endif
|
||||
|
||||
@ -246,9 +246,11 @@ static void stm32l4_tim_reload_counter(FAR struct stm32l4_tim_dev_s *dev);
|
||||
static void stm32l4_tim_enable(FAR struct stm32l4_tim_dev_s *dev);
|
||||
static void stm32l4_tim_disable(FAR struct stm32l4_tim_dev_s *dev);
|
||||
static void stm32l4_tim_reset(FAR struct stm32l4_tim_dev_s *dev);
|
||||
#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\
|
||||
defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\
|
||||
defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG)
|
||||
#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \
|
||||
defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \
|
||||
defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \
|
||||
defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \
|
||||
defined(HAVE_TIM17_GPIOCONFIG)
|
||||
static void stm32l4_tim_gpioconfig(uint32_t cfg, stm32l4_tim_channel_t mode);
|
||||
#endif
|
||||
|
||||
@ -524,9 +526,11 @@ static void stm32l4_tim_reset(FAR struct stm32l4_tim_dev_s *dev)
|
||||
* Name: stm32l4_tim_gpioconfig
|
||||
************************************************************************************/
|
||||
|
||||
#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\
|
||||
defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\
|
||||
defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG)
|
||||
#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \
|
||||
defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \
|
||||
defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \
|
||||
defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \
|
||||
defined(HAVE_TIM17_GPIOCONFIG)
|
||||
static void stm32l4_tim_gpioconfig(uint32_t cfg, stm32l4_tim_channel_t mode)
|
||||
{
|
||||
/* TODO: Add support for input capture and bipolar dual outputs for TIM8 */
|
||||
@ -760,7 +764,7 @@ static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev,
|
||||
uint16_t ccmr_orig = 0;
|
||||
uint16_t ccmr_val = 0;
|
||||
uint16_t ccmr_mask = 0xff;
|
||||
uint16_t ccer_val = stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET);
|
||||
uint16_t ccer_val;
|
||||
uint8_t ccmr_offset = STM32L4_GTIM_CCMR1_OFFSET;
|
||||
|
||||
DEBUGASSERT(dev != NULL);
|
||||
@ -774,6 +778,7 @@ static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev,
|
||||
|
||||
/* Assume that channel is disabled and polarity is active high */
|
||||
|
||||
ccer_val = stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET);
|
||||
ccer_val &= ~(3 << (channel << 2));
|
||||
|
||||
/* This function is not supported on basic timers. To enable or
|
||||
|
||||
@ -534,6 +534,16 @@ static inline void rcc_enableccip(void)
|
||||
regval |= RCC_CCIPR_ADCSEL_SYSCLK;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_DFSDM1
|
||||
/* Select SYSCLK as DFSDM clock source */
|
||||
|
||||
/* TODO: not sure if this can be done on these MCUs.
|
||||
* RM0394 Rev 3, p. 525 is confused.
|
||||
*/
|
||||
|
||||
//regval |= RCC_CCIPR_DFSDMSEL_SYSCLK;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_CCIPR);
|
||||
}
|
||||
|
||||
|
||||
@ -563,6 +563,12 @@ static inline void rcc_enableccip(void)
|
||||
regval |= RCC_CCIPR_ADCSEL_SYSCLK;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_DFSDM1
|
||||
/* Select SYSCLK as DFSDM clock source */
|
||||
|
||||
regval |= RCC_CCIPR_DFSDMSEL_SYSCLK;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_CCIPR);
|
||||
}
|
||||
|
||||
|
||||
@ -608,6 +608,12 @@ static inline void rcc_enableccip(void)
|
||||
regval |= RCC_CCIPR_ADCSEL_SYSCLK;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_DFSDM1
|
||||
/* Select SYSCLK as DFSDM clock source */
|
||||
|
||||
regval |= RCC_CCIPR_DFSDMSEL_SYSCLK;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_CCIPR);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user