LPC17 Ethernet: Add support for the Micrel KSZ8041 PHY.
This commit is contained in:
Gregory Nutt
parent
201a024ef9
commit
391367e8ca
@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/lpc17xx/lpc17_ethernet.c
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*
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* Copyright (C) 2010-2014 Gregory Nutt. All rights reserved.
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* Copyright (C) 2010-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -183,6 +183,11 @@
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# define LPC17_PHYID1 MII_PHYID1_KS8721
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# define LPC17_PHYID2 MII_PHYID2_KS8721
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# define LPC17_HAVE_PHY 1
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#if defined(CONFIG_ETH0_PHY_KSZ8041)
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# define LPC17_PHYNAME "KSZ8041"
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# define LPC17_PHYID1 MII_PHYID1_KSZ8041
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# define LPC17_PHYID2 MII_PHYID2_KSZ8041
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# define LPC17_HAVE_PHY 1
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#elif defined(CONFIG_ETH0_PHY_DP83848C)
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# define LPC17_PHYNAME "DP83848C"
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# define LPC17_PHYID1 MII_PHYID1_DP83848C
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@ -2773,20 +2778,53 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
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priv->lp_mode = LPC17_10BASET_HD;
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lpc17_putreg(0, LPC17_ETH_SUPP);
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break;
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case KS8721_10BTCR_MODE_100BTHD: /* 100BASE-T half duplex */
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priv->lp_mode = LPC17_100BASET_HD;
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break;
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case KS8721_10BTCR_MODE_10BTFD: /* 10BASE-T full duplex */
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priv->lp_mode = LPC17_10BASET_FD;
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lpc17_putreg(0, LPC17_ETH_SUPP);
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break;
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case KS8721_10BTCR_MODE_100BTFD: /* 100BASE-T full duplex */
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priv->lp_mode = LPC17_100BASET_FD;
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break;
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default:
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ndbg("Unrecognized mode: %04x\n", phyreg);
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return -ENODEV;
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}
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#if defined(CONFIG_ETH0_PHY_KSZ8041)
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phyreg = lpc17_phyread(phyaddr, MII_KSZ8041_PHYCTRL2);
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switch (phyreg & MII_PHYCTRL2_MODE_MASK)
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{
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case MII_PHYCTRL2_MODE_10HDX: /* 10BASE-T half duplex */
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priv->lp_mode = LPC17_10BASET_HD;
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lpc17_putreg(0, LPC17_ETH_SUPP);
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break;
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case MII_PHYCTRL2_MODE_100HDX: /* 100BASE-T half duplex */
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priv->lp_mode = LPC17_100BASET_HD;
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break;
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case MII_PHYCTRL2_MODE_10FDX: /* 10BASE-T full duplex */
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priv->lp_mode = LPC17_10BASET_FD;
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lpc17_putreg(0, LPC17_ETH_SUPP);
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break;
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case MII_PHYCTRL2_MODE_100FDX: /* 100BASE-T full duplex */
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priv->lp_mode = LPC17_100BASET_FD;
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break;
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default:
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ndbg("Unrecognized mode: %04x\n", phyreg);
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return -ENODEV;
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}
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#elif defined(CONFIG_ETH0_PHY_DP83848C)
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phyreg = lpc17_phyread(phyaddr, MII_DP83848C_STS);
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@ -2797,19 +2835,24 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
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case 0x0000:
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priv->lp_mode = LPC17_100BASET_HD;
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break;
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case 0x0002:
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priv->lp_mode = LPC17_10BASET_HD;
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break;
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case 0x0004:
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priv->lp_mode = LPC17_100BASET_FD;
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break;
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case 0x0006:
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priv->lp_mode = LPC17_10BASET_FD;
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break;
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default:
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ndbg("Unrecognized mode: %04x\n", phyreg);
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return -ENODEV;
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}
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#elif defined(CONFIG_ETH0_PHY_LAN8720)
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{
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uint16_t advertise;
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@ -2856,6 +2899,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
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return -ENODEV;
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}
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}
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#else
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# warning "PHY Unknown: speed and duplex are bogus"
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#endif
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@ -293,6 +293,9 @@ config ETH0_PHY_AM79C874
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config ETH0_PHY_KS8721
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bool "Micrel KS8721 PHY"
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config ETH0_PHY_KSZ8041
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bool "Micrel KSZ8041 PHY"
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config ETH0_PHY_KSZ8051
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bool "Micrel KSZ8051 PHY"
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@ -339,6 +342,9 @@ config ETH1_PHY_AM79C874
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config ETH1_PHY_KS8721
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bool "Micrel KS8721 PHY"
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config ETH1_PHY_KSZ8041
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bool "Micrel KSZ8041 PHY"
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config ETH1_PHY_KSZ8051
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bool "Micrel KSZ8051 PHY"
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@ -110,6 +110,13 @@
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#define MII_KS8721_INTCS 0x1b /* Interrupt control/status register */
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#define MII_KS8721_10BTCR 0x1f /* 10BASE-TX PHY control register */
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/* Micrel KSZ8041: 0x15, 0x1b, 0x1e-0x1f */
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#define MII_KSZ8041_RXERR 0x15 /* RXERR Counter */
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#define MII_KSZ8041_INT 0x1b /* Interrupt Control/Status */
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#define MII_KSZ8041_PHYCTRL1 0x1e /* PHY Control 1 */
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#define MII_KSZ8041_PHYCTRL2 0x1f /* PHY Control 2 */
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/* Micrel KSZ8051: 0x11, 0x15-0x18, 0x1b, 0x1d-0x1f */
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#define MII_KSZ8051_AFEC1 0x11 /* AFE Control 1 */
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@ -499,7 +506,10 @@
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#define KS8721_10BTCR_PAIRSWAPD (1 << 13) /* Bit 13: Pairswap disable */
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/* KSZ8051/81-specific register bit settings ********************************/
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/* KSZ8051/81 MII ID1/2 register bits */
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/* KSZ8041/51/81 MII ID1/2 register bits */
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#define MII_PHYID1_KSZ8041 0x0022 /* ID1 value for Micrel KSZ8041 */
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#define MII_PHYID2_KSZ8041 0x1510 /* ID2 value for Micrel KSZ8041 */
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#define MII_PHYID1_KSZ8051 0x0022 /* ID1 value for Micrel KSZ8051 */
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#define MII_PHYID2_KSZ8051 0x1550 /* ID2 value for Micrel KSZ8051 */
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@ -511,7 +521,7 @@
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/* Bits 5-15: Reserved */
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#define KSZ8081_DRCTRL_PLLOFF (1 << 4) /* Bit 4: Turn PLL off in EDPD mode */
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/* Bits 0-3: Reserved */
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/* KSZ8051/81 Register 0x1b: Interrupt control/status */
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/* KSZ8041/51/81 Register 0x1b: Interrupt control/status */
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#define MII_KSZ80x1_INT_JEN (1 << 15) /* Jabber interrupt enable */
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#define MII_KSZ80x1_INT_REEN (1 << 14) /* Receive error interrupt enable */
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@ -531,6 +541,30 @@
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#define MII_KSZ80x1_INT_RF (1 << 1) /* Remote fault interrupt */
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#define MII_KSZ80x1_INT_LU (1 << 0) /* Link up interrupt */
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/* KSZ8041 Register 0x1e: PHY Control 1 -- To be provided */
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/* KSZ8041 Register 0x1e: PHY Control 2 */
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#define MII_PHYCTRL2_MDIX (1 << 15) /* Bit 15: Micrel/HP MDI/MDI-X state */
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#define MII_PHYCTRL2_MDIX_SEL (1 << 14) /* Bit 14: MDI/MDI-X select */
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#define MII_PHYCTRL2_PSDIS (1 << 13) /* Bit 13: Pair swap disable */
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#define MII_PHYCTRL2_ENERGYDET (1 << 12) /* Bit 12: Energy detect */
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#define MII_PHYCTRL2_FORCE (1 << 11) /* Bit 11: Force link */
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#define MII_PHYCTRL2_PWRSAVE (1 << 10) /* Bit 10: Power saving */
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#define MII_PHYCTRL2_INTLVL (1 << 9) /* Bit 9: Interrupt level */
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#define MII_PHYCTRL2_ENJABBER (1 << 8) /* Bit 8: Enable jabber */
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#define MII_PHYCTRL2_ANEGCOMP (1 << 7) /* Bit 7: Auto-negotiation complete */
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#define MII_PHYCTRL2_ENPAUSE (1 << 6) /* Bit 6: Enable pause */
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#define MII_PHYCTRL2_ISOLATE (1 << 5) /* Bit 5: PHY isolate */
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#define MII_PHYCTRL2_MODE_SHIFT (2) /* Bits 2-4: Operation mode */
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#define MII_PHYCTRL2_MODE_MASK (7 << MII_PHYCTRL2_MODE_SHIFT)
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# define MII_PHYCTRL2_MODE_BUSY (0 << MII_PHYCTRL2_MODE_SHIFT) /* Still in autonegotiation */
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# define MII_PHYCTRL2_MODE_10HDX (1 << MII_PHYCTRL2_MODE_SHIFT) /* 10Base-T half-duplex */
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# define MII_PHYCTRL2_MODE_100HDX (2 << MII_PHYCTRL2_MODE_SHIFT) /* 100Base-T half-duplex */
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# define MII_PHYCTRL2_MODE_10FDX (5 << MII_PHYCTRL2_MODE_SHIFT) /* 10Base-T full-duplex */
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# define MII_PHYCTRL2_MODE_100FDX (6 << MII_PHYCTRL2_MODE_SHIFT) /* 100Base-T full-duplex */
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#define MII_PHYCTRL2_SEQTEST (1 << 1) /* Bit 1: Enable SQE test */
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#define MII_PHYCTRL2_DISDS (1 << 0) /* Bit 1: Disable data scrambling */
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/* KSZ8051/81 Register 0x1e: PHY Control 1 */
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/* Bits 10-15: Reserved */
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#define MII_PHYCTRL1_ENPAUSE (1 << 9) /* Bit 9: Enable pause */
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