+
|
+
+
+ Atmel AT91SAM4L.
+ This port uses the Atmel SAM4L Xplained Pro development board.
+ This board features the ATSAM4LC4C MCU with 256KB of FLASH and 32KB of internal SRAM.
+
+
+
+ STATUS:
+ As of this writing, the basic port is code complete and fully verified configurations exist for the basic NuttX OS test and for the NuttShell NSH).
+ The first fully functional LM4F120 LaunchPad port was released in NuttX-6.28.
+
+
+ Memory Usage.
+ The ATSAM4LC4C comes in a 61004-pin package and has 256KB FLASH and 32KB of SRAM.
+ Below is the current memory usage for the NSH configuration (June 9, 2013).
+ This is not a minimal implementation, but a full-featured NSH configuration.
+
+
+ Static memory usage can be shown with size command:
+
+
+$ size nuttx
+ text data bss dec hex filename
+ 43572 122 2380 46074 b3fa nuttx
+
+
+ NuttX, the NSH application, and GCC libraries use 42.6KB of FLASH leaving 213.4B of FLASH (83.4%) free from additional application development.
+ Static SRAM usage is about 2.3KB (<7%) and leaves 29.7KB (92.7%) available for heap at runtime.
+
+ SRAM usage at run-time can be shown with the NSH free command.
+ This runtime memory usage includes the static memory usage plus all dynamic memory allocation for things like stacks and I/O buffers:
+
+NuttShell (NSH) NuttX-6.28
+nsh> free
+ total used free largest
+Mem: 29232 5920 23312 23312
+
+
+ You can see that 22.8KB (71.1%) of the SRAM heap is staill available for further application development while NSH is running.
+
+
+ |
+
+
|
diff --git a/arch/arm/src/armv7-m/nvic.h b/arch/arm/src/armv7-m/nvic.h
index e6d6f8e9e1..2d76e4e6b6 100644
--- a/arch/arm/src/armv7-m/nvic.h
+++ b/arch/arm/src/armv7-m/nvic.h
@@ -399,8 +399,8 @@
/* Interrrupt controller type (INCTCTL_TYPE) */
-#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 4-0: Number of interrupt intputs / 32 */
-#define NVIC_ICTR_INTLINESNUM_MASK (0x1f << NVIC_ICTR_INTLINESNUM_SHIFT)
+#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 0-3: Number of interrupt inputs / 32 - 1 */
+#define NVIC_ICTR_INTLINESNUM_MASK (15 << NVIC_ICTR_INTLINESNUM_SHIFT)
/* SysTick control and status register (SYSTICK_CTRL) */
diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c
index f212742114..dcb6a187c7 100644
--- a/arch/arm/src/sam34/sam_irq.c
+++ b/arch/arm/src/sam34/sam_irq.c
@@ -221,18 +221,51 @@ static inline void sam_prioritize_syscall(int priority)
static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
{
+ unsigned int extint = irq - SAM_IRQ_EXTINT;
+
DEBUGASSERT(irq >= SAM_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= SAM_IRQ_EXTINT)
{
- if (irq < SAM_IRQ_NIRQS)
+#if SAM_IRQ_NEXTINT <= 32
+ if (extint < SAM_IRQ_NEXTINT)
{
*regaddr = NVIC_IRQ0_31_ENABLE;
- *bit = 1 << (irq - SAM_IRQ_EXTINT);
+ *bit = 1 << extint;
}
else
+#elif SAM_IRQ_NEXTINT <= 64
+ if (extint < 32)
+ {
+ *regaddr = NVIC_IRQ0_31_ENABLE;
+ *bit = 1 << extint;
+ }
+ else if (extint < SAM_IRQ_NEXTINT)
+ {
+ *regaddr = NVIC_IRQ32_63_ENABLE;
+ *bit = 1 << (extint - 32);
+ }
+ else
+#elif SAM_IRQ_NEXTINT <= 96
+ if (extint < 32)
+ {
+ *regaddr = NVIC_IRQ0_31_ENABLE;
+ *bit = 1 << extint;
+ }
+ else if (extint < 64)
+ {
+ *regaddr = NVIC_IRQ32_63_ENABLE;
+ *bit = 1 << (extint - 32);
+ }
+ else if (extint < SAM_IRQ_NEXTINT)
+ {
+ *regaddr = NVIC_IRQ64_95_ENABLE;
+ *bit = 1 << (extint - 64);
+ }
+ else
+#endif
{
return ERROR; /* Invalid interrupt */
}
@@ -279,9 +312,32 @@ static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
void up_irqinitialize(void)
{
- /* Disable all interrupts */
+ uintptr_t regaddr;
+ int nintlines;
+ int i;
- putreg32(0, NVIC_IRQ0_31_ENABLE);
+ /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt
+ * lines that the NVIC supports, defined in groups of 32. That is,
+ * the total number of interrupt lines is up to (32*(INTLINESNUM+1)).
+ *
+ * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers
+ * 1 -> 64 " " " ", 2 enable registers, 16 priority registers
+ * 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers
+ * ...
+ */
+
+ nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1;
+
+ /* Disable all interrupts. There are nintlines interrupt enable
+ * registers.
+ */
+
+ for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE;
+ i > 0;
+ i--, regaddr += 4)
+ {
+ putreg32(0, regaddr);
+ }
/* Set up the vector table address.
*
@@ -291,24 +347,26 @@ void up_irqinitialize(void)
#if defined(CONFIG_ARCH_RAMVECTORS)
up_ramvec_initialize();
-#elif defined(CONFIG_STM32_DFU)
+#elif defined(CONFIG_SAM_BOOTLOADER)
putreg32((uint32_t)sam_vectors, NVIC_VECTAB);
#endif
- /* Set all interrrupts (and exceptions) to the default priority */
+ /* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
- putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
- putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
- putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
- putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
- putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
- putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
- putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
- putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
+ /* Now set all of the interrupt lines to the default priority. There are
+ * nintlines * 8 priority registers.
+ */
+
+ for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY;
+ i > 0;
+ i--, regaddr += 4)
+ {
+ putreg32(0, regaddr);
+ }
/* currents_regs is non-NULL only while processing an interrupt */
diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c
index 713326e07c..f2289d356d 100644
--- a/arch/arm/src/sam34/sam_serial.c
+++ b/arch/arm/src/sam34/sam_serial.c
@@ -1310,6 +1310,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
priv->imr &= ~UART_INT_TXRDY;
up_disableint(priv);
}
+
irqrestore(flags);
}
diff --git a/configs/sam4l-xplained/scripts/ld.script b/configs/sam4l-xplained/scripts/ld.script
index e908e7a3ee..7a225b9991 100755
--- a/configs/sam4l-xplained/scripts/ld.script
+++ b/configs/sam4l-xplained/scripts/ld.script
@@ -33,8 +33,8 @@
*
****************************************************************************/
-/* The ATSAM4LC4C has 256Kb of FLASH beginning at address 0x0000:0000 and
- * 32Kb of SRAM beginning at address 0x2000:0000
+/* The ATSAM4LC4C has 256KB of FLASH beginning at address 0x0000:0000 and
+ * 32KB of SRAM beginning at address 0x2000:0000
*/
MEMORY
|