diff --git a/arch/arm/include/samv7/same70_irq.h b/arch/arm/include/samv7/same70_irq.h index 9dbfe0c072..579e4b3158 100644 --- a/arch/arm/include/samv7/same70_irq.h +++ b/arch/arm/include/samv7/same70_irq.h @@ -54,7 +54,7 @@ #define SAM_PID_RSTC (1) /* Reset Controller */ #define SAM_PID_RTC (2) /* Real Time Clock */ #define SAM_PID_RTT (3) /* Real Time Timer */ -#define SAM_PID_WDT0 (4) /* Watchdog Timer 0 */ +#define SAM_PID_WDT (4) /* Watchdog Timer */ #define SAM_PID_PMC (5) /* Power Management Controller */ #define SAM_PID_EFC (6) /* Embedded Flash Controller */ #define SAM_PID_UART0 (7) /* Universal Asynchronous Receiver Transmitter 0 */ @@ -113,7 +113,7 @@ #define SAM_PID_PWM1 (60) /* Pulse Width Modulation Controller 1 */ #define SAM_PID_FPU (61) /* ARM Floating Point Unit interrupt */ #define SAM_PID_SDRAMC (62) /* SDRAM Controller */ -#define SAM_PID_WDT1 (63) /* Watchdog Timer 1 */ +#define SAM_PID_RSWDT (63) /* Reinforced Safety Watchdog Timer */ #define SAM_PID_CCW (64) /* ARM Cache ECC Warning */ #define SAM_PID_CCF (65) /* ARM Cache ECC Fault */ #define SAM_PID_EMACQ1 (66) /* EMAC Queue 1 Interrupt */ @@ -128,7 +128,7 @@ #define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */ #define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */ #define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */ -#define SAM_IRQ_WDT0 (SAM_IRQ_EXTINT+SAM_PID_WDT0) /* Watchdog Timer 0 */ +#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer */ #define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */ #define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EFC) /* Embedded Flash Controller */ #define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter 0 */ @@ -187,7 +187,7 @@ #define SAM_IRQ_PWM1 (SAM_IRQ_EXTINT+SAM_PID_PWM1) /* Pulse Width Modulation Controller 1 */ #define SAM_IRQ_FPU (SAM_IRQ_EXTINT+SAM_PID_FPU) /* ARM Floating Point Unit interrupt */ #define SAM_IRQ_SDRAMC (SAM_IRQ_EXTINT+SAM_PID_SDRAMC) /* SDRAM Controller */ -#define SAM_IRQ_WDT1 (SAM_IRQ_EXTINT+SAM_PID_WDT1) /* Watchdog Timer 1 */ +#define SAM_IRQ_RSWDT (SAM_IRQ_EXTINT+SAM_PID_RSWDT) /* Reinforced Safety Watchdog Timer */ #define SAM_IRQ_CCW (SAM_IRQ_EXTINT+SAM_PID_CCW) /* ARM Cache ECC Warning */ #define SAM_IRQ_CCF (SAM_IRQ_EXTINT+SAM_PID_CCF) /* ARM Cache ECC Fault */ #define SAM_IRQ_EMACQ1 (SAM_IRQ_EXTINT+SAM_PID_EMACQ1) /* EMAC Queue 1 Interrupt */ diff --git a/arch/arm/include/samv7/samv71_irq.h b/arch/arm/include/samv7/samv71_irq.h index ba504e8d8c..4077e6fdd1 100644 --- a/arch/arm/include/samv7/samv71_irq.h +++ b/arch/arm/include/samv7/samv71_irq.h @@ -54,7 +54,7 @@ #define SAM_PID_RSTC (1) /* Reset Controller */ #define SAM_PID_RTC (2) /* Real Time Clock */ #define SAM_PID_RTT (3) /* Real Time Timer */ -#define SAM_PID_WDT0 (4) /* Watchdog Timer 0 */ +#define SAM_PID_WDT (4) /* Watchdog Timer */ #define SAM_PID_PMC (5) /* Power Management Controller */ #define SAM_PID_EFC (6) /* Embedded Flash Controller */ #define SAM_PID_UART0 (7) /* Universal Asynchronous Receiver Transmitter 0 */ @@ -113,7 +113,7 @@ #define SAM_PID_PWM1 (60) /* Pulse Width Modulation Controller 1 */ #define SAM_PID_FPU (61) /* ARM Floating Point Unit interrupt */ #define SAM_PID_SDRAMC (62) /* SDRAM Controller */ -#define SAM_PID_WDT1 (63) /* Watchdog Timer 1 */ +#define SAM_PID_RSWDT (63) /* Reinforced Safetry Watchdog Timer */ #define SAM_PID_CCW (64) /* ARM Cache ECC Warning */ #define SAM_PID_CCF (65) /* ARM Cache ECC Fault */ #define SAM_PID_EMACQ1 (66) /* EMAC Queue 1 Interrupt */ @@ -128,7 +128,7 @@ #define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */ #define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */ #define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */ -#define SAM_IRQ_WDT0 (SAM_IRQ_EXTINT+SAM_PID_WDT0) /* Watchdog Timer 0 */ +#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer*/ #define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */ #define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EFC) /* Embedded Flash Controller */ #define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter 0 */ @@ -187,7 +187,7 @@ #define SAM_IRQ_PWM1 (SAM_IRQ_EXTINT+SAM_PID_PWM1) /* Pulse Width Modulation Controller 1 */ #define SAM_IRQ_FPU (SAM_IRQ_EXTINT+SAM_PID_FPU) /* ARM Floating Point Unit interrupt */ #define SAM_IRQ_SDRAMC (SAM_IRQ_EXTINT+SAM_PID_SDRAMC) /* SDRAM Controller */ -#define SAM_IRQ_WDT1 (SAM_IRQ_EXTINT+SAM_PID_WDT1) /* Watchdog Timer 1 */ +#define SAM_IRQ_RSWDT (SAM_IRQ_EXTINT+SAM_PID_RSWDT) /* Reinforced Safety Watchdog Timer */ #define SAM_IRQ_CCW (SAM_IRQ_EXTINT+SAM_PID_CCW) /* ARM Cache ECC Warning */ #define SAM_IRQ_CCF (SAM_IRQ_EXTINT+SAM_PID_CCF) /* ARM Cache ECC Fault */ #define SAM_IRQ_EMACQ1 (SAM_IRQ_EXTINT+SAM_PID_EMACQ1) /* EMAC Queue 1 Interrupt */ diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c index b6109e1c9b..c0c258eb16 100644 --- a/arch/arm/src/common/up_initialize.c +++ b/arch/arm/src/common/up_initialize.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include #include @@ -272,6 +273,12 @@ void up_initialize(void) (void)tun_initialize(); #endif +#ifdef CONFIG_NETDEV_TELNET + /* Initialize the Telnet session factory */ + + (void)telnet_initialize(); +#endif + /* Initialize USB -- device and/or host */ up_usbinitialize(); diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c index 54aa82d63b..39f72d63ff 100644 --- a/arch/arm/src/sama5/sam_udphs.c +++ b/arch/arm/src/sama5/sam_udphs.c @@ -969,11 +969,20 @@ static void sam_dma_wrsetup(struct sam_usbdev_s *priv, struct sam_ep_s *privep, if (remaining > DMA_MAX_FIFO_SIZE) { privreq->inflight = DMA_MAX_FIFO_SIZE; + privep->zlpneeded = false; } else #endif { privreq->inflight = remaining; + + /* If the size is an exact multple of full packets, then note if + * we need to send a zero length packet next. + */ + + privep->zlpneeded = + ((privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0 && + (remaining % privep->ep.maxpacket) == 0); } /* And perform the single DMA transfer. @@ -1223,9 +1232,19 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv, * the request. */ - if (nbytes >= privep->ep.maxpacket) + privep->zlpneeded = false; + if (nbytes > privep->ep.maxpacket) { - nbytes = privep->ep.maxpacket; + nbytes = privep->ep.maxpacket; + } + else if (nbytes == privep->ep.maxpacket) + { + /* If the size is exactly a full packet, then note if we need to + * send a zero length packet next. + */ + + privep->zlpneeded = + ((privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0); } /* This is the new number of bytes "in-flight" */ @@ -1352,26 +1371,6 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep) bytesleft = privreq->req.len - privreq->req.xfrd; if (bytesleft > 0) { - /* If the size is exactly a full packet, then note if we need to - * send a zero length packet next. - */ - - if (bytesleft == privep->ep.maxpacket && - (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) - { - /* Next time we get here, bytesleft will be zero and zlpneeded - * will be set. - */ - - privep->zlpneeded = true; - } - else - { - /* No zero packet is forthcoming (maybe later) */ - - privep->zlpneeded = false; - } - /* The way that we handle the transfer is going to depend on * whether or not this endpoint supports DMA. In either case * the endpoint state will transition to SENDING. @@ -2392,6 +2391,12 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno) /* This is an IN endpoint. Continuing processing the write * request. We must call sam_req_write in the IDLE state * with the number of bytes transferred in 'inflight' + * + * REVISIT: On the SAMV7, I found that you really need to + * wait for the TX completion interrupt before calling + * sam_req_write(). For the SAMV7, the logic here just + * enables that TX completion interrupt. The symptom of + * the problem was occassional missing zero-length packets. */ DEBUGASSERT(USB_ISEPIN(privep->ep.eplog)); @@ -2451,7 +2456,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno) USB_ISEPOUT(privep->ep.eplog)); /* Get the number of bytes transferred from the DMA status. - * + * * BUFF_COUNT holds the number of untransmitted bytes. In this case, * BUFF_COUNT should not be zero. BUFF_COUNT was set to the * 'inflight' count when the DMA started so the difference will diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index eb16234ab4..94cdc0a792 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -445,6 +445,7 @@ config SAMV7_TC3 config SAMV7_TRNG bool "True Random Number Generator (TRNG)" default n + select ARCH_HAVE_RNG config SAMV7_TWIHS0 bool "Two-wire Interface 0 (TWIHS0)" @@ -534,13 +535,15 @@ config SAMV7_USART2 select ARCH_HAVE_USART2 select ARCH_HAVE_SERIAL_TERMIOS -config SAMV7_WDT0 - bool "Watchdog Timer (WDT0)" +config SAMV7_WDT + bool "Watchdog Timer (WDT)" default n + select WATCHDOG -config SAMV7_WDT1 - bool "Watchdog Timer (WDT1)" +config SAMV7_RSWDT + bool "Reinforced Safety Watchdog Timer (RSWDT)" default n + select WATCHDOG endmenu # SAMV7 Peripheral Selection @@ -573,6 +576,82 @@ config SAMV7_GPIOE_IRQ endif # SAMV7_GPIO_IRQ +if SAMV7_WDT || SAMV7_RSWDT + +menu "Watchdog Configuration" + +if SAMV7_WDT + +comment "Watchdog Configuration" + +config SAMV7_WDT_INTERRUPT + bool "Interrupt on timeout" + default n + ---help--- + The normal behavior is to reset everything when a watchdog timeout + occurs. An alternative behavior is to simply interrupt when the + timeout occurs. This setting enables that alternative behavior. + +config SAMV7_WDT_DEBUGHALT + bool "Halt on DEBUG" + default y if DEBUG + default n if !DEBUG + ---help--- + Halt the watchdog timer in the debug state + +config SAMV7_WDT_IDLEHALT + bool "Halt in IDLE" + default y + ---help--- + Halt the watchdog timer in the IDLE state + +config SAMV7_WDT_REGDEBUG + bool "Register level debug" + default n + depends on DEBUG + ---help--- + Enable low-level register debug output + +endif # SAMV7_WDT + +if SAMV7_RSWDT + +comment "Reinforced Safety Watchdog Configuration" + +config SAMV7_RSWDT_INTERRUPT + bool "Interrupt on timeout" + default n + ---help--- + The normal behavior is to reset everything when a watchdog timeout + occurs. An alternative behavior is to simply interrupt when the + timeout occurs. This setting enables that alternative behavior. + +config SAMV7_RSWDT_DEBUGHALT + bool "Halt on DEBUG" + default y if DEBUG + default n if !DEBUG + ---help--- + Halt the watchdog timer in the debug state + +config SAMV7_RSWDT_IDLEHALT + bool "Halt in IDLE" + default y + ---help--- + Halt the watchdog timer in the IDLE state + +config SAMV7_RSWDT_REGDEBUG + bool "Register level debug" + default n + depends on DEBUG + ---help--- + Enable low-level register debug output + +endif # SAMV7_RSWDT + +endmenu # Watchdog configuration + +endif # SAMV7_WDT || SAMV7_RSWDT + menuconfig SAMV7_PROGMEM bool "FLASH program memory" ---help--- diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs index 39af478376..79559c9380 100644 --- a/arch/arm/src/samv7/Make.defs +++ b/arch/arm/src/samv7/Make.defs @@ -136,6 +136,14 @@ ifeq ($(CONFIG_SAMV7_XDMAC),y) CHIP_CSRCS += sam_xdmac.c endif +ifeq ($(CONFIG_SAMV7_WDT),y) +CHIP_CSRCS += sam_wdt.c +endif + +ifeq ($(CONFIG_SAMV7_RSWDT),y) +CHIP_CSRCS += sam_rswdt.c +endif + ifeq ($(CONFIG_SAMV7_SPI_MASTER),y) CHIP_CSRCS += sam_spi.c endif @@ -189,6 +197,10 @@ ifeq ($(CONFIG_SAMV7_USBDEVHS),y) CHIP_CSRCS += sam_usbdevhs.c endif +ifeq ($(CONFIG_SAMV7_TRNG),y) +CHIP_CSRCS += sam_trng.c +endif + ifeq ($(CONFIG_SAMV7_PROGMEM),y) CHIP_CSRCS += sam_progmem.c endif diff --git a/arch/arm/src/samv7/chip/sam_trng.h b/arch/arm/src/samv7/chip/sam_trng.h new file mode 100644 index 0000000000..5f4d2ef3a1 --- /dev/null +++ b/arch/arm/src/samv7/chip/sam_trng.h @@ -0,0 +1,85 @@ +/************************************************************************************ + * arch/arm/src/samv7/chip/sam_trng.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TRNG_H +#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TRNG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/sam_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* TRNG Register Offsets ************************************************************/ + +#define SAM_TRNG_CR_OFFSET 0x0000 /* Control Register */ +#define SAM_TRNG_IER_OFFSET 0x0010 /* Interrupt Enable Register */ +#define SAM_TRNG_IDR_OFFSET 0x0014 /* Interrupt Disable Register */ +#define SAM_TRNG_IMR_OFFSET 0x0018 /* Interrupt Mask Register */ +#define SAM_TRNG_ISR_OFFSET 0x001c /* Interrupt Status Register */ +#define SAM_TRNG_ODATA_OFFSET 0x0050 /* Output Data Register */ + +/* TRNG Register Addresses **********************************************************/ + +#define SAM_TRNG_CR (SAM_TRNG_BASE+SAM_TRNG_CR_OFFSET) +#define SAM_TRNG_IER (SAM_TRNG_BASE+SAM_TRNG_IER_OFFSET) +#define SAM_TRNG_IDR (SAM_TRNG_BASE+SAM_TRNG_IDR_OFFSET) +#define SAM_TRNG_IMR (SAM_TRNG_BASE+SAM_TRNG_IMR_OFFSET) +#define SAM_TRNG_ISR (SAM_TRNG_BASE+SAM_TRNG_ISR_OFFSET) +#define SAM_TRNG_ODATA (SAM_TRNG_BASE+SAM_TRNG_ODATA_OFFSET) + +/* TRNG Register Bit Definitions ****************************************************/ + +/* Control Register */ + +#define TRNG_CR_ENABLE (1 << 0) /* Bit 0: 1=Enables the TRNG */ +# define TRNG_CR_DISABLE (0) /* Bit 0: 0=Disables the TRNG */ +#define TRNG_CR_KEY_SHIFT (8) /* Bits 8-31: Security key */ +#define TRNG_CR_KEY_MASK (0xffffff << TRNG_CR_KEY_SHIFT) +# define TRNG_CR_KEY (0x524e47 << TRNG_CR_KEY_SHIFT) /* RNG in ASCII */ + +/* Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, + * and Interrupt Status Register + */ + +#define TRNG_INT_DATRDY (1 << 0) /* Bit 0: Data ready */ + +/* Output Data Register (32-bit output data) */ + +#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TRNG_H */ diff --git a/arch/arm/src/samv7/chip/sam_wdt.h b/arch/arm/src/samv7/chip/sam_wdt.h index 9b298c443e..3a949c3c97 100644 --- a/arch/arm/src/samv7/chip/sam_wdt.h +++ b/arch/arm/src/samv7/chip/sam_wdt.h @@ -58,17 +58,17 @@ /* WDT register addresses ***************************************************************/ -/* WDT0: Legacy Watchdog Timer */ +/* WDT: Legacy Watchdog Timer */ -#define SAM_WDT0_CR (SAM_WDT0_BASE+SAM_WDT_CR_OFFSET) -#define SAM_WDT0_MR (SAM_WDT0_BASE+SAM_WDT_MR_OFFSET) -#define SAM_WDT0_SR (SAM_WDT0_BASE+SAM_WDT_SR_OFFSET) +#define SAM_WDT_CR (SAM_WDT_BASE+SAM_WDT_CR_OFFSET) +#define SAM_WDT_MR (SAM_WDT_BASE+SAM_WDT_MR_OFFSET) +#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET) -/* WDT1: Reinforced Safety Watchdog Timer */ +/* RSWDT: Reinforced Safety Watchdog Timer */ -#define SAM_WDT1_CR (SAM_WDT1_BASE+SAM_WDT_CR_OFFSET) -#define SAM_WDT1_MR (SAM_WDT1_BASE+SAM_WDT_MR_OFFSET) -#define SAM_WDT1_SR (SAM_WDT1_BASE+SAM_WDT_SR_OFFSET) +#define SAM_RSWDT_CR (SAM_RSWDT_BASE+SAM_WDT_CR_OFFSET) +#define SAM_RSWDT_MR (SAM_RSWDT_BASE+SAM_WDT_MR_OFFSET) +#define SAM_RSWDT_SR (SAM_RSWDT_BASE+SAM_WDT_SR_OFFSET) /* WDT register bit definitions *********************************************************/ /* Watchdog Timer Control Register */ @@ -76,8 +76,8 @@ #define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ #define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ #define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT) -# define WDT0_CR_KEY (0xa5 << WDT_CR_KEY_SHIFT) -# define WDT1_CR_KEY (0xc4 << WDT_CR_KEY_SHIFT) +# define WDT_CR_KEY (0xa5 << WDT_CR_KEY_SHIFT) +# define RSWDT_CR_KEY (0xc4 << WDT_CR_KEY_SHIFT) /* Watchdog Timer Mode Register */ @@ -87,20 +87,20 @@ # define WDT_MR_WDV(n) ((uint32_t)(n) << WDT_MR_WDV_SHIFT) #define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ #define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ -#define WDT1_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor (WDT1 only) */ +#define RSWDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor (RSWDT only) */ #define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ -#define WDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value (WDT0 only) */ +#define WDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value (WDT only) */ #define WDT_MR_WDD_MAX 0xfff #define WDT_MR_WDD_MASK (WDT_MR_WDD_MAX << WDT_MR_WDD_SHIFT) -# define WDT0_MR_WDD(n) ((uint32_t)(n) << WDT_MR_WDD_SHIFT) -# define WDT1_MR_WDD_ALLONES (0xfff << WDT_MR_WDD_SHIFT) +# define WDT_MR_WDD(n) ((uint32_t)(n) << WDT_MR_WDD_SHIFT) +# define RSWDT_MR_WDD_ALLONES (0xfff << WDT_MR_WDD_SHIFT) #define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */ #define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */ /* Watchdog Timer Status Register */ #define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ -#define WDT0_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error (WDT0 only) */ +#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error (WDT only) */ /**************************************************************************************** * Public Types diff --git a/arch/arm/src/samv7/chip/same70_memorymap.h b/arch/arm/src/samv7/chip/same70_memorymap.h index e6a21a3804..8bfa52ecc1 100644 --- a/arch/arm/src/samv7/chip/same70_memorymap.h +++ b/arch/arm/src/samv7/chip/same70_memorymap.h @@ -140,11 +140,11 @@ # define SAM_RSTC_BASE 0x400e1800 /* 0x400e1800-0x400e180f: Reset Controller (RSTC) */ # define SAM_SUPC_BASE 0x400e1810 /* 0x400e1810-0x400e182f: Supply Controller (SUPC) */ # define SAM_RTT_BASE 0x400e1830 /* 0x400e1830-0x400e184f: Real Time Timer (RTT) */ -# define SAM_WDT0_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer 0 (WDT0) */ +# define SAM_WDT_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer (WDT) */ # define SAM_RTC_BASE 0x400e1860 /* 0x400e1860-0x400e188f: Real Time Clock (RTC) */ # define SAM_GPBR_BASE 0x400e1890 /* 0x400e1890-0x400e18ff: GPBR */ # define SAM_SYSC_BASE 0x400e18e0 /* 0x400e1890-0x400e18ff: System Controller Common */ -# define SAM_WDT1_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Watchdog Timer 1 (WDT1) */ +# define SAM_RSWDT_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Reinforced Safety Watchdog Timer (RSWDT) */ #define SAM_UART2_BASE 0x400e1a00 /* 0x400e1a00-0x400e1bff: UART 2 */ #define SAM_UART3_BASE 0x400e1c00 /* 0x400e1c00-0x400e1dff: UART 3 */ #define SAM_UART4_BASE 0x400e1e00 /* 0x400e1e00-0x400e1fff: UART 4 */ diff --git a/arch/arm/src/samv7/chip/samv71_memorymap.h b/arch/arm/src/samv7/chip/samv71_memorymap.h index b7d55f1031..df8a5a11a8 100644 --- a/arch/arm/src/samv7/chip/samv71_memorymap.h +++ b/arch/arm/src/samv7/chip/samv71_memorymap.h @@ -140,11 +140,11 @@ # define SAM_RSTC_BASE 0x400e1800 /* 0x400e1800-0x400e180f: Reset Controller (RSTC) */ # define SAM_SUPC_BASE 0x400e1810 /* 0x400e1810-0x400e182f: Supply Controller (SUPC) */ # define SAM_RTT_BASE 0x400e1830 /* 0x400e1830-0x400e184f: Real Time Timer (RTT) */ -# define SAM_WDT0_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer 0 (WDT0) */ +# define SAM_WDT_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer(WDT) */ # define SAM_RTC_BASE 0x400e1860 /* 0x400e1860-0x400e188f: Real Time Clock (RTC) */ # define SAM_GPBR_BASE 0x400e1890 /* 0x400e1890-0x400e18ff: GPBR */ # define SAM_SYSC_BASE 0x400e18e0 /* 0x400e1890-0x400e18ff: System Controller Common */ -# define SAM_WDT1_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Watchdog Timer 1 (WDT1) */ +# define SAM_RSWDT_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Reinforced Safety Watchdog Timer (RSWDT) */ #define SAM_UART2_BASE 0x400e1a00 /* 0x400e1a00-0x400e1bff: UART 2 */ #define SAM_UART3_BASE 0x400e1c00 /* 0x400e1c00-0x400e1dff: UART 3 */ #define SAM_UART4_BASE 0x400e1e00 /* 0x400e1e00-0x400e1fff: UART 4 */ diff --git a/arch/arm/src/samv7/sam_clockconfig.c b/arch/arm/src/samv7/sam_clockconfig.c index f45304ce3e..c7bd6bbc9a 100644 --- a/arch/arm/src/samv7/sam_clockconfig.c +++ b/arch/arm/src/samv7/sam_clockconfig.c @@ -110,14 +110,14 @@ static inline void sam_efcsetup(void) static inline void sam_wdtsetup(void) { -#if !defined(CONFIG_SAMV7_WDT0) || \ - (defined(CONFIG_WDT0_ENABLED_ON_RESET) && defined(CONFIG_WDT0_DISABLE_ON_RESET)) - putreg32(WDT_MR_WDDIS, SAM_WDT0_MR); +#if !defined(CONFIG_SAMV7_WDT) || \ + (defined(CONFIG_WDT_ENABLED_ON_RESET) && defined(CONFIG_WDT_DISABLE_ON_RESET)) + putreg32(WDT_MR_WDDIS, SAM_WDT_MR); #endif -#if !defined(CONFIG_SAMV7_WDT1) || \ - (defined(CONFIG_WDT1_ENABLED_ON_RESET) && defined(CONFIG_WDT1_DISABLE_ON_RESET)) - putreg32(WDT_MR_WDDIS, SAM_WDT1_MR); +#if !defined(CONFIG_SAMV7_RSWDT) || \ + (defined(CONFIG_RSWDT_ENABLED_ON_RESET) && defined(CONFIG_RSWDT_DISABLE_ON_RESET)) + putreg32(WDT_MR_WDDIS, SAM_RSWDT_MR); #endif } diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c new file mode 100644 index 0000000000..0d92c40dfd --- /dev/null +++ b/arch/arm/src/samv7/sam_rswdt.c @@ -0,0 +1,705 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_rswdg.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "sam_wdt.h" + +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_SAMV7_RSWDT) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* The Watchdog Timer uses the Slow Clock divided by 128 to establish the + * maximum Watchdog period to be 16 seconds (with a typical Slow Clock of + * 32768 kHz). + */ + +#ifndef BOARD_SCLK_FREQUENCY +# define BOARD_SCLK_FREQUENCY 32768 +#endif + +#define RSWDT_FREQUENCY (BOARD_SCLK_FREQUENCY / 128) + +/* At 32768Hz, the maximum timeout value will be: + * + * 4096 / RSWDT_FREQUENCY = 256 seconds or 16,000 milliseconds + * + * And the minimum (non-zero) timeout would be: + * + * 1 / RSWDT_FREQUENCY = 3.9 milliseconds + */ + +#define RSWDT_MINTIMEOUT ((1000 + RSWDT_FREQUENCY - 1) / RSWDT_FREQUENCY) +#define RSWDT_MAXTIMEOUT ((4096 * 1000) / RSWDT_FREQUENCY) + +/* Debug ********************************************************************/ +/* Non-standard debug that may be enabled just for testing the watchdog + * driver. NOTE: that only lldbg types are used so that the output is + * immediately available. + */ + +#ifdef CONFIG_DEBUG_WATCHDOG +# define wddbg lldbg +# define wdvdbg llvdbg +#else +# define wddbg(x...) +# define wdvdbg(x...) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * well-known watchdog_lowerhalf_s structure. + */ + +struct sam_lowerhalf_s +{ + FAR const struct watchdog_ops_s *ops; /* Lower half operations */ +#ifdef CONFIG_SAMV7_RSWDT_INTERRUPT + xcpt_t handler; /* Current RSWDT interrupt handler */ +#endif + uint32_t timeout; /* The actual timeout value (milliseconds) */ + uint16_t reload; /* The 12-bit watchdog reload value */ + bool started; /* The timer has been started */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ +/* Register operations ******************************************************/ + +#if defined(CONFIG_SAMV7_RSWDT_REGDEBUG) && defined(CONFIG_DEBUG) +static uint32_t sam_getreg(uintptr_t regaddr); +static void sam_putreg(uint32_t regval, uintptr_t regaddr); +#else +# define sam_getreg(regaddr) getreg32(regaddr) +# define sam_putreg(regval,regaddr) putreg32(regval,regaddr) +#endif + +/* Interrupt hanlding *******************************************************/ + +#ifdef CONFIG_SAMV7_RSWDT_INTERRUPT +static int sam_interrupt(int irq, FAR void *context); +#endif + +/* "Lower half" driver methods **********************************************/ + +static int sam_start(FAR struct watchdog_lowerhalf_s *lower); +static int sam_stop(FAR struct watchdog_lowerhalf_s *lower); +static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower); +static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status); +static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout); +static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower, + xcpt_t handler); +static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* "Lower half" driver methods */ + +static const struct watchdog_ops_s g_wdgops = +{ + .start = sam_start, + .stop = sam_stop, + .keepalive = sam_keepalive, + .getstatus = sam_getstatus, + .settimeout = sam_settimeout, + .capture = sam_capture, + .ioctl = sam_ioctl, +}; + +/* "Lower half" driver state */ + +static struct sam_lowerhalf_s g_wdtdev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_getreg + * + * Description: + * Get the contents of an SAMV7 register + * + ****************************************************************************/ + +#if defined(CONFIG_SAMV7_RSWDT_REGDEBUG) && defined(CONFIG_DEBUG) +static uint32_t sam_getreg(uintptr_t regaddr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint32_t preval = 0; + + /* Read the value from the register */ + + uint32_t regval = getreg32(regaddr); + + /* Is this the same value that we read from the same registe last time? Are + * we polling the register? If so, suppress some of the output. + */ + + if (regaddr == prevaddr && regval == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + lldbg("...\n"); + } + + return regval; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + lldbg("[repeats %d more times]\n", count-3); + } + + /* Save the new address, value, and count */ + + prevaddr = regaddr; + preval = regval; + count = 1; + } + + /* Show the register value read */ + + lldbg("%08x->%048\n", regaddr, regval); + return regval; +} +#endif + +/**************************************************************************** + * Name: sam_putreg + * + * Description: + * Set the contents of an SAMV7 register to a value + * + ****************************************************************************/ + +#if defined(CONFIG_SAMV7_RSWDT_REGDEBUG) && defined(CONFIG_DEBUG) +static void sam_putreg(uint32_t regval, uintptr_t regaddr) +{ + /* Show the register value being written */ + + lldbg("%08x<-%08x\n", regaddr, regval); + + /* Write the value */ + + putreg32(regval, regaddr); +} +#endif + +/**************************************************************************** + * Name: sam_interrupt + * + * Description: + * RSWDT early warning interrupt + * + * Input Parameters: + * Usual interrupt handler arguments. + * + * Returned Values: + * Always returns OK. + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_RSWDT_INTERRUPT +static int sam_interrupt(int irq, FAR void *context) +{ + FAR struct sam_lowerhalf_s *priv = &g_wdtdev; + + /* Is there a registered handler? */ + + if (priv->handler) + { + /* Yes... NOTE: This interrupt service routine (ISR) must reload + * the RSWDT counter to prevent the reset. Otherwise, we will reset + * upon return. + */ + + priv->handler(irq, context); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: sam_start + * + * Description: + * Start the watchdog timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_start(FAR struct watchdog_lowerhalf_s *lower) +{ + FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower; + + /* The watchdog timer is enabled or disabled by writing to the MR register. + * + * NOTE: The Watchdog Mode Register (RSWDT_MR) can be written only once. Only + * a processor reset resets it. Writing the RSWDT_MR register reloads the + * timer with the newly programmed mode parameters. + */ + + wdvdbg("Entry\n"); + return priv->started ? OK : -ENOSYS; +} + +/**************************************************************************** + * Name: sam_stop + * + * Description: + * Stop the watchdog timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_stop(FAR struct watchdog_lowerhalf_s *lower) +{ + /* The watchdog timer is enabled or disabled by writing to the MR register. + * + * NOTE: The Watchdog Mode Register (RSWDT_MR) can be written only once. Only + * a processor reset resets it. Writing the RSWDT_MR register reloads the + * timer with the newly programmed mode parameters. + */ + + wdvdbg("Entry\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: sam_keepalive + * + * Description: + * Reset the watchdog timer to the current timeout value, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the atchdog timer or "petting the dog". + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower) +{ + wdvdbg("Entry\n"); + + /* Write RSWDT_CR_WDRSTT to the RSWDT CR regiser (along with the KEY value) + * will restart the watchdog timer. + */ + + sam_putreg(WDT_CR_WDRSTT | RSWDT_CR_KEY, SAM_RSWDT_CR); + return OK; +} + +/**************************************************************************** + * Name: sam_getstatus + * + * Description: + * Get the current watchdog timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * stawtus - The location to return the watchdog status information. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status) +{ + FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower; + + wdvdbg("Entry\n"); + DEBUGASSERT(priv); + + /* Return the status bit */ + + status->flags = WDFLAGS_RESET; + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + +#ifdef CONFIG_SAMV7_RSWDT_INTERRUPT + if (priv->handler) + { + status->flags |= WDFLAGS_CAPTURE; + } +#endif + + /* Return the actual timeout is milliseconds */ + + status->timeout = priv->timeout; + + /* Get the time remaining until the watchdog expires (in milliseconds) + * + * REVISIT: I think this that this information is available. + */ + + status->timeleft = 0; + + wdvdbg("Status :\n"); + wdvdbg(" flags : %08x\n", status->flags); + wdvdbg(" timeout : %d\n", status->timeout); + wdvdbg(" timeleft : %d\n", status->timeleft); + return OK; +} + +/**************************************************************************** + * Name: sam_settimeout + * + * Description: + * Set a new timeout value (and reset the watchdog timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * timeout - The new timeout value in millisecnds. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower; + uint32_t reload; + uint32_t regval; + + DEBUGASSERT(priv); + wdvdbg("Entry: timeout=%d\n", timeout); + + /* Can this timeout be represented? */ + + if (timeout < RSWDT_MINTIMEOUT || timeout >= RSWDT_MAXTIMEOUT) + { + wddbg("Cannot represent timeout: %d < %d > %d\n", + RSWDT_MINTIMEOUT, timeout, RSWDT_MAXTIMEOUT); + return -ERANGE; + } + + /* Calculate the reload value to achiee this (appoximate) timeout. + * + * Examples with RSWDT_FREQUENCY = 32768 / 128 = 256: + * timeout = 4 -> reload = 1 + * timeout = 16000 -> reload = 4096 + */ + + reload = (timeout * RSWDT_FREQUENCY + 500) / 1000; + if (reload < 1) + { + reload = 1; + } + else if (reload > 4095) + { + reload = 4095; + } + + /* Calculate and save the actual timeout value in milliseconds: + * + * timeout = 1000 * (reload + 1) / Fwwdg + */ + + priv->timeout = (1000 * reload + RSWDT_FREQUENCY/2) / RSWDT_FREQUENCY; + + /* Remember the selected values */ + + priv->reload = reload; + + wdvdbg("reload=%d timout: %d->%d\n", + reload, timeout, priv->timeout); + + /* Set the RSWDT_MR according to calculated value + * + * NOTE: The Watchdog Mode Register (RSWDT_MR) can be written only once. Only + * a processor reset resets it. Writing the RSWDT_MR register reloads the + * timer with the newly programmed mode parameters. + */ + + regval = WDT_MR_WDV(reload) | RSWDT_MR_WDD_ALLONES; + +#ifdef CONFIG_SAMV7_RSWDT_INTERRUPT + /* Generate an interrupt whent he watchdog timer expires */ + + regval |= WDT_MR_WDFIEN; +#else + /* Reset (everything) if the watchdog timer expires. + * + * REVISIT: Set WDT_MR_WDRPROC so that only the processor is reset? + */ + + regval |= WDT_MR_WDRSTEN; +#endif + +#ifdef CONFIG_SAMV7_RSWDT_DEBUGHALT + /* Halt the watchdog in the debug state */ + + regval |= WDT_MR_WDDBGHLT; +#endif + +#ifdef CONFIG_SAMV7_RSWDT_IDLEHALT + /* Halt the watchdog in the IDLE mode */ + + regval |= WDT_MR_WDIDLEHLT; +#endif + + sam_putreg(regval, SAM_RSWDT_MR); + + /* NOTE: We had to start the watchdog here (because we cannot re-write the + * MR register). So sam_start will not be able to do anything. + */ + + priv->started = true; + + wdvdbg("Setup: CR: %08x MR: %08x SR: %08x\n", + sam_getreg(SAM_RSWDT_CR), sam_getreg(SAM_RSWDT_MR), + sam_getreg(SAM_RSWDT_SR)); + + return OK; +} + +/**************************************************************************** + * Name: sam_capture + * + * Description: + * Don't reset on watchdog timer timeout; instead, call this user provider + * timeout handler. NOTE: Providing handler==NULL will restore the reset + * behavior. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * newhandler - The new watchdog expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * + * Returned Values: + * The previous watchdog expiration function pointer or NULL is there was + * no previous function pointer, i.e., if the previous behavior was + * reset-on-expiration (NULL is also returned if an error occurs). + * + ****************************************************************************/ + +static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower, + xcpt_t handler) +{ +#ifndef CONFIG_SAMV7_RSWDT_INTERRUPT + wddbg("ERROR: Not configured for this mode\n"); + return NULL; +#else + FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower; + irqstate_t flags; + xcpt_t oldhandler; + + DEBUGASSERT(priv); + wdvdbg("Entry: handler=%p\n", handler); + + /* Get the old handler return value */ + + flags = irqsave(); + oldhandler = priv->handler; + + /* Save the new handler */ + + priv->handler = handler; + + /* Are we attaching or detaching the handler? */ + + if (handler) + { + /* Attaching... Enable the RSWDT interrupt */ + + up_enable_irq(SAM_IRQ_RSWDT); + } + else + { + /* Detaching... Disable the RSWDT interrupt */ + + up_disable_irq(SAM_IRQ_RSWDT); + } + + irqrestore(flags); + return oldhandler; +#endif +} + +/**************************************************************************** + * Name: sam_ioctl + * + * Description: + * Any ioctl commands that are not recognized by the "upper-half" driver + * are forwarded to the lower half driver through this method. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * cmd - The ioctol command value + * arg - The optional argument that accompanies the 'cmd'. The + * interpretation of this argument depends on the particular + * command. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg) +{ + wdvdbg("cmd=%d arg=%ld\n", cmd, arg); + + /* No ioctls are supported */ + + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_wdginitialize + * + * Description: + * Initialize the RSWDT watchdog time. The watchdog timer is initialized and + * registered as 'devpath. The initial state of the watchdog time is + * disabled. + * + * Input Parameters: + * None + * + * Returned Values: + * None + * + ****************************************************************************/ + +int up_wdginitialize(void) +{ + FAR struct sam_lowerhalf_s *priv = &g_wdtdev; + + wdvdbg("Entry: CR: %08x MR: %08x SR: %08x\n", + sam_getreg(SAM_RSWDT_CR), sam_getreg(SAM_RSWDT_MR), + sam_getreg(SAM_RSWDT_SR)); + + /* Check if some previous logic was disabled the watchdog timer. Since the + * MR can be written only one time, we are out of business if that is the + * case. + */ + + DEBUGASSERT((sam_getreg(SAM_RSWDT_MR) & WDT_MR_WDDIS) == 0); + + /* No clock setup is required. The Watchdog Timer uses the Slow Clock + * divided by 128 to establish the maximum Watchdog period to be 16 seconds + * (with a typical Slow Clock of 32768 kHz). + */ + + /* Initialize the driver state structure. Here we assume: (1) the state + * structure lies in .bss and was zeroed at reset time. (2) This function + * is only called once so it is never necessary to re-zero the structure. + */ + + priv->ops = &g_wdgops; + +#ifdef CONFIG_SAMV7_RSWDT_INTERRUPT + /* Attach our RSWDT interrupt handler (But don't enable it yet) */ + + (void)irq_attach(SAM_IRQ_RSWDT, sam_interrupt); +#endif + + /* Register the watchdog driver as /dev/rswdt */ + + (void)watchdog_register("/dev/rswdt", + (FAR struct watchdog_lowerhalf_s *)priv); + return OK; +} + +#endif /* CONFIG_WATCHDOG && CONFIG_SAMV7_RSWDT */ diff --git a/arch/arm/src/samv7/sam_trng.c b/arch/arm/src/samv7/sam_trng.c new file mode 100644 index 0000000000..3a76b924e1 --- /dev/null +++ b/arch/arm/src/samv7/sam_trng.c @@ -0,0 +1,390 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_trng.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from the SAMA5D3 TRNG Nuttx driver which, in turn, derives, in + * part, from Max Holtzberg's STM32 RNG Nuttx driver: + * + * Copyright (C) 2012 Max Holtzberg. All rights reserved. + * Author: Max Holtzberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "sam_periphclks.h" +#include "sam_trng.h" + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Interrupts */ + +static int sam_interrupt(int irq, void *context); + +/* Character driver methods */ + +static ssize_t sam_read(struct file *filep, char *buffer, size_t); + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct trng_dev_s +{ + sem_t exclsem; /* Enforces exclusive access to the TRNG */ + sem_t waitsem; /* Wait for buffer full */ + uint32_t *samples; /* Current buffer being filled */ + size_t maxsamples; /* Size of the current buffer (in 32-bit words) */ + volatile size_t nsamples; /* Number of samples currently buffered */ + volatile bool first; /* The first random number must be handled differently */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct trng_dev_s g_trngdev; + +static const struct file_operations g_trngops = +{ + 0, /* open */ + 0, /* close */ + sam_read, /* read */ + 0, /* write */ + 0, /* seek */ + 0 /* ioctl */ +#ifndef CONFIG_DISABLE_POLL + , 0 /* poll */ +#endif +}; + +/**************************************************************************** + * Private functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_interrupt + * + * Description: + * The TRNG interrupt handler + * + * Input Parameters: + * + * Returned Value: + * + * + ****************************************************************************/ + +static int sam_interrupt(int irq, void *context) +{ + uint32_t odata; + + /* Loop where there are samples available to be read and/or until the user + * buffer is filled. Each sample requires only 84 clocks it is likely + * that we will loop here. + */ + + for (; ; ) + { + /* Read the random sample (before checking DATRDY -- but probably not + * necessary) + */ + + odata = getreg32(SAM_TRNG_ODATA); + + /* Verify that sample data is available (DATARDY is cleared when the + * interrupt status regiser is read) + */ + + if ((getreg32(SAM_TRNG_ISR) & TRNG_INT_DATRDY) == 0) + { + /* No? Then return and continue processing on the next interrupt. */ + + return OK; + } + + /* As required by the FIPS PUB (Federal Information Processing Standard + * Publication) 140-2, the first random number generated after setting + * the RNGEN bit should not be used, but saved for comparison with the + * next generated random number. Each subsequent generated random number + * has to be compared with the previously generated number. The test + * fails if any two compared numbers are equal (continuous random number + * generator test). + */ + + if (g_trngdev.nsamples == 0) + { + /* This is the first sample we have taken. Save it for subsequent + * comparison. + */ + + g_trngdev.samples[0] = odata; + g_trngdev.nsamples = 1; + continue; + } + + /* This is not the first sample. Check if the new sample differs from + * the preceding sample. + */ + + else if (odata == g_trngdev.samples[g_trngdev.nsamples - 1]) + { + /* Two samples with the same value. Discard this one and try again. */ + + continue; + } + + /* This sample differs from the previous value. Have we discarded the + * first sample yet? + */ + + if (g_trngdev.first) + { + /* No, discard it now by replacing it with the new sample */ + + g_trngdev.samples[0] = odata; + g_trngdev.nsamples = 1; + g_trngdev.first = false; + } + + /* Yes.. the first sample has been dicarded */ + + else + { + /* Add the new random number to the buffer */ + + g_trngdev.samples[g_trngdev.nsamples] = odata; + g_trngdev.nsamples++; + } + + /* Have all of the requested samples been saved? */ + + if (g_trngdev.nsamples == g_trngdev.maxsamples) + { + /* Yes.. disable any further interrupts */ + + putreg32(TRNG_INT_DATRDY, SAM_TRNG_IDR); + + /* Disable the TRNG */ + + putreg32(TRNG_CR_DISABLE | TRNG_CR_KEY, SAM_TRNG_CR); + + /* And wakeup the waiting read thread. */ + + sem_post(&g_trngdev.waitsem); + return OK; + } + } +} + +/**************************************************************************** + * Name: sam_read + * + * Description: + * This is the standard, NuttX character driver read method + * + * Input Parameters: + * filep - The VFS file instance + * buffer - Buffer in which to return the random samples + * buflen - The length of the buffer + * + * Returned Value: + * + ****************************************************************************/ + +static ssize_t sam_read(struct file *filep, char *buffer, size_t buflen) +{ + ssize_t retval; + int ret; + + fvdbg("buffer=%p buflen=%d\n", buffer, (int)buflen); + + /* Get exclusive access to the TRNG harware */ + + if (sem_wait(&g_trngdev.exclsem) != OK) + { + /* This is probably -EINTR meaning that we were awakened by a signal */ + + return -errno; + } + + /* Save the buffer information. */ + + DEBUGASSERT(((uintptr_t)buffer & 3) == 0); + + g_trngdev.samples = (uint32_t *)buffer; + g_trngdev.maxsamples = buflen >> 2; + g_trngdev.nsamples = 0; + g_trngdev.first = true; + + /* Enable the TRNG */ + + putreg32(TRNG_CR_ENABLE | TRNG_CR_KEY, SAM_TRNG_CR); + + /* Clear any pending TRNG interrupts by reading the interrupt status + * register + */ + + (void)getreg32(SAM_TRNG_ISR); + + /* Enable TRNG interrupts */ + + putreg32(TRNG_INT_DATRDY, SAM_TRNG_IER); + + /* Wait until the buffer is filled */ + + while (g_trngdev.nsamples < g_trngdev.maxsamples) + { + ret = sem_wait(&g_trngdev.waitsem); + + fvdbg("Awakened: nsamples=%d maxsamples=%d ret=%d\n", + g_trngdev.nsamples, g_trngdev.maxsamples, ret); + + if (ret < 0) + { + /* We must have been awakened by a signal */ + + if (g_trngdev.nsamples > 0) + { + break; + } + else + { + retval = -errno; + goto errout; + } + } + } + + /* Success... calculate the number of bytes to return */ + + retval = g_trngdev.nsamples << 2; + +errout: + + /* Disable TRNG interrupts */ + + putreg32(TRNG_INT_DATRDY, SAM_TRNG_IDR); + + /* Disable the TRNG */ + + putreg32(TRNG_CR_DISABLE | TRNG_CR_KEY, SAM_TRNG_CR); + + /* Release our lock on the TRNG hardware */ + + sem_post(&g_trngdev.exclsem); + + fvdbg("Return %d\n", (int)retval); + return retval; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_rnginitialize + * + * Description: + * Initialize the TRNG hardware and register the /dev/randome driver. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_rnginitialize(void) +{ + int ret; + + fvdbg("Initializing TRNG hardware\n"); + + /* Initialize the device structure */ + + memset(&g_trngdev, 0, sizeof(struct trng_dev_s)); + sem_init(&g_trngdev.exclsem, 0, 1); + sem_init(&g_trngdev.waitsem, 0, 0); + + /* Enable clocking to the TRNG */ + + sam_trng_enableclk(); + + /* Initialize the TRNG interrupt */ + + if (irq_attach(SAM_IRQ_TRNG, sam_interrupt)) + { + fdbg("ERROR: Failed to attach to IRQ%d\n", SAM_IRQ_TRNG); + return; + } + + /* Disable the interrupts at the TRNG */ + + putreg32(TRNG_INT_DATRDY, SAM_TRNG_IDR); + + /* Disable the TRNG */ + + putreg32(TRNG_CR_DISABLE | TRNG_CR_KEY, SAM_TRNG_CR); + + /* Register the character driver */ + + ret = register_driver("/dev/random", &g_trngops, 0644, NULL); + if (ret < 0) + { + fdbg("ERROR: Failed to register /dev/random\n"); + return; + } + + /* Enable the TRNG interrupt at the AIC */ + + up_enable_irq(SAM_IRQ_TRNG); +} diff --git a/arch/arm/src/samv7/sam_trng.h b/arch/arm/src/samv7/sam_trng.h new file mode 100644 index 0000000000..cd3c9f24b9 --- /dev/null +++ b/arch/arm/src/samv7/sam_trng.h @@ -0,0 +1,76 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_trng.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMV7_SAM_TRNG_H +#define __ARCH_ARM_SRC_SAMV7_SAM_TRNG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_trng.h" + +#if defined(CONFIG_DEV_RANDOM) && defined(CONFIG_SAMV7_TRNG) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_DEV_RANDOM && CONFIG_SAMV7_TRNG */ +#endif /* __ARCH_ARM_SRC_SAMV7_SAM_TRNG_H */ diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index bfbd3c4e32..f3225c8573 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -1020,11 +1020,20 @@ static void sam_dma_wrsetup(struct sam_usbdev_s *priv, struct sam_ep_s *privep, if (remaining > DMA_MAX_FIFO_SIZE) { privreq->inflight = DMA_MAX_FIFO_SIZE; + privep->zlpneeded = false; } else #endif { privreq->inflight = remaining; + + /* If the size is an exact multple of full packets, then note if + * we need to send a zero length packet next. + */ + + privep->zlpneeded = + ((privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0 && + (remaining % privep->ep.maxpacket) == 0); } /* And perform the single DMA transfer. @@ -1229,6 +1238,8 @@ static void sam_ep_fifocon(unsigned int epno) /* Clear the NAK IN bit to stop NAKing IN tokens from the host. We now * have data ready to go. + * + * REVISIT: I don't think this is necessary, */ sam_putreg(USBHS_DEVEPTINT_NAKINI, SAM_USBHS_DEVEPTICR(epno)); @@ -1270,9 +1281,19 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv, * the request. */ - if (nbytes >= privep->ep.maxpacket) + privep->zlpneeded = false; + if (nbytes > privep->ep.maxpacket) { - nbytes = privep->ep.maxpacket; + nbytes = privep->ep.maxpacket; + } + else if (nbytes == privep->ep.maxpacket) + { + /* If the size is exactly a full packet, then note if we need to + * send a zero length packet next. + */ + + privep->zlpneeded = + ((privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0); } /* This is the new number of bytes "in-flight" */ @@ -1389,26 +1410,6 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep) bytesleft = privreq->req.len - privreq->req.xfrd; if (bytesleft > 0) { - /* If the size is exactly a full packet, then note if we need to - * send a zero length packet next. - */ - - if (bytesleft == privep->ep.maxpacket && - (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) - { - /* Next time we get here, bytesleft will be zero and zlpneeded - * will be set. - */ - - privep->zlpneeded = true; - } - else - { - /* No zero packet is forthcoming (maybe later) */ - - privep->zlpneeded = false; - } - /* The way that we handle the transfer is going to depend on * whether or not this endpoint supports DMA. In either case * the endpoint state will transition to SENDING. @@ -2495,8 +2496,14 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno) */ DEBUGASSERT(USB_ISEPIN(privep->ep.eplog)); + sam_putreg(USBHS_DEVEPTINT_TXINI, SAM_USBHS_DEVEPTICR(epno)); + +#if 1 /* Wait for TXINI */ + sam_putreg(USBHS_DEVEPTINT_TXINI, SAM_USBHS_DEVEPTIER(epno)); +#else privep->epstate = USBHS_EPSTATE_IDLE; (void)sam_req_write(priv, privep); +#endif } else if (privep->epstate == USBHS_EPSTATE_RECEIVING) { @@ -2554,7 +2561,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno) USB_ISEPOUT(privep->ep.eplog)); /* Get the number of bytes transferred from the DMA status. - * + * * BUFF_COUNT holds the number of untransmitted bytes. In this case, * BUFF_COUNT should not be zero. BUFF_COUNT was set to the * 'inflight' count when the DMA started so the difference will @@ -2645,9 +2652,9 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno) { /* Continue/resume processing the write requests. */ + sam_putreg(USBHS_DEVEPTINT_TXINI, SAM_USBHS_DEVEPTICR(epno)); privep->epstate = USBHS_EPSTATE_IDLE; (void)sam_req_write(priv, privep); - sam_putreg(USBHS_DEVEPTINT_TXINI, SAM_USBHS_DEVEPTICR(epno)); } /* Setting of the device address is a special case. The address was diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c new file mode 100644 index 0000000000..5f377aba4d --- /dev/null +++ b/arch/arm/src/samv7/sam_wdt.c @@ -0,0 +1,705 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_wdg.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "sam_wdt.h" + +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_SAMV7_WDT) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* The Watchdog Timer uses the Slow Clock divided by 128 to establish the + * maximum Watchdog period to be 16 seconds (with a typical Slow Clock of + * 32768 kHz). + */ + +#ifndef BOARD_SCLK_FREQUENCY +# define BOARD_SCLK_FREQUENCY 32768 +#endif + +#define WDT_FREQUENCY (BOARD_SCLK_FREQUENCY / 128) + +/* At 32768Hz, the maximum timeout value will be: + * + * 4096 / WDT_FREQUENCY = 256 seconds or 16,000 milliseconds + * + * And the minimum (non-zero) timeout would be: + * + * 1 / WDT_FREQUENCY = 3.9 milliseconds + */ + +#define WDT_MINTIMEOUT ((1000 + WDT_FREQUENCY - 1) / WDT_FREQUENCY) +#define WDT_MAXTIMEOUT ((4096 * 1000) / WDT_FREQUENCY) + +/* Debug ********************************************************************/ +/* Non-standard debug that may be enabled just for testing the watchdog + * driver. NOTE: that only lldbg types are used so that the output is + * immediately available. + */ + +#ifdef CONFIG_DEBUG_WATCHDOG +# define wddbg lldbg +# define wdvdbg llvdbg +#else +# define wddbg(x...) +# define wdvdbg(x...) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * well-known watchdog_lowerhalf_s structure. + */ + +struct sam_lowerhalf_s +{ + FAR const struct watchdog_ops_s *ops; /* Lower half operations */ +#ifdef CONFIG_SAMV7_WDT_INTERRUPT + xcpt_t handler; /* Current WDT interrupt handler */ +#endif + uint32_t timeout; /* The actual timeout value (milliseconds) */ + uint16_t reload; /* The 12-bit watchdog reload value */ + bool started; /* The timer has been started */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ +/* Register operations ******************************************************/ + +#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG) +static uint32_t sam_getreg(uintptr_t regaddr); +static void sam_putreg(uint32_t regval, uintptr_t regaddr); +#else +# define sam_getreg(regaddr) getreg32(regaddr) +# define sam_putreg(regval,regaddr) putreg32(regval,regaddr) +#endif + +/* Interrupt hanlding *******************************************************/ + +#ifdef CONFIG_SAMV7_WDT_INTERRUPT +static int sam_interrupt(int irq, FAR void *context); +#endif + +/* "Lower half" driver methods **********************************************/ + +static int sam_start(FAR struct watchdog_lowerhalf_s *lower); +static int sam_stop(FAR struct watchdog_lowerhalf_s *lower); +static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower); +static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status); +static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout); +static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower, + xcpt_t handler); +static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* "Lower half" driver methods */ + +static const struct watchdog_ops_s g_wdgops = +{ + .start = sam_start, + .stop = sam_stop, + .keepalive = sam_keepalive, + .getstatus = sam_getstatus, + .settimeout = sam_settimeout, + .capture = sam_capture, + .ioctl = sam_ioctl, +}; + +/* "Lower half" driver state */ + +static struct sam_lowerhalf_s g_wdtdev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_getreg + * + * Description: + * Get the contents of an SAMV7 register + * + ****************************************************************************/ + +#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG) +static uint32_t sam_getreg(uintptr_t regaddr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint32_t preval = 0; + + /* Read the value from the register */ + + uint32_t regval = getreg32(regaddr); + + /* Is this the same value that we read from the same registe last time? Are + * we polling the register? If so, suppress some of the output. + */ + + if (regaddr == prevaddr && regval == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + lldbg("...\n"); + } + + return regval; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + lldbg("[repeats %d more times]\n", count-3); + } + + /* Save the new address, value, and count */ + + prevaddr = regaddr; + preval = regval; + count = 1; + } + + /* Show the register value read */ + + lldbg("%08x->%048\n", regaddr, regval); + return regval; +} +#endif + +/**************************************************************************** + * Name: sam_putreg + * + * Description: + * Set the contents of an SAMV7 register to a value + * + ****************************************************************************/ + +#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG) +static void sam_putreg(uint32_t regval, uintptr_t regaddr) +{ + /* Show the register value being written */ + + lldbg("%08x<-%08x\n", regaddr, regval); + + /* Write the value */ + + putreg32(regval, regaddr); +} +#endif + +/**************************************************************************** + * Name: sam_interrupt + * + * Description: + * WDT early warning interrupt + * + * Input Parameters: + * Usual interrupt handler arguments. + * + * Returned Values: + * Always returns OK. + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_WDT_INTERRUPT +static int sam_interrupt(int irq, FAR void *context) +{ + FAR struct sam_lowerhalf_s *priv = &g_wdtdev; + + /* Is there a registered handler? */ + + if (priv->handler) + { + /* Yes... NOTE: This interrupt service routine (ISR) must reload + * the WDT counter to prevent the reset. Otherwise, we will reset + * upon return. + */ + + priv->handler(irq, context); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: sam_start + * + * Description: + * Start the watchdog timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_start(FAR struct watchdog_lowerhalf_s *lower) +{ + FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower; + + /* The watchdog timer is enabled or disabled by writing to the MR register. + * + * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. Only + * a processor reset resets it. Writing the WDT_MR register reloads the + * timer with the newly programmed mode parameters. + */ + + wdvdbg("Entry\n"); + return priv->started ? OK : -ENOSYS; +} + +/**************************************************************************** + * Name: sam_stop + * + * Description: + * Stop the watchdog timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_stop(FAR struct watchdog_lowerhalf_s *lower) +{ + /* The watchdog timer is enabled or disabled by writing to the MR register. + * + * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. Only + * a processor reset resets it. Writing the WDT_MR register reloads the + * timer with the newly programmed mode parameters. + */ + + wdvdbg("Entry\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: sam_keepalive + * + * Description: + * Reset the watchdog timer to the current timeout value, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the atchdog timer or "petting the dog". + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower) +{ + wdvdbg("Entry\n"); + + /* Write WDT_CR_WDRSTT to the WDT CR regiser (along with the KEY value) + * will restart the watchdog timer. + */ + + sam_putreg(WDT_CR_WDRSTT | WDT_CR_KEY, SAM_WDT_CR); + return OK; +} + +/**************************************************************************** + * Name: sam_getstatus + * + * Description: + * Get the current watchdog timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * stawtus - The location to return the watchdog status information. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status) +{ + FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower; + + wdvdbg("Entry\n"); + DEBUGASSERT(priv); + + /* Return the status bit */ + + status->flags = WDFLAGS_RESET; + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + +#ifdef CONFIG_SAMV7_WDT_INTERRUPT + if (priv->handler) + { + status->flags |= WDFLAGS_CAPTURE; + } +#endif + + /* Return the actual timeout is milliseconds */ + + status->timeout = priv->timeout; + + /* Get the time remaining until the watchdog expires (in milliseconds) + * + * REVISIT: I think this that this information is available. + */ + + status->timeleft = 0; + + wdvdbg("Status :\n"); + wdvdbg(" flags : %08x\n", status->flags); + wdvdbg(" timeout : %d\n", status->timeout); + wdvdbg(" timeleft : %d\n", status->timeleft); + return OK; +} + +/**************************************************************************** + * Name: sam_settimeout + * + * Description: + * Set a new timeout value (and reset the watchdog timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * timeout - The new timeout value in millisecnds. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower; + uint32_t reload; + uint32_t regval; + + DEBUGASSERT(priv); + wdvdbg("Entry: timeout=%d\n", timeout); + + /* Can this timeout be represented? */ + + if (timeout < WDT_MINTIMEOUT || timeout >= WDT_MAXTIMEOUT) + { + wddbg("Cannot represent timeout: %d < %d > %d\n", + WDT_MINTIMEOUT, timeout, WDT_MAXTIMEOUT); + return -ERANGE; + } + + /* Calculate the reload value to achiee this (appoximate) timeout. + * + * Examples with WDT_FREQUENCY = 32768 / 128 = 256: + * timeout = 4 -> reload = 1 + * timeout = 16000 -> reload = 4096 + */ + + reload = (timeout * WDT_FREQUENCY + 500) / 1000; + if (reload < 1) + { + reload = 1; + } + else if (reload > 4095) + { + reload = 4095; + } + + /* Calculate and save the actual timeout value in milliseconds: + * + * timeout = 1000 * (reload + 1) / Fwwdg + */ + + priv->timeout = (1000 * reload + WDT_FREQUENCY/2) / WDT_FREQUENCY; + + /* Remember the selected values */ + + priv->reload = reload; + + wdvdbg("reload=%d timout: %d->%d\n", + reload, timeout, priv->timeout); + + /* Set the WDT_MR according to calculated value + * + * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. Only + * a processor reset resets it. Writing the WDT_MR register reloads the + * timer with the newly programmed mode parameters. + */ + + regval = WDT_MR_WDV(reload) | WDT_MR_WDD(reload); + +#ifdef CONFIG_SAMV7_WDT_INTERRUPT + /* Generate an interrupt whent he watchdog timer expires */ + + regval |= WDT_MR_WDFIEN; +#else + /* Reset (everything) if the watchdog timer expires. + * + * REVISIT: Set WDT_MR_WDRPROC so that only the processor is reset? + */ + + regval |= WDT_MR_WDRSTEN; +#endif + +#ifdef CONFIG_SAMV7_WDT_DEBUGHALT + /* Halt the watchdog in the debug state */ + + regval |= WDT_MR_WDDBGHLT; +#endif + +#ifdef CONFIG_SAMV7_WDT_IDLEHALT + /* Halt the watchdog in the IDLE mode */ + + regval |= WDT_MR_WDIDLEHLT; +#endif + + sam_putreg(regval, SAM_WDT_MR); + + /* NOTE: We had to start the watchdog here (because we cannot re-write the + * MR register). So sam_start will not be able to do anything. + */ + + priv->started = true; + + wdvdbg("Setup: CR: %08x MR: %08x SR: %08x\n", + sam_getreg(SAM_WDT_CR), sam_getreg(SAM_WDT_MR), + sam_getreg(SAM_WDT_SR)); + + return OK; +} + +/**************************************************************************** + * Name: sam_capture + * + * Description: + * Don't reset on watchdog timer timeout; instead, call this user provider + * timeout handler. NOTE: Providing handler==NULL will restore the reset + * behavior. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * newhandler - The new watchdog expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * + * Returned Values: + * The previous watchdog expiration function pointer or NULL is there was + * no previous function pointer, i.e., if the previous behavior was + * reset-on-expiration (NULL is also returned if an error occurs). + * + ****************************************************************************/ + +static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower, + xcpt_t handler) +{ +#ifndef CONFIG_SAMV7_WDT_INTERRUPT + wddbg("ERROR: Not configured for this mode\n"); + return NULL; +#else + FAR struct sam_lowerhalf_s *priv = (FAR struct sam_lowerhalf_s *)lower; + irqstate_t flags; + xcpt_t oldhandler; + + DEBUGASSERT(priv); + wdvdbg("Entry: handler=%p\n", handler); + + /* Get the old handler return value */ + + flags = irqsave(); + oldhandler = priv->handler; + + /* Save the new handler */ + + priv->handler = handler; + + /* Are we attaching or detaching the handler? */ + + if (handler) + { + /* Attaching... Enable the WDT interrupt */ + + up_enable_irq(SAM_IRQ_WDT); + } + else + { + /* Detaching... Disable the WDT interrupt */ + + up_disable_irq(SAM_IRQ_WDT); + } + + irqrestore(flags); + return oldhandler; +#endif +} + +/**************************************************************************** + * Name: sam_ioctl + * + * Description: + * Any ioctl commands that are not recognized by the "upper-half" driver + * are forwarded to the lower half driver through this method. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * cmd - The ioctol command value + * arg - The optional argument that accompanies the 'cmd'. The + * interpretation of this argument depends on the particular + * command. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg) +{ + wdvdbg("cmd=%d arg=%ld\n", cmd, arg); + + /* No ioctls are supported */ + + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_wdginitialize + * + * Description: + * Initialize the WDT watchdog time. The watchdog timer is initialized and + * registered as 'devpath. The initial state of the watchdog time is + * disabled. + * + * Input Parameters: + * None + * + * Returned Values: + * None + * + ****************************************************************************/ + +int up_wdginitialize(void) +{ + FAR struct sam_lowerhalf_s *priv = &g_wdtdev; + + wdvdbg("Entry: CR: %08x MR: %08x SR: %08x\n", + sam_getreg(SAM_WDT_CR), sam_getreg(SAM_WDT_MR), + sam_getreg(SAM_WDT_SR)); + + /* Check if some previous logic was disabled the watchdog timer. Since the + * MR can be written only one time, we are out of business if that is the + * case. + */ + + DEBUGASSERT((sam_getreg(SAM_WDT_MR) & WDT_MR_WDDIS) == 0); + + /* No clock setup is required. The Watchdog Timer uses the Slow Clock + * divided by 128 to establish the maximum Watchdog period to be 16 seconds + * (with a typical Slow Clock of 32768 kHz). + */ + + /* Initialize the driver state structure. Here we assume: (1) the state + * structure lies in .bss and was zeroed at reset time. (2) This function + * is only called once so it is never necessary to re-zero the structure. + */ + + priv->ops = &g_wdgops; + +#ifdef CONFIG_SAMV7_WDT_INTERRUPT + /* Attach our WDT interrupt handler (But don't enable it yet) */ + + (void)irq_attach(SAM_IRQ_WDT, sam_interrupt); +#endif + + /* Register the watchdog driver as /dev/wdt */ + + (void)watchdog_register("/dev/wdt", + (FAR struct watchdog_lowerhalf_s *)priv); + return OK; +} + +#endif /* CONFIG_WATCHDOG && CONFIG_SAMV7_WDT */ diff --git a/arch/arm/src/samv7/sam_wdt.h b/arch/arm/src/samv7/sam_wdt.h new file mode 100644 index 0000000000..d5d7c50728 --- /dev/null +++ b/arch/arm/src/samv7/sam_wdt.h @@ -0,0 +1,76 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_wdt.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMV7_SAM_WDT_H +#define __ARCH_ARM_SRC_SAMV7_SAM_WDT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_wdt.h" + +#ifdef CONFIG_WATCHDOG + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_WATCHDOG */ +#endif /* __ARCH_ARM_SRC_SAMV7_SAM_WDT_H */ diff --git a/arch/avr/src/common/up_initialize.c b/arch/avr/src/common/up_initialize.c index f6273cb4e9..298c71c1a1 100644 --- a/arch/avr/src/common/up_initialize.c +++ b/arch/avr/src/common/up_initialize.c @@ -46,6 +46,7 @@ #include #include #include +#include #include #include @@ -286,6 +287,12 @@ void up_initialize(void) (void)tun_initialize(); #endif +#ifdef CONFIG_NETDEV_TELNET + /* Initialize the Telnet session factory */ + + (void)telnet_initialize(); +#endif + /* Initialize USB */ up_usbinitialize(); diff --git a/arch/hc/src/common/up_initialize.c b/arch/hc/src/common/up_initialize.c index 6b2495f728..f549747f8a 100644 --- a/arch/hc/src/common/up_initialize.c +++ b/arch/hc/src/common/up_initialize.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include @@ -210,6 +211,12 @@ void up_initialize(void) (void)tun_initialize(); #endif +#ifdef CONFIG_NETDEV_TELNET + /* Initialize the Telnet session factory */ + + (void)telnet_initialize(); +#endif + /* Initialize USB */ up_usbinitialize(); diff --git a/arch/mips/src/common/up_initialize.c b/arch/mips/src/common/up_initialize.c index 3588057b1d..5a60cee560 100644 --- a/arch/mips/src/common/up_initialize.c +++ b/arch/mips/src/common/up_initialize.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include @@ -212,6 +213,12 @@ void up_initialize(void) (void)tun_initialize(); #endif +#ifdef CONFIG_NETDEV_TELNET + /* Initialize the Telnet session factory */ + + (void)telnet_initialize(); +#endif + /* Initialize USB -- device and/or host */ up_usbinitialize(); diff --git a/arch/sh/src/common/up_initialize.c b/arch/sh/src/common/up_initialize.c index 3b19140ac0..1239cd5805 100644 --- a/arch/sh/src/common/up_initialize.c +++ b/arch/sh/src/common/up_initialize.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include @@ -200,6 +201,12 @@ void up_initialize(void) (void)tun_initialize(); #endif +#ifdef CONFIG_NETDEV_TELNET + /* Initialize the Telnet session factory */ + + (void)telnet_initialize(); +#endif + /* Initialize USB */ up_usbinitialize(); diff --git a/arch/sim/src/up_initialize.c b/arch/sim/src/up_initialize.c index 4bf85707a0..1143e347e7 100644 --- a/arch/sim/src/up_initialize.c +++ b/arch/sim/src/up_initialize.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include #include @@ -196,6 +197,12 @@ void up_initialize(void) (void)tun_initialize(); #endif +#ifdef CONFIG_NETDEV_TELNET + /* Initialize the Telnet session factory */ + + (void)telnet_initialize(); +#endif + #if defined(CONFIG_FS_SMARTFS) && defined(CONFIG_SIM_SPIFLASH) up_init_smartfs(); #endif diff --git a/arch/x86/src/common/up_initialize.c b/arch/x86/src/common/up_initialize.c index d395c2d654..43bc71a2c1 100644 --- a/arch/x86/src/common/up_initialize.c +++ b/arch/x86/src/common/up_initialize.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include @@ -212,6 +213,12 @@ void up_initialize(void) (void)tun_initialize(); #endif +#ifdef CONFIG_NETDEV_TELNET + /* Initialize the Telnet session factory */ + + (void)telnet_initialize(); +#endif + /* Initialize USB -- device and/or host */ up_usbinitialize(); diff --git a/arch/z16/src/common/up_initialize.c b/arch/z16/src/common/up_initialize.c index 2932c50f17..ce72e27421 100644 --- a/arch/z16/src/common/up_initialize.c +++ b/arch/z16/src/common/up_initialize.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include @@ -216,5 +217,11 @@ void up_initialize(void) (void)tun_initialize(); #endif +#ifdef CONFIG_NETDEV_TELNET + /* Initialize the Telnet session factory */ + + (void)telnet_initialize(); +#endif + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/z80/src/common/up_initialize.c b/arch/z80/src/common/up_initialize.c index 67aad82a37..64343c8984 100644 --- a/arch/z80/src/common/up_initialize.c +++ b/arch/z80/src/common/up_initialize.c @@ -47,6 +47,7 @@ #include #include #include +#include #include @@ -199,5 +200,11 @@ void up_initialize(void) (void)tun_initialize(); #endif +#ifdef CONFIG_NETDEV_TELNET + /* Initialize the Telnet session factory */ + + (void)telnet_initialize(); +#endif + board_autoled_on(LED_IRQSENABLED); }