Update CP15 access macros
This commit is contained in:
Gregory Nutt
parent
7475712d87
commit
39cace15a1
@ -7,10 +7,8 @@
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*
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* References:
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*
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* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1, Copyright © 2010
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* ARM. All rights reserved. ARM DDI 0434B (ID101810)
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* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright ©
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* 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.b (ID072512)
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* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright
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* 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.c (ID051414)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -74,9 +72,9 @@
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#define _CP15(op1,rd,crn,crm,op2) p15, op1, rd, crn, crm, op2
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#define CP15_MIDR(r) _CP15(0, r, c0, c0, 0) /* Main ID Register */
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#define CP15_TR(r) _CP15(0, r, c0, c0, 1) /* Cache Type Register */
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#define CP15_CTR(r) _CP15(0, r, c0, c0, 1) /* Cache Type Register */
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#define CP15_TCMTR(r) _CP15(0, r, c0, c0, 2) /* TCM Type Register */
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#define CP15_TLBTR(r) _CP15(0, r, c0, c0, 3) /* TLB Type Register */
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#define CP15_MPUIDR(r) _CP15(0, r, c0, c0, 4) /* MPU Type Register */
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#define CP15_MPIDR(r) _CP15(0, r, c0, c0, 5) /* Multiprocessor Affinity Register */
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#define CP15_REVIDR(r) _CP15(0, r, c0, c0, 6) /* Revision ID register (Cortex-A9) */
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#define CP15_MID_PFR0(r) _CP15(0, r, c0, c1, 0) /* Processor Feature Register 0 */
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@ -101,16 +99,6 @@
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#define CP15_SCTLR(r) _CP15(0, r, c1, c0, 0) /* System Control Register */
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#define CP15_ACTLR(r) _CP15(0, r, c1, c0, 1) /* Auxiliary Control Register */
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#define CP15_CPACR(r) _CP15(0, r, c1, c0, 2) /* Coprocessor Access Control Register */
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#define CP15_SCR(r) _CP15(0, r, c1, c1, 0) /* Secure Configuration Register */
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#define CP15_SDER(r) _CP15(0, r, c1, c1, 1) /* Secure Debug Enable Register */
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#define CP15_NSACR(r) _CP15(0, r, c1, c1, 2) /* Non-secure Access Control Register */
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#define CP15_VCR(r) _CP15(0, r, c1, c1, 3) /* Virtualization Control Register */
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#define CP15_TTBR0(r) _CP15(0, r, c2, c0, 0) /* Translation Table Base Register 0 */
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#define CP15_TTBR1(r) _CP15(0, r, c2, c0, 1) /* Translation Table Base Register 1 */
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#define CP15_TTBCR(r) _CP15(0, r, c2, c0, 2) /* Translation Table Base Control Register */
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#define CP15_DACR(r) _CP15(0, r, c3, c0, 0) /* Domain Access Control Register */
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#define CP15_DFSR(r) _CP15(0, r, c5, c0, 0) /* Data Fault Status Register */
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#define CP15_IFSR(r) _CP15(0, r, c5, c0, 1) /* Instruction Fault Status Register */
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@ -120,96 +108,53 @@
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#define CP15_DFAR(r) _CP15(0, r, c6, c0, 0) /* Data Fault Address Register */
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#define CP15_IFAR(r) _CP15(0, r, c6, c0, 2) /* Instruction Fault Address Register */
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#define CP15_NOP(r) _CP15(0, r, c7, c0, 4)
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#define CP15_ICIALLUIS(r) _CP15(0, r, c7, c1, 0) /* Cache Operations Registers */
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#define CP15_BPIALLIS(r) _CP15(0, r, c7, c1, 6)
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#define CP15_PAR(r) _CP15(0, r, c7, c4, 0) /* Physical Address Register */
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#define CP15_ICIALLU(r) _CP15(0, r, c7, c5, 0) /* Cache Operations Registers */
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#define CP15_ICIMVAU(r) _CP15(0, r, c7, c5, 1)
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#define CP15_ISB(r) _CP15(0, r, c7, c5, 4)
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#define CP15_CP15ISB(r) _CP15(0, r, c7, c5, 4) /* CP15 Instruction Synchronization Barrier operation */
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#define CP15_BPIALL(r) _CP15(0, r, c7, c5, 6) /* Cache Operations Registers */
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#define CP15_BPIMVA(r) _CP15(0, r, c7, c5, 7) /* Cortex-A5 */
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#define CP15_DCIMVAC(r) _CP15(0, r, c7, c6, 1)
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#define CP15_DCISW(r) _CP15(0, r, c7, c6, 2)
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#define CP15_V2PCWPR(r,n) _CP15(0, r, c7, c8, (n)) /* VA to PA operations, n=0-3 */
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# define CP15_V2PCWPR0(r) _CP15(0, r, c7, c8, 0)
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# define CP15_V2PCWPR1(r) _CP15(0, r, c7, c8, 1)
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# define CP15_V2PCWPR2(r) _CP15(0, r, c7, c8, 2)
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# define CP15_V2PCWPR3(r) _CP15(0, r, c7, c8, 3)
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#define CP15_V2POWPR(r,n) _CP15(0, r, c7, c8, ((n)+4)) /* n=0-3 */
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# define CP15_V2POWPR0(r) _CP15(0, r, c7, c8, 4)
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# define CP15_V2POWPR1(r) _CP15(0, r, c7, c8, 5)
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# define CP15_V2POWPR2(r) _CP15(0, r, c7, c8, 6)
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# define CP15_V2POWPR3(r) _CP15(0, r, c7, c8, 7)
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#define CP15_DCCMVAC(r) _CP15(0, r, c7, c10, 1) /* Cache Operations Registers (aka DCCVAC) */
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#define CP15_DCCSW(r) _CP15(0, r, c7, c10, 2)
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#define CP15_DSB(r) _CP15(0, r, c7, c10, 4)
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#define CP15_DMB(r) _CP15(0, r, c7, c10, 5)
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#define CP15_DCCMVAC(r) _CP15(0, r, c7, c10, 1) /* Data Cache Clean by MVA to PoC */
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#define CP15_DCCSW(r) _CP15(0, r, c7, c10, 2) /* Data Cache Clean by Set/Way */
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#define CP15_CP15DSB(r) _CP15(0, r, c7, c10, 4) /* CP15 Data Synchronization Barrier operation */
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#define CP15_CP15DMB(r) _CP15(0, r, c7, c10, 5) /* CP15 Instruction Synchronization Barrier operation */
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#define CP15_DCCMVAU(r) _CP15(0, r, c7, c11, 1) /* Cache Operations Registers */
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#define CP15_DCCIMVAC(r) _CP15(0, r, c7, c14, 1)
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#define CP15_DCCISW(r) _CP15(0, r, c7, c14, 2)
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#define CP15_TLBIALLIS(r) _CP15(0, r, c8, c3, 0) /* Invalidate entire unified TLB Inner Shareable */
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#define CP15_TLBIMVAIS(r) _CP15(0, r, c8, c3, 1) /* Invalidate unified TLB entry by MVA and ASID, Inner Shareable */
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#define CP15_TLBIASIDIS(r) _CP15(0, r, c8, c3, 2) /* Invalidate unified TLB by ASID match Inner Shareable */
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#define CP15_TLBIMVAAIS(r) _CP15(0, r, c8, c3, 3) /* Invalidate unified TLB entry by MVA all ASID Inner Shareable */
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#define CP15_TLBIALL(r,c) _CP15(0, r, c8, c, 0) /* Invalidate entire instruction TLB. CRm = c5, c6, or c7 */
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#define CP15_TLBIMVA(r,c) _CP15(0, r, c8, c, 1) /* Invalidate instruction TLB entry by MVA and ASID. CRm = c5, c6, or c7 */
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#define CP15_TLBIASID(r,c) _CP15(0, r, c8, c, 2) /* Invalidate data TLB by ASID match. CRm = c5, c6, or c7 */
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#define CP15_TLBIMVAA(r,c) _CP15(0, r, c8, c, 3) /* Invalidate unified TLB entry by MVA and ASID. CRm = c5, c6, or c7 */
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#define CP15_MCR(r) _CP15(0, r, c9, c12, 0) /* Performance Monitor Control Register */
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#define CP15_PMCR(r) _CP15(0, r, c9, c12, 0) /* Performance Monitor Control Register */
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#define CP15_PMCNTENSET(r) _CP15(0, r, c9, c12, 1) /* Count Enable Set Register */
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#define CP15_PMCNTENCLR(r) _CP15(0, r, c9, c12, 2) /* Count Enable Clear Register */
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#define CP15_MOVSR(r) _CP15(0, r, c9, c12, 3) /* Overflow Flag Status Register */
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#define CP15_PMOVSR(r) _CP15(0, r, c9, c12, 3) /* Overflow Flag Status Register */
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#define CP15_PMSWINC(r) _CP15(0, r, c9, c12, 4) /* Software Increment Register */
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#define CP15_PMSELR(r) _CP15(0, r, c9, c12, 5) /* Event Counter Selection Register */
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#define CP15_PMCEID0(r) _CP15(0, r, c9, c12, 6) /* Common Event Identification Registers (Cortex-A5) */
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#define CP15_PMCEID1(r) _CP15(0, r, c9, c12, 7)
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#define CP15_PMCCNTR(r) _CP15(0, r, c9, c13, 0) /* Cycle Count Register */
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#define CP15_PMXEVTYPER(r) _CP15(0, r, c9, c13, 1) /* Event Type Select Register */
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#define CP15_PMCCFILTR(r) _CP15(0, r, c9, c13, 1) /* Cycle Count Filter Control Register */
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#define CP15_MXEVCNTR(r) _CP15(0, r, c9, c13, 2) /* Event Count Registers (Cortex-A5) */
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#define CP15_PMXEVCNTR(r) _CP15(0, r, c9, c13, 2) /* Event Count Registers (Cortex-A5) */
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#define CP15_PMUSERENR(r) _CP15(0, r, c9, c14, 0) /* User Enable Register */
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#define CP15_PMINTENSET(r) _CP15(0, r, c9, c14, 1) /* Interrupt Enable Set Register */
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#define CP15_PMINTENCLR(r) _CP15(0, r, c9, c14, 2) /* Interrupt Enable Clear Register */
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#define CP15_TLBLCKDOWN(r) _CP15(0, r, c10, c0, 0) /* TLB Lockdown register (Cortex-A9) */
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#define CP15_PPRRR(r) _CP15(0, r, c10, c2, 0) /* Primary Region Remap Register */
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#define CP15_NMRR(r) _CP15(0, r, c10, c2, 1) /* Normal Memory Remap Register */
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#define CP15_PLEIDR(r) _CP15(0, r, c11, c0, 0) /* PLE ID Register (Cortex-A9) */
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#define CP15_PLEASR(r) _CP15(0, r, c11, c0, 2) /* PLE Activity Status Register (Cortex-A9) */
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#define CP15_PLEFSR(r) _CP15(0, r, c11, c0, 4) /* PLE FIFO Status Register (Cortex-A9) */
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#define CP15_PLEUAR(r) _CP15(0, r, c11, c1, 0) /* Preload Engine User Accessibility Register (Cortex-A9) */
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#define CP15_PLEPCR(r) _CP15(0, r, c11, c1, 1) /* Preload Engine Parameters Control Register (Cortex-A9) */
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#define CP15_VBAR(r) _CP15(0, r, c12, c0, 0) /* Vector Base Address Register */
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#define CP15_MVBAR(r) _CP15(0, r, c12, c0, 1) /* Monitor Vector Base Address Register */
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#define CP15_ISR(r) _CP15(0, r, c12, c1, 0) /* Interrupt Status Register */
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#define CP15_VIR(r) _CP15(0, r, c12, c1, 1) /* Virtualization Interrupt Register */
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#define CP15_FCSEIDR(r) _CP15(0, r, c13, c0, 0) /* Fast Context Switch Extension (FCSE) not implemented */
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#define CP15_CONTEXTIDR(r) _CP15(0, r, c13, c0, 1) /* Context ID Register */
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#define CP15_TPIDRURW(r) _CP15(0, r, c13, c0, 2) /* Software Thread ID Registers */
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#define CP15_TPIDRURO(r) _CP15(0, r, c13, c0, 3)
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#define CP15_TPIDRPRW(r) _CP15(0, r, c13, c0, 4)
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#define CP15_PWRCTRL(r) _CP15(0, r, c15, c0, 0) /* Power Control Register (Cortex-A9) */
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#define CP15_NEONBUSY(r) _CP15(0, r, c15, c1, 1) /* NEON Busy Register (Cortex-A9) */
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#define CP15_DR0(r) _CP15(3, r, c15, c0, 0) /* Data Register (Cortex-A5) */
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#define CP15_DR1(r) _CP15(3, r, c15, c0, 1) /* Data Register (Cortex-A5) */
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#define CP15_DTAGR(r) _CP15(3, r, c15, c2, 0) /* Data Cache Tag Read Operation Register (Cortex-A5) */
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#define CP15_ITAGR(r) _CP15(3, r, c15, c2, 1) /* Instruction Cache Tag Read Operation Register (Cortex-A5) */
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#define CP15_DDATAR(r) _CP15(3, r, c15, c4, 0) /* Data Cache Data Read Operation Register (Cortex-A5) */
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#define CP15_IDATAR(r) _CP15(3, r, c15, c4, 1) /* Instruction Cache Data Read Operation Register (Cortex-A5) */
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#define CP15_TLBR(r) _CP15(3, r, c15, c4, 2) /* TLB Data Read Operation Register (Cortex-A5) */
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#define CP15_CBADDR(r) _CP15(4, r, c15, c0, 0) /* Configuration Base Address Register */
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#define CP15_TLBHITMAP(r) _CP15(5, r, c15, c0, 0) /* TLB access and attributes (Cortex-A5) */
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#define CP15_RTLBLCKDWN(r) _CP15(5, r, c15, c4, 2) /* Select Lockdown TLB Entry for read (Cortex-A9) */
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#define CP15_WTLBLCKDWN(r) _CP15(5, r, c15, c4, 4) /* Select Lockdown TLB Entry for write (Cortex-A9) */
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#define CP15_MAINTLBVA(r) _CP15(5, r, c15, c5, 2) /* Main TLB VA register (Cortex-A9) */
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#define CP15_MAINTLBPA(r) _CP15(5, r, c15, c6, 2) /* Main TLB PA register (Cortex-A9) */
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#define CP15_MAINTLBAT(r) _CP15(5, r, c15, c7, 2) /* Main TLB Attribute register (Cortex-A9) */
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#define CP15_CNTFRQ(r) _CP15(0, r, c14, c0, 0) /* Counter Frequency register */
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#define CP15_CNTKCTL(r) _CP15(0, r, c14, c1, 0) /* Timer PL1 Control register */
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#define CP15_CNTP_TVAL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical TimerValue register */
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#define CP15_CNTP_CTL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical Timer Control register */
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#define CP15_CNTV_TVAL(r) _CP15(0, r, c14, c3, 0) /* Virtual TimerValue register */
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#define CP15_CNTV_CTL(r) _CP15(0, r, c14, c3, 0) /* Virtual Timer Control register */
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#define CP15_CNTPCT(r,n) _CP15(0, r, c14, c14, n) /* 64-bit Physical Count register */
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#define CP15_CNTVCT(r,n) _CP15(1, r, c14, c14, n) /* Virtual Count register */
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#define CP15_CNTP_CVAL(r,n) _CP15(2, r, c14, c14, n) /* PL1 Physical Timer CompareValue register */
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#define CP15_CNTV_CVAL(r,n) _CP15(3, r, c14, c14, n) /* Virtual Timer CompareValue register */
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#endif /* __ARCH_ARM_SRC_ARMV7_R_CP15_H */
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@ -92,7 +92,7 @@
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cp15_clean_dcache:
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mrc CP15_TR(r3) /* Read the Cache Type Register */
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mrc CP15_CTR(r3) /* Read the Cache Type Register */
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lsr r3, r3, #16 /* Isolate the DMinLine field */
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and r3, r3, #0xf
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mov r2, #4
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@ -93,7 +93,7 @@
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.type cp15_coherent_dcache, function
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cp15_coherent_dcache:
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mrc CP15_TR(r3) /* Read the Cache Type Register */
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mrc CP15_CTR(r3) /* Read the Cache Type Register */
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lsr r3, r3, #16 /* Isolate the DMinLine field */
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and r3, r3, #0xf
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mov r2, #4
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@ -111,7 +111,7 @@ cp15_coherent_dcache:
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dsb
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mrc CP15_TR(r3) /* Read the Cache Type Register */
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mrc CP15_CTR(r3) /* Read the Cache Type Register */
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and r3, r3, #0xf /* Isolate the IminLine field */
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mov r2, #4
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mov r2, r2, lsl r3 /* Get the cache line size in bytes */
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@ -92,7 +92,7 @@
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cp15_flush_dcache:
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mrc CP15_TR(r3) /* Read the Cache Type Register */
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mrc CP15_CTR(r3) /* Read the Cache Type Register */
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lsr r3, r3, #16 /* Isolate the DMinLine field */
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and r3, r3, #0xf
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mov r2, #4
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@ -93,7 +93,7 @@
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cp15_invalidate_dcache:
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mrc CP15_TR(r3) /* Read the Cache Type Register */
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mrc CP15_CTR(r3) /* Read the Cache Type Register */
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lsr r3, r3, #16 /* Isolate the DMinLine field */
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and r3, r3, #0xf
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mov r2, #4
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