SAMA5D4: Updated HSMCI header file
This commit is contained in:
Gregory Nutt
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04430796c4
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39cb768969
@ -1,7 +1,7 @@
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/****************************************************************************************
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* arch/arm/src/sama5/chip/sam_hsmci.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -79,7 +79,7 @@
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/* 0x0100-0x0124: Reserved for PCD registers */
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#define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x05fc FIFO Memory Aperture */
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/* HSMCI register adresses **************************************************************/
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/* HSMCI register addresses *************************************************************/
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#define SAM_HSMCI0_CR (SAM_HSMCI0_VBASE+SAM_HSMCI_CR_OFFSET)
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#define SAM_HSMCI0_MR (SAM_HSMCI0_VBASE+SAM_HSMCI_MR_OFFSET)
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@ -129,29 +129,31 @@
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#define SAM_HSMCI1_WPSR (SAM_HSMCI1_VBASE+SAM_HSMCI_WPSR_OFFSET)
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#define SAM_HSMCI1_FIFO (SAM_HSMCI1_VBASE+SAM_HSMCI_FIFO_OFFSET)
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#define SAM_HSMCI2_CR (SAM_HSMCI2_VBASE+SAM_HSMCI_CR_OFFSET)
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#define SAM_HSMCI2_MR (SAM_HSMCI2_VBASE+SAM_HSMCI_MR_OFFSET)
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#define SAM_HSMCI2_DTOR (SAM_HSMCI2_VBASE+SAM_HSMCI_DTOR_OFFSET)
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#define SAM_HSMCI2_SDCR (SAM_HSMCI2_VBASE+SAM_HSMCI_SDCR_OFFSET)
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#define SAM_HSMCI2_ARGR (SAM_HSMCI2_VBASE+SAM_HSMCI_ARGR_OFFSET)
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#define SAM_HSMCI2_CMDR (SAM_HSMCI2_VBASE+SAM_HSMCI_CMDR_OFFSET)
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#define SAM_HSMCI2_BLKR (SAM_HSMCI2_VBASE+SAM_HSMCI_BLKR_OFFSET)
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#define SAM_HSMCI2_CSTOR (SAM_HSMCI2_VBASE+SAM_HSMCI_CSTOR_OFFSET)
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#define SAM_HSMCI2_RSPR0 (SAM_HSMCI2_VBASE+SAM_HSMCI_RSPR0_OFFSET)
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#define SAM_HSMCI2_RSPR1 (SAM_HSMCI2_VBASE+SAM_HSMCI_RSPR1_OFFSET)
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#define SAM_HSMCI2_RSPR2 (SAM_HSMCI2_VBASE+SAM_HSMCI_RSPR2_OFFSET)
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#define SAM_HSMCI2_RSPR3 (SAM_HSMCI2_VBASE+SAM_HSMCI_RSPR3_OFFSET)
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#define SAM_HSMCI2_RDR (SAM_HSMCI2_VBASE+SAM_HSMCI_RDR_OFFSET)
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#define SAM_HSMCI2_TDR (SAM_HSMCI2_VBASE+SAM_HSMCI_TDR_OFFSET)
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#define SAM_HSMCI2_SR (SAM_HSMCI2_VBASE+SAM_HSMCI_SR_OFFSET)
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#define SAM_HSMCI2_IER (SAM_HSMCI2_VBASE+SAM_HSMCI_IER_OFFSET)
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#define SAM_HSMCI2_IDR (SAM_HSMCI2_VBASE+SAM_HSMCI_IDR_OFFSET)
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#define SAM_HSMCI2_IMR (SAM_HSMCI2_VBASE+SAM_HSMCI_IMR_OFFSET)
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#define SAM_HSMCI2_DMA (SAM_HSMCI2_VBASE+SAM_HSMCI_DMA_OFFSET)
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#define SAM_HSMCI2_CFG (SAM_HSMCI2_VBASE+SAM_HSMCI_CFG_OFFSET)
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#define SAM_HSMCI2_WPMR (SAM_HSMCI2_VBASE+SAM_HSMCI_WPMR_OFFSET)
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#define SAM_HSMCI2_WPSR (SAM_HSMCI2_VBASE+SAM_HSMCI_WPSR_OFFSET)
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#define SAM_HSMCI2_FIFO (SAM_HSMCI2_VBASE+SAM_HSMCI_FIFO_OFFSET)
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#ifdef CONFIG_SAMA5_HAVE_HSMCI2
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# define SAM_HSMCI2_CR (SAM_HSMCI2_VBASE+SAM_HSMCI_CR_OFFSET)
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# define SAM_HSMCI2_MR (SAM_HSMCI2_VBASE+SAM_HSMCI_MR_OFFSET)
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# define SAM_HSMCI2_DTOR (SAM_HSMCI2_VBASE+SAM_HSMCI_DTOR_OFFSET)
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# define SAM_HSMCI2_SDCR (SAM_HSMCI2_VBASE+SAM_HSMCI_SDCR_OFFSET)
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# define SAM_HSMCI2_ARGR (SAM_HSMCI2_VBASE+SAM_HSMCI_ARGR_OFFSET)
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# define SAM_HSMCI2_CMDR (SAM_HSMCI2_VBASE+SAM_HSMCI_CMDR_OFFSET)
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# define SAM_HSMCI2_BLKR (SAM_HSMCI2_VBASE+SAM_HSMCI_BLKR_OFFSET)
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# define SAM_HSMCI2_CSTOR (SAM_HSMCI2_VBASE+SAM_HSMCI_CSTOR_OFFSET)
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# define SAM_HSMCI2_RSPR0 (SAM_HSMCI2_VBASE+SAM_HSMCI_RSPR0_OFFSET)
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# define SAM_HSMCI2_RSPR1 (SAM_HSMCI2_VBASE+SAM_HSMCI_RSPR1_OFFSET)
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# define SAM_HSMCI2_RSPR2 (SAM_HSMCI2_VBASE+SAM_HSMCI_RSPR2_OFFSET)
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# define SAM_HSMCI2_RSPR3 (SAM_HSMCI2_VBASE+SAM_HSMCI_RSPR3_OFFSET)
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# define SAM_HSMCI2_RDR (SAM_HSMCI2_VBASE+SAM_HSMCI_RDR_OFFSET)
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# define SAM_HSMCI2_TDR (SAM_HSMCI2_VBASE+SAM_HSMCI_TDR_OFFSET)
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# define SAM_HSMCI2_SR (SAM_HSMCI2_VBASE+SAM_HSMCI_SR_OFFSET)
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# define SAM_HSMCI2_IER (SAM_HSMCI2_VBASE+SAM_HSMCI_IER_OFFSET)
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# define SAM_HSMCI2_IDR (SAM_HSMCI2_VBASE+SAM_HSMCI_IDR_OFFSET)
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# define SAM_HSMCI2_IMR (SAM_HSMCI2_VBASE+SAM_HSMCI_IMR_OFFSET)
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# define SAM_HSMCI2_DMA (SAM_HSMCI2_VBASE+SAM_HSMCI_DMA_OFFSET)
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# define SAM_HSMCI2_CFG (SAM_HSMCI2_VBASE+SAM_HSMCI_CFG_OFFSET)
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# define SAM_HSMCI2_WPMR (SAM_HSMCI2_VBASE+SAM_HSMCI_WPMR_OFFSET)
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# define SAM_HSMCI2_WPSR (SAM_HSMCI2_VBASE+SAM_HSMCI_WPSR_OFFSET)
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# define SAM_HSMCI2_FIFO (SAM_HSMCI2_VBASE+SAM_HSMCI_FIFO_OFFSET)
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#endif
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/* HSMCI register bit definitions *******************************************************/
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@ -258,13 +260,16 @@
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#define HSMCI_BLKR_BCNT_SHIFT (0) /* Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count */
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#define HSMCI_BLKR_BCNT_MASK (0xffff << HSMCI_BLKR_BCNT_SHIFT)
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# define HSMCI_BLKR_BCNT(n) ((uint32_t)(n) << HSMCI_BLKR_BCNT_SHIFT)
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#define HSMCI_BLKR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */
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#define HSMCI_BLKR_BLKLEN_MASK (0xffff << HSMCI_BLKR_BLKLEN_SHIFT)
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# define HSMCI_BLKR_BLKLEN(n) ((uint32_t)(n) << HSMCI_BLKR_BLKLEN_SHIFT)
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/* HSMCI Completion Signal Timeout Register */
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#define HSMCI_CSTOR_CSTOCYC_SHIFT (0) /* Bits 0-3: Completion Signal Timeout Cycle Number */
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#define HSMCI_CSTOR_CSTOCYC_MASK (15 << HSMCI_CSTOR_CSTOCYC_SHIFT)
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# define HSMCI_CSTOR_CSTOCYC(n) ((uint32_t)(n) << HSMCI_CSTOR_CSTOCYC_SHIFT)
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#define HSMCI_CSTOR_CSTOMUL_SHIFT (4) /* Bits 4-6: Completion Signal Timeout Multiplier */
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#define HSMCI_CSTOR_CSTOMUL_MASK (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
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# define HSMCI_CSTOR_CSTOMUL_1 (0 << HSMCI_CSTOR_CSTOMUL_SHIFT)
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@ -291,6 +296,11 @@
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#define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */
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#define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */
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#define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */
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#ifdef ATSAMA5D4
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# define HSMCI_INT_SDIOIRQB (1 << 9) /* Bit 9: SDIO Interrupt for Slot B */
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#endif
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#define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */
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#define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */
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#define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */
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@ -312,16 +322,24 @@
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/* HSMCI DMA Configuration Register */
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#define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */
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#define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT)
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#ifdef ATSAMA5D3
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# define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */
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# define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT)
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# define HSMCI_DMA_OFFSET(n) ((uint32_t)(n) << HSMCI_DMA_OFFSET_SHIFT)
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#endif
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#define HSMCI_DMA_CHKSIZE_SHIFT (4) /* Bits 4-6: DMA Channel Read and Write Chunk Size */
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#define HSMCI_DMA_CHKSIZE_MASK (7 << HSMCI_DMA_CHKSIZE_SHIFT)
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# define HSMCI_DMA_CHKSIZE_1 (0 << HSMCI_DMA_CHKSIZE_SHIFT) /* 1 data available */
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# define HSMCI_DMA_CHKSIZE_4 (1 << HSMCI_DMA_CHKSIZE_SHIFT) /* 4 data available */
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# define HSMCI_DMA_CHKSIZE_8 (2 << HSMCI_DMA_CHKSIZE_SHIFT) /* 8 data available */
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# define HSMCI_DMA_CHKSIZE_16 (3 << HSMCI_DMA_CHKSIZE_SHIFT) /* 16 data available */
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# define HSMCI_DMA_CHKSIZE_32 (4 << HSMCI_DMA_CHKSIZE_SHIFT) /* 32 data available */
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#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */
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#define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */
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#ifdef ATSAMA5D3
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# define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */
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#endif
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/* HSMCI Configuration Register */
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@ -332,21 +350,16 @@
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/* HSMCI Write Protect Mode Register */
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#define HSMCI_WPMR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */
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#define HSMCI_WPMR_WP_KEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */
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#define HSMCI_WPMR_WP_KEY_MASK (0x00ffffff << HSMCI_WPMR_WP_KEY_SHIFT)
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# define HSMCI_WPMR_WP_KEY (0x004d4349 << HSMCI_WPMR_WP_KEY_SHIFT)
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#define HSMCI_WPMR_WPEN (1 << 0) /* Bit 0: Write Protection Enable */
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#define HSMCI_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */
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#define HSMCI_WPMR_WPKEY_MASK (0x00ffffff << HSMCI_WPMR_WPKEY_SHIFT)
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# define HSMCI_WPMR_WPKEY (0x004d4349 << HSMCI_WPMR_WPKEY_SHIFT)
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/* HSMCI Write Protect Status Register */
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#define HSMCI_WPSR_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */
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#define HSMCI_WPSR_VS_MASK (15 << HSMCI_WPSR_VS_SHIFT)
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# define HSMCI_WPSR_VS_NONE (0 << HSMCI_WPSR_VS_SHIFT)
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# define HSMCI_WPSR_VS_WRITE (1 << HSMCI_WPSR_VS_SHIFT)
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# define HSMCI_WPSR_VS_RESET (2 << HSMCI_WPSR_VS_SHIFT)
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# define HSMCI_WPSR_VS_BOTH (3 << HSMCI_WPSR_VS_SHIFT)
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#define HSMCI_WPSR_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
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#define HSMCI_WPSR_VSRC_MASK (0xffff << HSMCI_WPSR_VSRC_SHIFT)
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#define HSMCI_WPSR_WPVS (1 << 0) /* Bit 0: Write Protection Violation Status */
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#define HSMCI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
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#define HSMCI_WPSR_WPVSRC_MASK (0xffff << HSMCI_WPSR_WPVSRC_SHIFT)
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/****************************************************************************************
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* Public Types
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