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LPC43xx: Tweaks to pkolesnikov's LPC4370 changes to get a clean compilation

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This commit is contained in:
Gregory Nutt 2015-10-01 10:00:25 -06:00
parent 166d307add
commit 3a07b09b9a
3 changed files with 123 additions and 42 deletions
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136
arch/arm/include/lpc43xx/chip.h
View File

@ -134,8 +134,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4310FET100)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
@ -159,8 +160,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (4) /* Four ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (4) /* Four ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4320FBD144)
# warning "Data sheet and user manual are consistement for the LPC4320"
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
@ -185,8 +187,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4320FET100)
# warning "Data sheet and user manual are consistement for the LPC4320"
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
@ -211,8 +214,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (4) /* Four ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (4) /* Four ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4330FBD144)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
@ -236,8 +240,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET100)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
@ -261,8 +266,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (4) /* Four ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (4) /* Four ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET180)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
@ -286,8 +292,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET256)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
@ -311,8 +318,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
@ -336,8 +344,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4350FET180)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
@ -361,8 +370,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4350FET256)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
@ -386,8 +396,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4353FBD208)
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (256*1025)
@ -411,8 +422,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET180)
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (256*1025)
@ -436,8 +448,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET256)
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (256*1025)
@ -461,8 +474,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET180)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
@ -486,8 +500,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4357FBD208)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
@ -511,8 +526,9 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET256)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
@ -536,8 +552,60 @@
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4370FET100)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM (plus 18Kb for Cortex-M0)*/
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (32*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (16*1024)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# undef LPC43_NLCD /* No LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
# undef LPC43_MCPWM /* No PWM capability */
# undef LPC43_QEI /* No Quadrature Encoder capability */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two C-CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels (per ADC)*/
# define LPC43_NADC12 (1) /* ONne 12-bit ADC controllers (ADCHS)*/
#elif defined(CONFIG_ARCH_CHIP_LPC4370FET256)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM (plus 18Kb for Cortex-M0)*/
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (32*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (16*1024)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# define LPC43_NLCD (1) /* One LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two C-CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels (per ADC)*/
# define LPC43_NADC12 (1) /* ONne 12-bit ADC controllers (ADCHS)*/
#else
# error "Unsupported LPC43xx chip"
#endif

5
arch/arm/src/lpc43xx/Kconfig
View File

@ -328,6 +328,11 @@ config LPC43_I2C0
bool "I2C0"
default n
config LPC43_I2C0_SUPERFAST
bool "I2C0 super fast mode"
default n
depends on LPC43_I2C0
config LPC43_I2C1
bool "I2C1"
default n

24
arch/arm/src/lpc43xx/lpc43_i2c.c
View File

@ -84,6 +84,14 @@
#define I2C_TIMEOUT (20*1000/CONFIG_USEC_PER_TICK) /* 20 mS */
#ifdef CONFIG_LPC43_I2C0_SUPERFAST
# define I2C0_DEFAULT_FREQUENCY 1000000
#else
# define I2C0_DEFAULT_FREQUENCY 400000
#endif
#define I2C1_DEFAULT_FREQUENCY 400000
/****************************************************************************
* Private Data
****************************************************************************/
@ -507,7 +515,7 @@ struct i2c_dev_s *up_i2cinitialize(int port)
#ifdef CONFIG_LPC43_I2C0
if (port == 0)
{
priv = &g_i2c0dev;
priv = &g_i2c0dev;
priv->base = LPC43_I2C0_BASE;
priv->irqid = LPC43M0_IRQ_I2C0;
priv->baseFreq = BOARD_ABP1_FREQUENCY;
@ -516,12 +524,12 @@ struct i2c_dev_s *up_i2cinitialize(int port)
regval = getreg32(LPC43_SCU_SFSI2C0);
regval |= SCU_SFSI2C0_SCL_EZI | SCU_SFSI2C0_SDA_EZI;
if (CONFIG_I2C0_FREQ == 1000000)
{
/* Super fast mode */
regval |= SCU_SFSI2C0_SCL_EHD | SCU_SFSI2C0_SDA_EHD;
}
#ifdef CONFIG_LPC43_I2C0_SUPERFAST
/* Enable super fast mode */
regval |= SCU_SFSI2C0_SCL_EHD | SCU_SFSI2C0_SDA_EHD;
#endif
putreg32(regval, LPC43_SCU_SFSI2C0);
@ -531,7 +539,7 @@ struct i2c_dev_s *up_i2cinitialize(int port)
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_APB1_I2C0_CFG);
i2c_setfrequency((struct i2c_dev_s *)priv,CONFIG_I2C0_FREQ);
i2c_setfrequency((struct i2c_dev_s *)priv, I2C0_DEFAULT_FREQUENCY);
/* No pin configuration needed */
}
@ -558,7 +566,7 @@ struct i2c_dev_s *up_i2cinitialize(int port)
lpc43_pin_config(PINCONF_I2C1_SCL);
lpc43_pin_config(PINCONF_I2C1_SDA);
i2c_setfrequency(priv,CONFIG_I2C1_FREQ);
i2c_setfrequency(priv, I2C1_DEFAULT_FREQUENCY);
}
else