Add peripheral base addresses
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2973 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
146c74732e
commit
3a0e39c72a
@ -48,19 +48,40 @@
|
||||
|
||||
/* Physical memory map */
|
||||
|
||||
#define AVR32_ONCHIP_FLASH_BASE 0x80000000 /* 512Kb Flash Array */
|
||||
# define AVR32_APPL_BASE 0x80002000 /* 8Kb offset to application w/bootloader */
|
||||
#define AVR32_USER_FLASH_BASE 0x80800000 /* Flash User Page */
|
||||
# define AVR32_BTLDR_CONFIG 0x808001fc /* Bootloader configuration word */
|
||||
#define AVR32_ONCHIP_FLASH_BASE 0x80000000 /* 512Kb Flash Array */
|
||||
# define AVR32_APPL_BASE 0x80002000 /* 8Kb offset to application w/bootloader */
|
||||
#define AVR32_USER_FLASH_BASE 0x80800000 /* Flash User Page */
|
||||
# define AVR32_BTLDR_CONFIG 0x808001fc /* Bootloader configuration word */
|
||||
|
||||
/* Memory map for systems without an MMU */
|
||||
|
||||
#define AVR32_P1_BASE 0x80000000 /* 512MB non-translated space, cacheable */
|
||||
#define AVR32_P2_BASE 0xa0000000 /* 512MB non-translated space, non-cacheable */
|
||||
#define AVR32_P3_BASE 0xc0000000 /* 512MB translated space, cacheable */
|
||||
#define AVR32_P4_BASE 0xe0000000 /* 512MB system space, non-cacheable */
|
||||
#define AVR32_P1_BASE 0x80000000 /* 512MB non-translated space, cacheable */
|
||||
#define AVR32_P2_BASE 0xa0000000 /* 512MB non-translated space, non-cacheable */
|
||||
#define AVR32_P3_BASE 0xc0000000 /* 512MB translated space, cacheable */
|
||||
#define AVR32_P4_BASE 0xe0000000 /* 512MB system space, non-cacheable */
|
||||
|
||||
/* Peripheral Address Map */
|
||||
|
||||
#define AVR32_USB_BASE 0xfffe0000 /* USB 2.0 Interface */
|
||||
#define AVR32_HMATRIX_BASE 0xfffe1000 /* HSB Matrix */
|
||||
#define AVR32_HFLASHC_BASE 0xfffe1400 /* Flash Controller */
|
||||
#define AVR32_PDCA_BASE 0xffff0000 /* Peripheral DMA Controller */
|
||||
#define AVR32_INTC_BASE 0xffff0800 /* Interrupt controller */
|
||||
#define AVR32_PM_BASE 0xffff0c00 /* Power Manager */
|
||||
#define AVR32_RTC_BASE 0xffff0d00 /* Real Time Counter */
|
||||
#define AVR32_WDT_BASE 0xffff0d30 /* Watchdog Timer */
|
||||
#define AVR32_EIM_BASE 0xffff0d80 /* External Interrupt Controller */
|
||||
#define AVR32_GPIO_BASE 0xffff1000 /* General Purpose Input/Output */
|
||||
#define AVR32_USART0_BASE 0xffff1400 /* USART0 */
|
||||
#define AVR32_USART1_BASE 0xffff1800 /* USART1 */
|
||||
#define AVR32_USART2_BASE 0xffff1c00 /* USART2 */
|
||||
#define AVR32_SPI0_BASE 0xffff2400 /* Serial Peripheral Interface 0 */
|
||||
#define AVR32_TWI_BASE 0xffff2c00 /* Two-wire Interface */
|
||||
#define AVR32_PWM_BASE 0xffff3000 /* Pulse Width Modulation Controller */
|
||||
#define AVR32_SSC_BASE 0xffff3400 /* Synchronous Serial Controller */
|
||||
#define AVR32_TC_BASE 0xffff3800 /* Timer/Counter */
|
||||
#define AVR32_ADC_BASE 0xffff3c00 /* Analog to Digital Converter */
|
||||
#define AVR32_ABDAC_BASE 0xffff4000 /* Audio Bitstream DAC */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
|
||||
102
arch/avr/src/at91uc3/at91uc3_usart.h
Executable file
102
arch/avr/src/at91uc3/at91uc3_usart.h
Executable file
@ -0,0 +1,102 @@
|
||||
/************************************************************************************
|
||||
* arch/avr/src/at91uc3/at91uc3_usart.h
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_AVR_SRC_AT91UC3_AT91UC3_USART_H
|
||||
#define __ARCH_AVR_SRC_AT91UC3_AT91UC3_USART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define AVR32_USART_CR_OFFSET 0x0000 /* Control Register */
|
||||
#define AVR32_USART_MR_OFFSET 0x0004 /* Mode Register */
|
||||
#define AVR32_USART_IER_OFFSET 0x0008 /* Interrupt Enable Register */
|
||||
#define AVR32_USART_IDR_OFFSET 0x000c /* Interrupt Disable Register */
|
||||
#define AVR32_USART_IMR_OFFSET 0x0010 /* Interrupt Mask Register */
|
||||
#define AVR32_USART_CSR_OFFSET 0x0014 /* Channel Status Register */
|
||||
#define AVR32_USART_RHR_OFFSET 0x0018 /* Receiver Holding Register */
|
||||
#define AVR32_USART_THR_OFFSET 0x001c /* Transmitter Holding Register */
|
||||
#define AVR32_USART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register */
|
||||
#define AVR32_USART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register */
|
||||
#define AVR32_USART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register */
|
||||
#define AVR32_USART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register */
|
||||
#define AVR32_USART_NER_OFFSET 0x0044 /* Number of Errors Register */
|
||||
#define AVR32_USART_IFR_OFFSET 0x004c /* IrDA Filter Register */
|
||||
#define AVR32_USART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register */
|
||||
#define AVR32_USART_VERSION_OFFSET 0x00fc /* Version Register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define AVR32_USART0_CR (AVR32_USART0_BASE+AVR32_USART_CR_OFFSET)
|
||||
#define AVR32_USART0_MR (AVR32_USART0_BASE+AVR32_USART_MR_OFFSET)
|
||||
#define AVR32_USART0_IER (AVR32_USART0_BASE+AVR32_USART_IER_OFFSET)
|
||||
#define AVR32_USART0_IDR (AVR32_USART0_BASE+AVR32_USART_IDR_OFFSET)
|
||||
#define AVR32_USART0_IMR (AVR32_USART0_BASE+AVR32_USART_IMR_OFFSET)
|
||||
#define AVR32_USART0_CSR (AVR32_USART0_BASE+AVR32_USART_CSR_OFFSET)
|
||||
#define AVR32_USART0_RHR (AVR32_USART0_BASE+AVR32_USART_RHR_OFFSET)
|
||||
#define AVR32_USART0_THR (AVR32_USART0_BASE+AVR32_USART_THR_OFFSET)
|
||||
#define AVR32_USART0_BRGR (AVR32_USART0_BASE+AVR32_USART_BRGR_OFFSET)
|
||||
#define AVR32_USART0_RTOR (AVR32_USART0_BASE+AVR32_USART_RTOR_OFFSET)
|
||||
#define AVR32_USART0_TTGR (AVR32_USART0_BASE+AVR32_USART_TTGR_OFFSET)
|
||||
#define AVR32_USART0_FIDI (AVR32_USART0_BASE+AVR32_USART_FIDI_OFFSET)
|
||||
#define AVR32_USART0_NER (AVR32_USART0_BASE+AVR32_USART_NER_OFFSET)
|
||||
#define AVR32_USART0_IFR (AVR32_USART0_BASE+AVR32_USART_IFR_OFFSET)
|
||||
#define AVR32_USART0_MAN (AVR32_USART0_BASE+AVR32_USART_MAN_OFFSET)
|
||||
#define AVR32_USART0_VERSION (AVR32_USART0_BASE+AVR32_USART_VERSION_OFFSET)
|
||||
|
||||
/* Register Bit-field Definitions ***************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_AVR_SRC_AT91UC3_AT91UC3_USART_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user