i.MX6: Put in basic framework for interrupt handling
This commit is contained in:
Gregory Nutt
parent
a0783791a9
commit
3a14a4c4c6
153
arch/arm/src/armv7-a/arm_gic.c
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153
arch/arm/src/armv7-a/arm_gic.c
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/****************************************************************************
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* arch/arm/src/armv7-a/arm_gic.c
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include "gic.h"
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#ifdef CONFIG_ARMV7A_HAVE_GIC
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: arm_gic_initialize
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*
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* Description:
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* Perform basic GIC initialization for the current CPU
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void arm_gic_initialize(void)
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{
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# warning Missing logic
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}
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/****************************************************************************
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* Name: arm_decodeirq
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*
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* Description:
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* This function is called from the IRQ vector handler in arm_vectors.S.
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* At this point, the interrupt has been taken and the registers have
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* been saved on the stack. This function simply needs to determine the
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* the irq number of the interrupt and then to call arm_doirq to dispatch
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* the interrupt.
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*
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* Input parameters:
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* regs - A pointer to the register save area on the stack.
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*
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****************************************************************************/
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uint32_t *arm_decodeirq(uint32_t *regs)
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{
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# warning Missing logic
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return regs;
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}
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/****************************************************************************
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* Name: up_enable_irq
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*
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* Description:
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* On many architectures, there are three levels of interrupt enabling: (1)
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* at the global level, (2) at the level of the interrupt controller,
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* and (3) at the device level. In order to receive interrupts, they
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* must be enabled at all three levels.
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*
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* This function implements enabling of the device specified by 'irq'
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* at the interrupt controller level if supported by the architecture
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* (up_irq_restore() supports the global level, the device level is hardware
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* specific).
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*
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* Since this API is not supported on all architectures, it should be
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* avoided in common implementations where possible.
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*
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****************************************************************************/
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void up_enable_irq(int irq)
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{
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# warning Missnig logic
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}
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/****************************************************************************
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* Name: up_disable_irq
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*
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* Description:
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* This function implements disabling of the device specified by 'irq'
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* at the interrupt controller level if supported by the architecture
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* (up_irq_save() supports the global level, the device level is hardware
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* specific).
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*
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* Since this API is not supported on all architectures, it should be
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* avoided in common implementations where possible.
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*
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****************************************************************************/
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void up_disable_irq(int irq)
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{
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# warning Missnig logic
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}
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/****************************************************************************
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* Name: up_prioritize_irq
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*
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* Description:
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* Set the priority of an IRQ.
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*
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* Since this API is not supported on all architectures, it should be
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* avoided in common implementations where possible.
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*
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****************************************************************************/
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int up_prioritize_irq(int irq, int priority)
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{
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# warning Missnig logic
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return OK;
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}
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#endif /* CONFIG_ARMV7A_HAVE_GIC */
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@ -71,8 +71,8 @@ CMN_CSRCS += up_puts.c up_mdelay.c up_stackframe.c up_udelay.c
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CMN_CSRCS += up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
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CMN_CSRCS += arm_assert.c arm_blocktask.c arm_copyfullstate.c arm_dataabort.c
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CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_mmu.c arm_prefetchabort.c
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CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c
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CMN_CSRCS += arm_doirq.c arm_gic.c arm_initialstate.c arm_mmu.c
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CMN_CSRCS += arm_prefetchabort.c arm_releasepending.c arm_reprioritizertr.c
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CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
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CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c
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@ -132,4 +132,4 @@ CHIP_ASRCS =
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# i.MX6-specific C source files
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CHIP_CSRCS = imx_boot.c imx_memorymap.c
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CHIP_CSRCS = imx_boot.c imx_memorymap.c imx_irq.c
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134
arch/arm/src/imx6/imx_irq.c
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134
arch/arm/src/imx6/imx_irq.c
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/****************************************************************************
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* arch/arm/src/imx6/imx_irq.c
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <assert.h>
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#include <nuttx/arch.h>
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#include "up_internal.h"
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#include "sctlr.h"
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#include "gic.h"
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/****************************************************************************
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* Public Data
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****************************************************************************/
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volatile uint32_t *current_regs;
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/* Symbols defined via the linker script */
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extern uint32_t _vector_start; /* Beginning of vector block */
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extern uint32_t _vector_end; /* End+1 of vector block */
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_irqinitialize
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*
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* Description:
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* This function is called by up_initialize() during the bring-up of the
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* system. It is the responsibility of this function to but the interrupt
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* subsystem into the working and ready state.
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*
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****************************************************************************/
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void up_irqinitialize(void)
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{
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/* The following operations need to be atomic, but since this function is
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* called early in the initialization sequence, we expect to have exclusive
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* access to the GIC.
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*/
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/* Colorize the interrupt stack for debug purposes */
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#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
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{
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size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
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up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
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intstack_size);
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}
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#endif
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/* Initialize the Generic Interrupt Controller (GIC) for this CPU */
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arm_gic_initialize();
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#ifdef CONFIG_ARCH_LOWVECTORS
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/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
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* beginning of the .text region must appear at address at the address
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* specified in the VBAR. There are two ways to accomplish this:
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*
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* 1. By explicitly mapping the beginning of .text region with a page
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* table entry so that the virtual address zero maps to the beginning
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* of the .text region. VBAR == 0x0000:0000.
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*
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* 2. Set the Cortex-A5 VBAR register so that the vector table address
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* is moved to a location other than 0x0000:0000.
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*
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* The second method is used by this logic.
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*/
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/* Set the VBAR register to the address of the vector table */
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DEBUGASSERT((((uintptr_t)&_vector_start) & ~VBAR_MASK) == 0);
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cp15_wrvbar((uint32_t)&_vector_start);
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#endif /* CONFIG_ARCH_LOWVECTORS */
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/* currents_regs is non-NULL only while processing an interrupt */
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current_regs = NULL;
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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/* Initialize logic to support a second level of interrupt decoding for
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* PIO pins.
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*/
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#ifdef CONFIG_IMX6_PIO_IRQ
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imx_pioirq_initialize();
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#endif
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/* And finally, enable interrupts */
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(void)up_irq_enable();
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#endif
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}
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