arch: imxrt: Fix CONFIG_IMXRT_ENET_ENHANCEDBD
Summary: - I noticed that CONFIG_IMXRT_ENET_ENHANCEDBD is not correctly used though it is defined in Kconfig. - This commit fixes this issue. Impact: - None Testing: - Tested with imxrt1060-evk:netnsh_dcache_wb (will be added later) Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
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e6e2017d3c
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@ -640,7 +640,7 @@
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/* Legacy Buffer Descriptor */
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#ifdef CONFIG_ENET_ENHANCEDBD
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#ifdef CONFIG_IMXRT_ENET_ENHANCEDBD
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#ifdef IMXRT_USE_DBSWAP
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/* When DBSWP is used to swap the bytes in hardware, it is done 32-bits
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* at a time. Therefore, all 16 bit elements need to be swapped to
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@ -675,7 +675,7 @@ struct enet_desc_s
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uint32_t reserved2; /* unused */
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};
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#endif /* IMXRT_USE_DBSWAP */
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#else /* CONFIG_ENET_ENHANCEDBD */
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#else /* CONFIG_IMXRT_ENET_ENHANCEDBD */
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#ifdef IMXRT_USE_DBSWAP
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struct enet_desc_s
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{
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@ -691,7 +691,7 @@ struct enet_desc_s
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uint8_t *data; /* Buffer address */
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};
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#endif /* IMXRT_USE_DBSWAP */
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#endif /* CONFIG_ENET_ENHANCEDBD */
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#endif /* CONFIG_IMXRT_ENET_ENHANCEDBD */
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/****************************************************************************
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* Public Data
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@ -159,7 +159,8 @@
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* REVISIT: The size of descriptors and buffers must also be in even units
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* of the cache line size That is because the operations to clean and
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* invalidate the cache will operate on a full 32-byte cache line. If
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* CONFIG_ENET_ENHANCEDBD is selected, then the size of the descriptor is
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* CONFIG_IMXRT_ENET_ENHANCEDBD is selected,
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* then the size of the descriptor is
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* 32-bytes (and probably already the correct size for the cache line);
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* otherwise, the size of the descriptors much smaller, only 8 bytes.
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*/
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@ -665,7 +666,7 @@ static int imxrt_transmit(struct imxrt_driver_s *priv)
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*/
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txdesc->length = imxrt_swap16(priv->dev.d_len);
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#ifdef CONFIG_IMXRT_ENETENHANCEDBD
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#ifdef CONFIG_IMXRT_ENET_ENHANCEDBD
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txdesc->bdu = 0x00000000;
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txdesc->status2 = TXDESC_INT | TXDESC_TS; /* | TXDESC_IINS | TXDESC_PINS; */
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#endif
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@ -1343,7 +1344,7 @@ static int imxrt_ifup_action(struct net_driver_s *dev, bool resetphy)
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/* Select legacy of enhanced buffer descriptor format */
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#ifdef CONFIG_IMXRT_ENETENHANCEDBD
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#ifdef CONFIG_IMXRT_ENET_ENHANCEDBD
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imxrt_enet_putreg32(priv, ENET_ECR_EN1588, IMXRT_ENET_ECR_OFFSET);
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#else
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imxrt_enet_putreg32(priv, 0, IMXRT_ENET_ECR_OFFSET);
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@ -2608,7 +2609,7 @@ static void imxrt_initbuffers(struct imxrt_driver_s *priv)
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priv->txdesc[i].status1 = 0;
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priv->txdesc[i].length = 0;
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priv->txdesc[i].data = (uint8_t *)imxrt_swap32((uint32_t)addr);
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#ifdef CONFIG_IMXRT_ENETENHANCEDBD
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#ifdef CONFIG_IMXRT_ENET_ENHANCEDBD
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priv->txdesc[i].status2 = TXDESC_IINS | TXDESC_PINS;
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#endif
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addr += ALIGNED_BUFSIZE;
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@ -2621,7 +2622,7 @@ static void imxrt_initbuffers(struct imxrt_driver_s *priv)
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priv->rxdesc[i].status1 = RXDESC_E;
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priv->rxdesc[i].length = 0;
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priv->rxdesc[i].data = (uint8_t *)imxrt_swap32((uint32_t)addr);
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#ifdef CONFIG_IMXRT_ENETENHANCEDBD
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#ifdef CONFIG_IMXRT_ENET_ENHANCEDBD
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priv->rxdesc[i].bdu = 0;
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priv->rxdesc[i].status2 = RXDESC_INT;
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#endif
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