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support stm32f429i-disco run open flash loader

Browse Source 
We can use the driver in nuttx to download
files with debugger

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: chao an <anchao@xiaomi.com>
This commit is contained in:
anjiahao 2023-05-16 20:02:22 +08:00 committed by Xiang Xiao
parent 7c8bb8c293
commit 3a808bab19
9 changed files with 241 additions and 3 deletions
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2
arch/arm/src/armv7-r/arm.h
View File

@ -125,7 +125,7 @@ extern "C"
*
****************************************************************************/
void arm_boot(void) noreturn_function;
void arm_boot(void);
/****************************************************************************
* Name: arm_data_initialize

2
arch/arm/src/stm32/stm32_start.c
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@ -200,5 +200,7 @@ void __start(void)
/* Shouldn't get here */
#ifndef CONFIG_DISABLE_IDLE_LOOP
for (; ; );
#endif
}

56
boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig Normal file
View File

@ -0,0 +1,56 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_ARCH_FPU is not set
# CONFIG_STM32_FLASH_PREFETCH is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="stm32f429i-disco"
CONFIG_ARCH_BOARD_STM32F429I_DISCO=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F429Z=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BCH=y
CONFIG_BOARD_LATE_INITIALIZE=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DRVR_MKRD=y
CONFIG_FRAME_POINTER=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_HEAP2_BASE=0xD0000000
CONFIG_HEAP2_SIZE=8388608
CONFIG_INIT_ENTRYNAME="ofloader"
CONFIG_INIT_ENTRYPOINT="ofloader_main"
CONFIG_INTELHEX_BINARY=y
CONFIG_MM_REGIONS=3
CONFIG_MTD=y
CONFIG_MTD_PROGMEM=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_FLASH_CONFIG_I=y
CONFIG_STM32_FMC=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_USART1=y
CONFIG_SYSTEM_OFLOADER=y
CONFIG_SYSTEM_OFLOADER_BUFFERSIZE=4096
CONFIG_SYSTEM_OFLOADER_DEBUG=y
CONFIG_SYSTEM_OFLOADER_TABLE="/dev/flash,0x08000000,0x20000"
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART1_SERIAL_CONSOLE=y

5
boards/arm/stm32/stm32f429i-disco/scripts/Make.defs
View File

@ -22,7 +22,12 @@ include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
ifeq ($(CONFIG_SYSTEM_OFLOADER),y)
LDSCRIPT = ofloader.ld
else
LDSCRIPT = ld.script
endif
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10

149
boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld Normal file
View File

@ -0,0 +1,149 @@
/****************************************************************************
* boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* The STM32F429ZIT6 has 2048Kb of sram beginning at address 0x0800:0000 and
* 256Kb of SRAM. SRAM is split up into four blocks:
*
* 1) 112Kb of SRAM beginning at address 0x2000:0000
* 2) 16Kb of SRAM beginning at address 0x2001:c000
* 3) 64Kb of SRAM beginning at address 0x2002:0000
* 4) 64Kb of CCM SRAM beginning at address 0x1000:0000
*
* When booting from sram, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
* the 0x0800:0000 address
* range.
*/
MEMORY
{
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{
PrgCode : ALIGN(4) {
KEEP(*(PrgCode PrgCode.*));
. = ALIGN(4);
} > sram
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > sram
.init_section : ALIGN(4) {
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > sram
.ARM.extab : ALIGN(4) {
*(.ARM.extab*)
} > sram
.ARM.exidx : ALIGN(4) {
__exidx_start = ABSOLUTE(.);
*(.ARM.exidx*)
__exidx_end = ABSOLUTE(.);
} > sram
.tdata : {
_stdata = ABSOLUTE(.);
*(.tdata .tdata.* .gnu.linkonce.td.*);
_etdata = ABSOLUTE(.);
} > sram
.tbss : {
_stbss = ABSOLUTE(.);
*(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon);
_etbss = ABSOLUTE(.);
} > sram
PrgData : ALIGN(4) {
KEEP(*(PrgData PrgData.*))
. = ALIGN(4);
} > sram
_eronly = ABSOLUTE(.);
/* The RAM vector table (if present) should lie at the beginning of SRAM */
.ram_vectors : {
*(.ram_vectors)
} > sram
.data : ALIGN(4) {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > sram
DevDscr : ALIGN(4) {
KEEP(*(DevDscr DevDscr.*));
KEEP(*(DevStack DevStack.*))
. = ALIGN(4);
/* StackBuff are the stack used to run opeflashloder,
* and the location of the transmitted buffer.
*/
} > sram
.bss : ALIGN(4) {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

19
boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c
View File

@ -37,7 +37,7 @@
# include <nuttx/mmcsd.h>
#endif
#ifdef CONFIG_MTD_SST25XX
#if defined(CONFIG_MTD_SST25XX) || defined(CONFIG_MTD_PROGMEM)
# include <nuttx/mtd/mtd.h>
#endif
@ -99,8 +99,10 @@ int stm32_bringup(void)
#endif
#if defined(CONFIG_MTD)
struct mtd_dev_s *mtd;
#if defined (CONFIG_MTD_SST25XX)
struct mtd_geometry_s geo;
#endif
#endif
#if defined(CONFIG_MTD_PARTITION_NAMES)
const char *partname = CONFIG_STM32F429I_DISCO_FLASH_PART_NAMES;
#endif
@ -120,6 +122,21 @@ int stm32_bringup(void)
/* Configure SPI-based devices */
#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PROGMEM)
mtd = progmem_initialize();
if (mtd == NULL)
{
syslog(LOG_ERR, "ERROR: progmem_initialize\n");
}
ret = register_mtddriver("/dev/flash", mtd, 0, mtd);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: register_mtddriver() failed: %d\n", ret);
}
#endif
#ifdef CONFIG_STM32_SPI4
/* Get the SPI port */

2
include/nuttx/init.h
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@ -98,7 +98,7 @@ EXTERN uint8_t g_nx_initstate; /* See enum nx_initstate_e */
/* OS entry point called by boot logic */
void nx_start(void) noreturn_function;
void nx_start(void);
#undef EXTERN
#ifdef __cplusplus

7
sched/Kconfig
View File

@ -46,6 +46,13 @@ config DISABLE_ENVIRON
endif # DISABLE_OS_API
config DISABLE_IDLE_LOOP
bool
default n
---help---
This option allows nx_start to return instead of
entering the idle loop.
menu "Clocks and Timers"
config ARCH_HAVE_TICKLESS

2
sched/init/nx_start.c
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@ -698,10 +698,12 @@ void nx_start(void)
/* When control is return to this point, the system is idle. */
sinfo("CPU0: Beginning Idle Loop\n");
#ifndef CONFIG_DISABLE_IDLE_LOOP
for (; ; )
{
/* Perform any processor-specific idle state operations */
up_idle();
}
#endif
}