From 3b07bc6716b7b5f446b744f8f035fc764970fcff Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 25 Feb 2014 10:56:23 -0600 Subject: [PATCH] SAM4E: Update SAM3/4 TC and DMAC register definition header files --- Documentation/NuttX.html | 6 +- arch/arm/src/sam34/Kconfig | 2 +- arch/arm/src/sam34/Make.defs | 4 +- arch/arm/src/sam34/chip/sam4e_memorymap.h | 14 +- arch/arm/src/sam34/chip/sam4s_memorymap.h | 3 +- .../sam34/chip/{sam3u_dmac.h => sam_dmac.h} | 204 +++-- arch/arm/src/sam34/chip/sam_tc.h | 729 +++++++++++------- arch/arm/src/sam34/chip/sam_twi.h | 65 +- .../src/sam34/{sam3u_dmac.c => sam_dmac.c} | 8 +- arch/arm/src/sam34/sam_hsmci.c | 6 +- configs/arduino-due/README.txt | 2 +- configs/arduino-due/nsh/defconfig | 2 +- configs/arduino-due/ostest/defconfig | 2 +- configs/sam3u-ek/README.txt | 4 +- configs/sam3u-ek/knsh/defconfig | 2 +- configs/sam3u-ek/nsh/defconfig | 2 +- configs/sam3u-ek/nx/defconfig | 2 +- configs/sam3u-ek/nxwm/defconfig | 2 +- configs/sam3u-ek/ostest/defconfig | 2 +- 19 files changed, 655 insertions(+), 406 deletions(-) rename arch/arm/src/sam34/chip/{sam3u_dmac.h => sam_dmac.h} (75%) rename arch/arm/src/sam34/{sam3u_dmac.c => sam_dmac.c} (99%) diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html index 95050becc0..28a3badf7a 100644 --- a/Documentation/NuttX.html +++ b/Documentation/NuttX.html @@ -1980,10 +1980,10 @@ nsh>

diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig index 1bf4b1476f..e5a4aa20c9 100644 --- a/arch/arm/src/sam34/Kconfig +++ b/arch/arm/src/sam34/Kconfig @@ -510,7 +510,7 @@ config SAM34_PDCA depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E select ARCH_DMA -config SAM34_DMA +config SAM34_DMAC bool "DMA controller" default n depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs index db235cad5f..3e8fe88fe2 100644 --- a/arch/arm/src/sam34/Make.defs +++ b/arch/arm/src/sam34/Make.defs @@ -92,8 +92,8 @@ ifeq ($(CONFIG_NUTTX_KERNEL),y) CHIP_CSRCS += sam_userspace.c sam_mpuinit.c endif -ifeq ($(CONFIG_SAM34_DMA),y) -CHIP_CSRCS += sam3u_dmac.c +ifeq ($(CONFIG_SAM34_DMAC),y) +CHIP_CSRCS += sam_dmac.c endif ifeq ($(CONFIG_SAM34_PDCA),y) diff --git a/arch/arm/src/sam34/chip/sam4e_memorymap.h b/arch/arm/src/sam34/chip/sam4e_memorymap.h index 7741436316..019acbd846 100644 --- a/arch/arm/src/sam34/chip/sam4e_memorymap.h +++ b/arch/arm/src/sam34/chip/sam4e_memorymap.h @@ -93,10 +93,16 @@ # define SAM_TC0_BASE 0x40090000 /* 0x40090000-0x4009003f: Timer Counter 0 */ # define SAM_TC1_BASE 0x40090040 /* 0x40090040-0x4009007f: Timer Counter 1 */ # define SAM_TC2_BASE 0x40090080 /* 0x40090080-0x400900bf: Timer Counter 2 */ -#define SAM_TC345_BASE 0x40098000 /* 0x40098000-0x40097fff: Timer Counters 3-5 */ -# define SAM_TC3_BASE 0x40098000 /* 0x40098000-0x4009003f: Timer Counter 3 */ -# define SAM_TC4_BASE 0x40098040 /* 0x40098040-0x4009007f: Timer Counter 4 */ -# define SAM_TC5_BASE 0x40098080 /* 0x40098080-0x400900bf: Timer Counter 5 */ + /* 0x400900c0-0x40093fff Reserved */ +#define SAM_TC345_BASE 0x40094000 /* 0x40094000-0x40094fff: Timer Counters 3-5 */ +# define SAM_TC3_BASE 0x40094000 /* 0x40094000-0x4009403f: Timer Counter 3 */ +# define SAM_TC4_BASE 0x40094040 /* 0x40094040-0x4009407f: Timer Counter 4 */ +# define SAM_TC5_BASE 0x40094080 /* 0x40094080-0x400940bf: Timer Counter 5 */ + /* 0x400940c0-0x40097fff Reserved */ +#define SAM_TC678_BASE 0x40098000 /* 0x40098000-0x40097fff: Timer Counters 6-8 */ +# define SAM_TC6_BASE 0x40098000 /* 0x40098000-0x4009003f: Timer Counter 6 */ +# define SAM_TC7_BASE 0x40098040 /* 0x40098040-0x4009007f: Timer Counter 7 */ +# define SAM_TC8_BASE 0x40098080 /* 0x40098080-0x400900bf: Timer Counter 8 */ /* 0x4009c000-0x4009ffff: Reserved */ #define SAM_USART_BASE 0x400a0000 /* 0x400a0000-0x400abfff: USART */ # define SAM_USART0_BASE 0x400a0000 /* 0x400a0000-0x400a3fff: USART0 */ diff --git a/arch/arm/src/sam34/chip/sam4s_memorymap.h b/arch/arm/src/sam34/chip/sam4s_memorymap.h index 111109ae6c..7ff388df67 100644 --- a/arch/arm/src/sam34/chip/sam4s_memorymap.h +++ b/arch/arm/src/sam34/chip/sam4s_memorymap.h @@ -73,11 +73,12 @@ #define SAM_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */ #define SAM_SPI0_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ /* 0x4000c000-0x4000ffff: Reserved */ -#define SAM_TC_BASE 0x40010000 /* 0x40010000-0x40017fff: Timer Counters */ +#define SAM_TC012_BASE 0x40010000 /* 0x40010000-0x400100bf: Timer Counters 0-2 */ # define SAM_TC0_BASE 0x40080000 /* 0x40010000-0x4001003f: Timer Counter 0 */ # define SAM_TC1_BASE 0x40080040 /* 0x40010040-0x4001007f: Timer Counter 1 */ # define SAM_TC2_BASE 0x40080080 /* 0x40010080-0x400100bf: Timer Counter 2 */ /* 0x400100c0-0x40013fff Reserved */ +#define SAM_TC345_BASE 0x40080000 /* 0x40014000-0x400140bf: Timer Counters 3-5 */ # define SAM_TC3_BASE 0x40080000 /* 0x40014000-0x4001403f: Timer Counter 3 */ # define SAM_TC4_BASE 0x40080040 /* 0x40014040-0x4001407f: Timer Counter 4 */ # define SAM_TC5_BASE 0x40080080 /* 0x40014080-0x400140bf: Timer Counter 5 */ diff --git a/arch/arm/src/sam34/chip/sam3u_dmac.h b/arch/arm/src/sam34/chip/sam_dmac.h similarity index 75% rename from arch/arm/src/sam34/chip/sam3u_dmac.h rename to arch/arm/src/sam34/chip/sam_dmac.h index a64f9764b3..a8d3a5305e 100644 --- a/arch/arm/src/sam34/chip/sam3u_dmac.h +++ b/arch/arm/src/sam34/chip/sam_dmac.h @@ -1,7 +1,8 @@ /**************************************************************************************** - * arch/arm/src/sam34/chip/sam3u_dmac.h + * arch/arm/src/sam34/chip/sam_dmac.h + * DMA Controller (DMAC) definitions for the SAM3U, SAM3X, SAM3A, and RCH_CHIP_SAM4E * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +34,8 @@ * ****************************************************************************************/ -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_DMAC_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_DMAC_H +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_DMAC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_DMAC_H /**************************************************************************************** * Included Files @@ -53,36 +54,42 @@ /* Global Registers */ -#define SAM_DMAC_GCFG_OFFSET 0x00 /* DMAC Global Configuration Register */ -#define SAM_DMAC_EN_OFFSET 0x04 /* DMAC Enable Register */ -#define SAM_DMAC_SREQ_OFFSET 0x08 /* DMAC Software Single Request Register */ -#define SAM_DMAC_CREQ_OFFSET 0x0c /* DMAC Software Chunk Transfer Request Register */ -#define SAM_DMAC_LAST_OFFSET 0x10 /* DMAC Software Last Transfer Flag Register */ - /* 0x014: Reserved */ -#define SAM_DMAC_EBCIER_OFFSET 0x18 /* DMAC Error Enable */ -#define SAM_DMAC_EBCIDR_OFFSET 0x1C /* DMAC Error Disable */ -#define SAM_DMAC_EBCIMR_OFFSET 0x20 /* DMAC Error Mask */ -#define SAM_DMAC_EBCISR_OFFSET 0x24 /* DMAC Error Status */ -#define SAM_DMAC_CHER_OFFSET 0x28 /* DMAC Channel Handler Enable Register */ -#define SAM_DMAC_CHDR_OFFSET 0x2c /* DMAC Channel Handler Disable Register */ -#define SAM_DMAC_CHSR_OFFSET 0x30 /* DMAC Channel Handler Status Register */ - /* 0x034-0x38: Reserved */ +#define SAM_DMAC_GCFG_OFFSET 0x0000 /* DMAC Global Configuration Register */ +#define SAM_DMAC_EN_OFFSET 0x0004 /* DMAC Enable Register */ +#define SAM_DMAC_SREQ_OFFSET 0x0008 /* DMAC Software Single Request Register */ +#define SAM_DMAC_CREQ_OFFSET 0x000c /* DMAC Software Chunk Transfer Request Register */ +#define SAM_DMAC_LAST_OFFSET 0x0010 /* DMAC Software Last Transfer Flag Register */ + /* 0x014: Reserved */ +#define SAM_DMAC_EBCIER_OFFSET 0x0018 /* DMAC Error Enable */ +#define SAM_DMAC_EBCIDR_OFFSET 0x001C /* DMAC Error Disable */ +#define SAM_DMAC_EBCIMR_OFFSET 0x0020 /* DMAC Error Mask */ +#define SAM_DMAC_EBCISR_OFFSET 0x0024 /* DMAC Error Status */ +#define SAM_DMAC_CHER_OFFSET 0x0028 /* DMAC Channel Handler Enable Register */ +#define SAM_DMAC_CHDR_OFFSET 0x002c /* DMAC Channel Handler Disable Register */ +#define SAM_DMAC_CHSR_OFFSET 0x0030 /* DMAC Channel Handler Status Register */ + /* 0x034-0x38: Reserved */ /* DMA channel registers */ -#define SAM_DMACHAN_OFFSET(n) (0x3c+((n)*0x28)) -#define SAM_DMACHAN0_OFFSET 0x3c /* 0x3c-0x60: Channel 0 */ -#define SAM_DMACHAN1_OFFSET 0x64 /* 0x64-0x88: Channel 1 */ -#define SAM_DMACHAN2_OFFSET 0x8c /* 0x8c-0xb0: Channel 2 */ -#define SAM_DMACHAN3_OFFSET 0xb4 /* 0xb4-0xd8: Channel 3 */ +#define SAM_DMACHAN_OFFSET(n) (0x003c+((n)*0x28)) +#define SAM_DMACHAN0_OFFSET 0x003c /* 0x3c-0x60: Channel 0 */ +#define SAM_DMACHAN1_OFFSET 0x0064 /* 0x64-0x88: Channel 1 */ +#define SAM_DMACHAN2_OFFSET 0x008c /* 0x8c-0xb0: Channel 2 */ +#define SAM_DMACHAN3_OFFSET 0x00b4 /* 0xb4-0xd8: Channel 3 */ -#define SAM_DMACHAN_SADDR_OFFSET 0x00 /* DMAC Channel Source Address Register */ -#define SAM_DMACHAN_DADDR_OFFSET 0x04 /* DMAC Channel Destination Address Register */ -#define SAM_DMACHAN_DSCR_OFFSET 0x08 /* DMAC Channel Descriptor Address Register */ -#define SAM_DMACHAN_CTRLA_OFFSET 0x0c /* DMAC Channel Control A Register */ -#define SAM_DMACHAN_CTRLB_OFFSET 0x10 /* DMAC Channel Control B Register */ -#define SAM_DMACHAN_CFG_OFFSET 0x14 /* DMAC Channel Configuration Register */ +#define SAM_DMACHAN_SADDR_OFFSET 0x0000 /* DMAC Channel Source Address Register */ +#define SAM_DMACHAN_DADDR_OFFSET 0x0004 /* DMAC Channel Destination Address Register */ +#define SAM_DMACHAN_DSCR_OFFSET 0x0008 /* DMAC Channel Descriptor Address Register */ +#define SAM_DMACHAN_CTRLA_OFFSET 0x000c /* DMAC Channel Control A Register */ +#define SAM_DMACHAN_CTRLB_OFFSET 0x0010 /* DMAC Channel Control B Register */ +#define SAM_DMACHAN_CFG_OFFSET 0x0014 /* DMAC Channel Configuration Register */ /* 0x18-0x24: Reserved */ - /* 0x017c-0x1fc: Reserved */ + +/* More Global Registers */ + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_DMAC_WPMR_OFFSET 0x01e4 /* DMAC Write Protect Mode Register */ +# define SAM_DMAC_WPSR_OFFSET 0x01e8 /* DMAC Write Protect Status Register DMAC_WPSR */ +#endif /* DMAC register adresses ***************************************************************/ @@ -144,6 +151,13 @@ #define SAM_DMACHAN3_CTRLB (SAM_DMACHAN3_BASE+SAM_DMACHAN_CTRLB_OFFSET) #define SAM_DMACHAN3_CFG (SAM_DMACHAN3_BASE+SAM_DMACHAN_CFG_OFFSET) +/* More Global Registers */ + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_DMAC_WPMR (SAM_DMAC_BASE+SAM_DMAC_WPMR_OFFSET) +# define SAM_DMAC_WPSR (SAM_DMAC_BASE+SAM_DMAC_WPSR_OFFSET) +#endif + /* DMAC register bit definitions ********************************************************/ /* Global Registers */ @@ -160,14 +174,14 @@ #define DMAC_SREQ_SHIFT(n) ((n)<<1) #define DMAC_SREQ_MASK(n) (3 << DMAC_SREQ_SHIFT(n)) -#define DMAC_SREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */ -#define DMAC_SREQ0_MASK (3 << DMAC_SREQ0_SHIFT) -#define DMAC_SREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */ -#define DMAC_SREQ1_MASK (3 << DMAC_SREQ1_SHIFT) -#define DMAC_SREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */ -#define DMAC_SREQ2_MASK (3 << DMAC_SREQ2_SHIFT) -#define DMAC_SREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */ -#define DMAC_SREQ3_MASK (3 << DMAC_SREQ3_SHIFT) +# define DMAC_SREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */ +# define DMAC_SREQ0_MASK (3 << DMAC_SREQ0_SHIFT) +# define DMAC_SREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */ +# define DMAC_SREQ1_MASK (3 << DMAC_SREQ1_SHIFT) +# define DMAC_SREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */ +# define DMAC_SREQ2_MASK (3 << DMAC_SREQ2_SHIFT) +# define DMAC_SREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */ +# define DMAC_SREQ3_MASK (3 << DMAC_SREQ3_SHIFT) #define DMAC_SREQ_SSREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source single transfer */ # define DMAC_SREQ_SSREQ(n) (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ_SHIFT(n))) @@ -186,14 +200,14 @@ #define DMAC_CREQ_SHIFT(n) ((n)<<1) #define DMAC_CREQ_MASK(n) (3 << DMAC_CREQ_SHIFT(n)) -#define DMAC_CREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */ -#define DMAC_CREQ0_MASK (3 << DMAC_CREQ0_SHIFT) -#define DMAC_CREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */ -#define DMAC_CREQ1_MASK (3 << DMAC_CREQ1_SHIFT) -#define DMAC_CREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */ -#define DMAC_CREQ2_MASK (3 << DMAC_CREQ2_SHIFT) -#define DMAC_CREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */ -#define DMAC_CREQ3_MASK (3 << DMAC_CREQ3_SHIFT) +# define DMAC_CREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */ +# define DMAC_CREQ0_MASK (3 << DMAC_CREQ0_SHIFT) +# define DMAC_CREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */ +# define DMAC_CREQ1_MASK (3 << DMAC_CREQ1_SHIFT) +# define DMAC_CREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */ +# define DMAC_CREQ2_MASK (3 << DMAC_CREQ2_SHIFT) +# define DMAC_CREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */ +# define DMAC_CREQ3_MASK (3 << DMAC_CREQ3_SHIFT) #define DMAC_CREQ_SCREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source chunk transfer */ # define DMAC_CREQ_SCREQ(n) (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ_SHIFT(n))) @@ -212,14 +226,14 @@ #define DMAC_LAST_SHIFT(n) ((n)<<1) #define DMAC_LAST_MASK(n) (3 << DMAC_LAST_SHIFT(n)) -#define DMAC_LAST0_SHIFT (0) /* Bits 0-1: Channel 0 */ -#define DMAC_LAST0_MASK (3 << DMAC_LAST0_SHIFT) -#define DMAC_LAST1_SHIFT (2) /* Bits 2-3: Channel 1 */ -#define DMAC_LAST1_MASK (3 << DMAC_LAST1_SHIFT) -#define DMAC_LAST2_SHIFT (4) /* Bits 4-5: Channel 2 */ -#define DMAC_LAST2_MASK (3 << DMAC_LAST2_SHIFT) -#define DMAC_LAST3_SHIFT (6) /* Bits 6-7: Channel 3 */ -#define DMAC_LAST3_MASK (3 << DMAC_LAST3_SHIFT) +# define DMAC_LAST0_SHIFT (0) /* Bits 0-1: Channel 0 */ +# define DMAC_LAST0_MASK (3 << DMAC_LAST0_SHIFT) +# define DMAC_LAST1_SHIFT (2) /* Bits 2-3: Channel 1 */ +# define DMAC_LAST1_MASK (3 << DMAC_LAST1_SHIFT) +# define DMAC_LAST2_SHIFT (4) /* Bits 4-5: Channel 2 */ +# define DMAC_LAST2_MASK (3 << DMAC_LAST2_SHIFT) +# define DMAC_LAST3_SHIFT (6) /* Bits 6-7: Channel 3 */ +# define DMAC_LAST3_MASK (3 << DMAC_LAST3_SHIFT) #define DMAC_LAST_SLAST_SHIFT (0) /* Bits 0, 2, 4, 6: Indicates the last transfer */ # define DMAC_LAST_SLAST(n) (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST_SHIFT(n))) @@ -342,17 +356,26 @@ # define DMAC_CHSR_STAL3 (1 << (DMAC_CHSR_STAL_SHIFT+3)) /* DMA channel registers */ +/* DMAC Channel n [n = 0..3] Source Address Register -- 32-bit address*/ +/* DMAC Channel n [n = 0..3] Destination Address Register -- 32-bit address*/ +/* DMAC Channel n [n = 0..3] Descriptor Address Register -- 32-bit address*/ /* DMAC Channel n [n = 0..3] Control A Register */ #define DMACHAN_CTRLA_BTSIZE_MAX (0xfff) #define DMACHAN_CTRLA_BTSIZE_SHIFT (0) /* Bits 0-11: Buffer Transfer Size */ #define DMACHAN_CTRLA_BTSIZE_MASK (DMACHAN_CTRLA_BTSIZE_MAX << DMACHAN_CTRLA_BTSIZE_SHIFT) -#define DMACHAN_CTRLA_SCSIZE (1 << 16) /* Bit 16: Source Chunk Transfer Size */ -# define DMACHAN_CTRLA_SCSIZE_1 (0) -# define DMACHAN_CTRLA_SCSIZE_4 DMACHAN_CTRLA_SCSIZE -#define DMACHAN_CTRLA_DCSIZE (1 << 20) /* Bit 20: Destination Chunk Transfer size */ -# define DMACHAN_CTRLA_DCSIZE_1 (0) -# define DMACHAN_CTRLA_DCSIZE_4 DMACHAN_CTRLA_DCSIZE +# define DMACHAN_CTRLA_BTSIZE(n) ((uint32_t)(n) << DMACHAN_CTRLA_BTSIZE_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ + defined(CONFIG_ARCH_CHIP_SAM3A) +# define DMACHAN_CTRLA_SCSIZE (1 << 16) /* Bit 16: Source Chunk Transfer Size */ +# define DMACHAN_CTRLA_SCSIZE_1 (0) +# define DMACHAN_CTRLA_SCSIZE_4 DMACHAN_CTRLA_SCSIZE +# define DMACHAN_CTRLA_DCSIZE (1 << 20) /* Bit 20: Destination Chunk Transfer size */ +# define DMACHAN_CTRLA_DCSIZE_1 (0) +# define DMACHAN_CTRLA_DCSIZE_4 DMACHAN_CTRLA_DCSIZE +#endif + #define DMACHAN_CTRLA_SRCWIDTH_SHIFT (24) /* Bits 24-25 */ #define DMACHAN_CTRLA_SRCWIDTH_MASK (3 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) # define DMACHAN_CTRLA_SRCWIDTH_BYTE (0 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) @@ -378,10 +401,16 @@ #define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */ #define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT) # define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */ +# if defined(CONFIG_ARCH_CHIP_SAM4E) +# define DMACHAN_CTRLB_SRCINCR_DECR (1 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Decrementing address */ +# endif # define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */ #define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */ #define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT) # define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */ +# if defined(CONFIG_ARCH_CHIP_SAM4E) +# define DMACHAN_CTRLB_DSTINCR_DECR (1 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Decrementing address */ +# endif # define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */ #define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */ @@ -397,22 +426,59 @@ #define DMACHAN_CFG_LOCKIF (1 << 20) /* Bit 20: Enable lock interface capability */ #define DMACHAN_CFG_LOCKB (1 << 21) /* Bit 21: Enable AHB Bus Locking capability */ #define DMACHAN_CFG_LOCKIFL (1 << 22) /* Bit 22: Lock Master Interface Arbiter */ -#define DMACHAN_CFG_AHBPRO_SHIFT (24) /* Bits 24-26: Bus access privilege */ -#define DMACHAN_CFG_AHBPRO_MASK (7 << DMACHAN_CFG_AHBPRO_SHIFT) -# define DMACHAN_CFG_AHBPRO_PRIV (1 << DMACHAN_CFG_AHBPRO_SHIFT) -# define DMACHAN_CFG_AHBPRO_BUFF (2 << DMACHAN_CFG_AHBPRO_SHIFT) -# define DMACHAN_CFG_AHBPRO_CACHE (4 << DMACHAN_CFG_AHBPRO_SHIFT) +#define DMACHAN_CFG_AHBPROT_SHIFT (24) /* Bits 24-26: Bus access privilege */ +#define DMACHAN_CFG_AHBPROT_MASK (7 << DMACHAN_CFG_AHBPROT_SHIFT) +# define DMACHAN_CFG_AHBPROT_PRIV (1 << DMACHAN_CFG_AHBPROT_SHIFT) +# define DMACHAN_CFG_AHBPROT_BUFF (2 << DMACHAN_CFG_AHBPROT_SHIFT) +# define DMACHAN_CFG_AHBPROT_CACHE (4 << DMACHAN_CFG_AHBPROT_SHIFT) #define DMACHAN_CFG_FIFOCFG_SHIFT (28) /* Bits 28-29 */ #define DMACHAN_CFG_FIFOCFG_MASK (3 << DMACHAN_CFG_FIFOCFG_SHIFT) # define DMACHAN_CFG_FIFOCFG_LARGEST (0 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Largest length AHB burst */ # define DMACHAN_CFG_FIFOCFG_HALF (1 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Half FIFO size */ # define DMACHAN_CFG_FIFOCFG_SINGLE (2 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Single AHB access */ +/* More Global Registers */ + +/* DMAC Write Protect Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define DMAC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +# define DMAC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +# define DMAC_WPMR_WPKEY_MASK (0x00ffffff << DMAC_WPMR_WPKEY_SHIFT) +# define DMAC_WPMR_WPKEY (0x00444d41 << DMAC_WPMR_WPKEY_SHIFT) +#endif + +/* DMAC Write Protect Status Register DMAC_WPSR */ + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define DMAC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +# define DMAC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +# define DMAC_WPSR_WPVSRC_MASK (0xffff << DMAC_WPSR_WPVSRC_SHIFT) +#endif + /* DMA Peripheral IDs *******************************************************************/ -#define DMACHAN_PID_MCI0 0 -#define DMACHAN_PID_SSC 3 -#define DMACHAN_PID_MCI1 13 +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ + defined(CONFIG_ARCH_CHIP_SAM3A) +# define DMACHAN_PID_MCI0 0 +# define DMACHAN_PID_SSC 3 +# define DMACHAN_PID_MCI1 13 +#endif + +/* Hardware interface numbers */ + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define DMAC_INTF_HSMCI 0 /* HSMCI Transmit/Receive */ +# define DMAC_INTF_SPI0TX 1 /* SPI Transmit */ +# define DMAC_INTF_SPI0RX 2 /* SPI Receive */ +# define DMAC_INTF_USART0TX 3 /* USART0 Transmit */ +# define DMAC_INTF_USART0RX 4 /* USART0 Receive */ +# define DMAC_INTF_USART1TX 5 /* USART1 Transmit */ +# define DMAC_INTF_USART1RX 6 /* USART1 Receive */ +# define DMAC_INTF_AESTX 11 /* AES Transmit */ +# define DMAC_INTF_AESRX 12 /* AES Receive */ +# define DMAC_INTF_PWMTX 13 /* PWM Transmit */ +#endif /**************************************************************************************** * Public Types @@ -437,4 +503,4 @@ struct dma_linklist_s * Public Functions ****************************************************************************************/ -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_DMAC_H */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_DMAC_H */ diff --git a/arch/arm/src/sam34/chip/sam_tc.h b/arch/arm/src/sam34/chip/sam_tc.h index 779a5a2afb..db43e9a0fb 100644 --- a/arch/arm/src/sam34/chip/sam_tc.h +++ b/arch/arm/src/sam34/chip/sam_tc.h @@ -1,8 +1,8 @@ /************************************************************************************************ * arch/arm/src/sam34/chip/sam_tc.h - * Timer Counter (TC) definitions for the SAM3U and SAM4S + * Timer Counter (TC) definitions for the SAM3U, SAM4E, and SAM4S * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,167 +52,246 @@ /* TC register offsets **************************************************************************/ -/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */ +/* Timer channel offsets (with respect to timer base offset at 0x00, 0x40, and 0x80 */ -#define SAM_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */ -#define SAM_TCN_CCR_OFFSET 0x00 /* Channel Control Register */ -#define SAM_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */ +#define SAM_TC_CCR_OFFSET 0x0000 /* Channel Control Register */ +#define SAM_TC_CMR_OFFSET 0x0004 /* Channel Mode Register */ -#if defined(CONFIG_ARCH_CHIP_SAM4S) -#define SAM_TCN_SMMR_OFFSET 0x08 /* Stepper Motor Mode Register */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC_SMMR_OFFSET 0x0008 /* Stepper Motor Mode Register */ +#endif + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC_RAB_OFFSET 0x000c /* Register AB */ +#endif + /* 0x0c Reserved */ +#define SAM_TC_CV_OFFSET 0x0010 /* Counter Value */ +#define SAM_TC_RA_OFFSET 0x0014 /* Register A */ +#define SAM_TC_RB_OFFSET 0x0018 /* Register B */ +#define SAM_TC_RC_OFFSET 0x001c /* Register C */ +#define SAM_TC_SR_OFFSET 0x0020 /* Status Register */ +#define SAM_TC_IER_OFFSET 0x0024 /* Interrupt Enable Register */ +#define SAM_TC_IDR_OFFSET 0x0028 /* Interrupt Disable Register */ +#define SAM_TC_IMR_OFFSET 0x002c /* Interrupt Mask Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC_EMR_OFFSET 0x0030 /* Extended Mode Register */ #endif - /* 0x0c Reserved */ -#define SAM_TCN_CV_OFFSET 0x10 /* Counter Value */ -#define SAM_TCN_RA_OFFSET 0x14 /* Register A */ -#define SAM_TCN_RB_OFFSET 0x18 /* Register B */ -#define SAM_TCN_RC_OFFSET 0x1c /* Register C */ -#define SAM_TCN_SR_OFFSET 0x20 /* Status Register */ -#define SAM_TCN_IER_OFFSET 0x24 /* Interrupt Enable Register */ -#define SAM_TCN_IDR_OFFSET 0x28 /* Interrupt Disable Register */ -#define SAM_TCN_IMR_OFFSET 0x2c /* Interrupt Mask Register */ /* Timer common registers */ -#define SAM_TC_BCR_OFFSET 0xc0 /* Block Control Register */ -#define SAM_TC_BMR_OFFSET 0xc4 /* Block Mode Register */ -#define SAM_TC_QIER_OFFSET 0xc8 /* QDEC Interrupt Enable Register */ -#define SAM_TC_QIDR_OFFSET 0xcc /* QDEC Interrupt Disable Register */ -#define SAM_TC_QIMR_OFFSET 0xd0 /* QDEC Interrupt Mask Register */ -#define SAM_TC_QISR_OFFSET 0xd4 /* QDEC Interrupt Status Register */ +#define SAM_TC_BCR_OFFSET 0x00c0 /* Block Control Register */ +#define SAM_TC_BMR_OFFSET 0x00c4 /* Block Mode Register */ +#define SAM_TC_QIER_OFFSET 0x00c8 /* QDEC Interrupt Enable Register */ +#define SAM_TC_QIDR_OFFSET 0x00cc /* QDEC Interrupt Disable Register */ +#define SAM_TC_QIMR_OFFSET 0x00d0 /* QDEC Interrupt Mask Register */ +#define SAM_TC_QISR_OFFSET 0x00d4 /* QDEC Interrupt Status Register */ -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TCN_FMR_OFFSET 0xd8 /* Fault Mode Register */ -# define SAM_TCN_WPMR_OFFSET 0xe4 /* Write Protect Mode Register */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC_FMR_OFFSET 0xd8 /* Fault Mode Register */ +# define SAM_TC_WPMR_OFFSET 0xe4 /* Write Protect Mode Register */ #endif -/* TC register adresses *************************************************************************/ +/* TC register addresses ************************************************************************/ -/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */ - -#define SAM_TC_CCR(n) (SAM_TCN_BASE(n)+SAM_TCN_CCR_OFFSET) -#define SAM_TC_CMR(n) (SAM_TCN_BASE(n)+SAM_TCN_CMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TCN_SMMR(n) (SAM_TCN_BASE(n)+SAM_TCN_SMMR_OFFSET) +#define SAM_TC0_CCR (SAM_TC0_BASE+SAM_TC_CCR_OFFSET) +#define SAM_TC0_CMR (SAM_TC0_BASE+SAM_TC_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC0_SMMR (SAM_TC0_BASE+SAM_TC_SMMR_OFFSET) #endif -#define SAM_TC_CV(n) (SAM_TCN_BASE(n)+SAM_TCN_CV_OFFSET) -#define SAM_TC_RA(n) (SAM_TCN_BASE(n)+SAM_TCN_RA_OFFSET) -#define SAM_TC_RB(n) (SAM_TCN_BASE(n)+SAM_TCN_RB_OFFSET) -#define SAM_TC_RC(n) (SAM_TCN_BASE(n)+SAM_TCN_RC_OFFSET) -#define SAM_TC_SR(n) (SAM_TCN_BASE(n)+SAM_TCN_SR_OFFSET) -#define SAM_TC_IER(n) (SAM_TCN_BASE(n)+SAM_TCN_IER_OFFSET) -#define SAM_TC_IDR(n) (SAM_TCN_BASE(n)+SAM_TCN_IDR_OFFSET) -#define SAM_TC_IMR(n) (SAM_TCN_BASE(n)+SAM_TCN_IMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TCN_FMR(n) (SAM_TCN_BASE(n)+SAM_TCN_FMR_OFFSET) -# define SAM_TCN_WPMR(n) (SAM_TCN_BASE(n)+SAM_TCN_WPMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC0_RAB (SAM_TC0_BASE+SAM_TC_RAB_OFFSET) +#endif +#define SAM_TC0_CV (SAM_TC0_BASE+SAM_TC_CV_OFFSET) +#define SAM_TC0_RA (SAM_TC0_BASE+SAM_TC_RA_OFFSET) +#define SAM_TC0_RB (SAM_TC0_BASE+SAM_TC_RB_OFFSET) +#define SAM_TC0_RC (SAM_TC0_BASE+SAM_TC_RC_OFFSET) +#define SAM_TC0_SR (SAM_TC0_BASE+SAM_TC_SR_OFFSET) +#define SAM_TC0_IER (SAM_TC0_BASE+SAM_TC_IER_OFFSET) +#define SAM_TC0_IDR (SAM_TC0_BASE+SAM_TC_IDR_OFFSET) +#define SAM_TC0_IMR (SAM_TC0_BASE+SAM_TC_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC0_EMR (SAM_TC0_BASE+SAM_TC_EMR_OFFSET) #endif -#define SAM_TC0_CCR (SAM_TC0_BASE+SAM_TCN_CCR_OFFSET) -#define SAM_TC0_CMR (SAM_TC0_BASE+SAM_TCN_CMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TC0_SMMR (SAM_TC0_BASE+SAM_TCN_SMMR_OFFSET) +#define SAM_TC1_CCR (SAM_TC1_BASE+SAM_TC_CCR_OFFSET) +#define SAM_TC1_CMR (SAM_TC1_BASE+SAM_TC_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC1_SMMR (SAM_TC1_BASE+SAM_TC_SMMR_OFFSET) #endif -#define SAM_TC0_CV (SAM_TC0_BASE+SAM_TCN_CV_OFFSET) -#define SAM_TC0_RA (SAM_TC0_BASE+SAM_TCN_RA_OFFSET) -#define SAM_TC0_RB (SAM_TC0_BASE+SAM_TCN_RB_OFFSET) -#define SAM_TC0_RC (SAM_TC0_BASE+SAM_TCN_RC_OFFSET) -#define SAM_TC0_SR (SAM_TC0_BASE+SAM_TCN_SR_OFFSET) -#define SAM_TC0_IER (SAM_TC0_BASE+SAM_TCN_IER_OFFSET) -#define SAM_TC0_IDR (SAM_TC0_BASE+SAM_TCN_IDR_OFFSET) -#define SAM_TC0_IMR (SAM_TC0_BASE+SAM_TCN_IMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TC0_FMR (SAM_TC0_BASE+SAM_TCN_FMR_OFFSET) -# define SAM_TC0_WPMR (SAM_TC0_BASE+SAM_TCN_WPMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC1_RAB (SAM_TC1_BASE+SAM_TC_RAB_OFFSET) +#endif +#define SAM_TC1_CV (SAM_TC1_BASE+SAM_TC_CV_OFFSET) +#define SAM_TC1_RA (SAM_TC1_BASE+SAM_TC_RA_OFFSET) +#define SAM_TC1_RB (SAM_TC1_BASE+SAM_TC_RB_OFFSET) +#define SAM_TC1_RC (SAM_TC1_BASE+SAM_TC_RC_OFFSET) +#define SAM_TC1_SR (SAM_TC1_BASE+SAM_TC_SR_OFFSET) +#define SAM_TC1_IER (SAM_TC1_BASE+SAM_TC_IER_OFFSET) +#define SAM_TC1_IDR (SAM_TC1_BASE+SAM_TC_IDR_OFFSET) +#define SAM_TC1_IMR (SAM_TC1_BASE+SAM_TC_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC1_EMR (SAM_TC1_BASE+SAM_TC_EMR_OFFSET) +#endif +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC1_FMR (SAM_TC1_BASE+SAM_TC_FMR_OFFSET) +# define SAM_TC1_WPMR (SAM_TC1_BASE+SAM_TC_WPMR_OFFSET) #endif -#define SAM_TC1_CCR (SAM_TC1_BASE+SAM_TCN_CCR_OFFSET) -#define SAM_TC1_CMR (SAM_TC1_BASE+SAM_TCN_CMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TC1_SMMR (SAM_TC1_BASE+SAM_TCN_SMMR_OFFSET) +#define SAM_TC2_CCR (SAM_TC2_BASE+SAM_TC_CCR_OFFSET) +#define SAM_TC2_CMR (SAM_TC2_BASE+SAM_TC_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC2_SMMR (SAM_TC2_BASE+SAM_TC_SMMR_OFFSET) #endif -#define SAM_TC1_CV (SAM_TC1_BASE+SAM_TCN_CV_OFFSET) -#define SAM_TC1_RA (SAM_TC1_BASE+SAM_TCN_RA_OFFSET) -#define SAM_TC1_RB (SAM_TC1_BASE+SAM_TCN_RB_OFFSET) -#define SAM_TC1_RC (SAM_TC1_BASE+SAM_TCN_RC_OFFSET) -#define SAM_TC1_SR (SAM_TC1_BASE+SAM_TCN_SR_OFFSET) -#define SAM_TC1_IER (SAM_TC1_BASE+SAM_TCN_IER_OFFSET) -#define SAM_TC1_IDR (SAM_TC1_BASE+SAM_TCN_IDR_OFFSET) -#define SAM_TC1_IMR (SAM_TC1_BASE+SAM_TCN_IMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TC1_FMR (SAM_TC1_BASE+SAM_TCN_FMR_OFFSET) -# define SAM_TC1_WPMR (SAM_TC1_BASE+SAM_TCN_WPMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC2_RAB (SAM_TC2_BASE+SAM_TC_RAB_OFFSET) +#endif +#define SAM_TC2_CV (SAM_TC2_BASE+SAM_TC_CV_OFFSET) +#define SAM_TC2_RA (SAM_TC2_BASE+SAM_TC_RA_OFFSET) +#define SAM_TC2_RB (SAM_TC2_BASE+SAM_TC_RB_OFFSET) +#define SAM_TC2_RC (SAM_TC2_BASE+SAM_TC_RC_OFFSET) +#define SAM_TC2_SR (SAM_TC2_BASE+SAM_TC_SR_OFFSET) +#define SAM_TC2_IER (SAM_TC2_BASE+SAM_TC_IER_OFFSET) +#define SAM_TC2_IDR (SAM_TC2_BASE+SAM_TC_IDR_OFFSET) +#define SAM_TC2_IMR (SAM_TC2_BASE+SAM_TC_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC2_EMR (SAM_TC2_BASE+SAM_TC_EMR_OFFSET) +#endif +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC2_FMR (SAM_TC2_BASE+SAM_TC_FMR_OFFSET) +# define SAM_TC2_WPMR (SAM_TC2_BASE+SAM_TC_WPMR_OFFSET) #endif -#define SAM_TC2_CCR (SAM_TC2_BASE+SAM_TCN_CCR_OFFSET) -#define SAM_TC2_CMR (SAM_TC2_BASE+SAM_TCN_CMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TC2_SMMR (SAM_TC2_BASE+SAM_TCN_SMMR_OFFSET) +#define SAM_TC3_CCR (SAM_TC3_BASE+SAM_TC_CCR_OFFSET) +#define SAM_TC3_CMR (SAM_TC3_BASE+SAM_TC_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC3_SMMR (SAM_TC3_BASE+SAM_TC_SMMR_OFFSET) #endif -#define SAM_TC2_CV (SAM_TC2_BASE+SAM_TCN_CV_OFFSET) -#define SAM_TC2_RA (SAM_TC2_BASE+SAM_TCN_RA_OFFSET) -#define SAM_TC2_RB (SAM_TC2_BASE+SAM_TCN_RB_OFFSET) -#define SAM_TC2_RC (SAM_TC2_BASE+SAM_TCN_RC_OFFSET) -#define SAM_TC2_SR (SAM_TC2_BASE+SAM_TCN_SR_OFFSET) -#define SAM_TC2_IER (SAM_TC2_BASE+SAM_TCN_IER_OFFSET) -#define SAM_TC2_IDR (SAM_TC2_BASE+SAM_TCN_IDR_OFFSET) -#define SAM_TC2_IMR (SAM_TC2_BASE+SAM_TCN_IMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TC2_FMR (SAM_TC2_BASE+SAM_TCN_FMR_OFFSET) -# define SAM_TC2_WPMR (SAM_TC2_BASE+SAM_TCN_WPMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC3_RAB (SAM_TC3_BASE+SAM_TC_RAB_OFFSET) +#endif +#define SAM_TC3_CV (SAM_TC3_BASE+SAM_TC_CV_OFFSET) +#define SAM_TC3_RA (SAM_TC3_BASE+SAM_TC_RA_OFFSET) +#define SAM_TC3_RB (SAM_TC3_BASE+SAM_TC_RB_OFFSET) +#define SAM_TC3_RC (SAM_TC3_BASE+SAM_TC_RC_OFFSET) +#define SAM_TC3_SR (SAM_TC3_BASE+SAM_TC_SR_OFFSET) +#define SAM_TC3_IER (SAM_TC3_BASE+SAM_TC_IER_OFFSET) +#define SAM_TC3_IDR (SAM_TC3_BASE+SAM_TC_IDR_OFFSET) +#define SAM_TC3_IMR (SAM_TC3_BASE+SAM_TC_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC3_EMR (SAM_TC3_BASE+SAM_TC_EMR_OFFSET) +#endif +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC3_FMR (SAM_TC3_BASE+SAM_TC_FMR_OFFSET) +# define SAM_TC3_WPMR (SAM_TC3_BASE+SAM_TC_WPMR_OFFSET) #endif -#define SAM_TC3_CCR (SAM_TC3_BASE+SAM_TCN_CCR_OFFSET) -#define SAM_TC3_CMR (SAM_TC3_BASE+SAM_TCN_CMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TC3_SMMR (SAM_TC3_BASE+SAM_TCN_SMMR_OFFSET) +#define SAM_TC4_CCR (SAM_TC4_BASE+SAM_TC_CCR_OFFSET) +#define SAM_TC4_CMR (SAM_TC4_BASE+SAM_TC_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC4_SMMR (SAM_TC4_BASE+SAM_TC_SMMR_OFFSET) #endif -#define SAM_TC3_CV (SAM_TC3_BASE+SAM_TCN_CV_OFFSET) -#define SAM_TC3_RA (SAM_TC3_BASE+SAM_TCN_RA_OFFSET) -#define SAM_TC3_RB (SAM_TC3_BASE+SAM_TCN_RB_OFFSET) -#define SAM_TC3_RC (SAM_TC3_BASE+SAM_TCN_RC_OFFSET) -#define SAM_TC3_SR (SAM_TC3_BASE+SAM_TCN_SR_OFFSET) -#define SAM_TC3_IER (SAM_TC3_BASE+SAM_TCN_IER_OFFSET) -#define SAM_TC3_IDR (SAM_TC3_BASE+SAM_TCN_IDR_OFFSET) -#define SAM_TC3_IMR (SAM_TC3_BASE+SAM_TCN_IMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TC3_FMR (SAM_TC3_BASE+SAM_TCN_FMR_OFFSET) -# define SAM_TC3_WPMR (SAM_TC3_BASE+SAM_TCN_WPMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC4_RAB (SAM_TC4_BASE+SAM_TC_RAB_OFFSET) +#endif +#define SAM_TC4_CV (SAM_TC4_BASE+SAM_TC_CV_OFFSET) +#define SAM_TC4_RA (SAM_TC4_BASE+SAM_TC_RA_OFFSET) +#define SAM_TC4_RB (SAM_TC4_BASE+SAM_TC_RB_OFFSET) +#define SAM_TC4_RC (SAM_TC4_BASE+SAM_TC_RC_OFFSET) +#define SAM_TC4_SR (SAM_TC4_BASE+SAM_TC_SR_OFFSET) +#define SAM_TC4_IER (SAM_TC4_BASE+SAM_TC_IER_OFFSET) +#define SAM_TC4_IDR (SAM_TC4_BASE+SAM_TC_IDR_OFFSET) +#define SAM_TC4_IMR (SAM_TC4_BASE+SAM_TC_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC4_EMR (SAM_TC4_BASE+SAM_TC_EMR_OFFSET) +#endif +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC4_FMR (SAM_TC4_BASE+SAM_TC_FMR_OFFSET) +# define SAM_TC4_WPMR (SAM_TC4_BASE+SAM_TC_WPMR_OFFSET) #endif -#define SAM_TC4_CCR (SAM_TC4_BASE+SAM_TCN_CCR_OFFSET) -#define SAM_TC4_CMR (SAM_TC4_BASE+SAM_TCN_CMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TC4_SMMR (SAM_TC4_BASE+SAM_TCN_SMMR_OFFSET) +#define SAM_TC5_CCR (SAM_TC5_BASE+SAM_TC_CCR_OFFSET) +#define SAM_TC5_CMR (SAM_TC5_BASE+SAM_TC_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC5_SMMR (SAM_TC5_BASE+SAM_TC_SMMR_OFFSET) #endif -#define SAM_TC4_CV (SAM_TC4_BASE+SAM_TCN_CV_OFFSET) -#define SAM_TC4_RA (SAM_TC4_BASE+SAM_TCN_RA_OFFSET) -#define SAM_TC4_RB (SAM_TC4_BASE+SAM_TCN_RB_OFFSET) -#define SAM_TC4_RC (SAM_TC4_BASE+SAM_TCN_RC_OFFSET) -#define SAM_TC4_SR (SAM_TC4_BASE+SAM_TCN_SR_OFFSET) -#define SAM_TC4_IER (SAM_TC4_BASE+SAM_TCN_IER_OFFSET) -#define SAM_TC4_IDR (SAM_TC4_BASE+SAM_TCN_IDR_OFFSET) -#define SAM_TC4_IMR (SAM_TC4_BASE+SAM_TCN_IMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TC4_FMR (SAM_TC4_BASE+SAM_TCN_FMR_OFFSET) -# define SAM_TC4_WPMR (SAM_TC4_BASE+SAM_TCN_WPMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC5_RAB (SAM_TC5_BASE+SAM_TC_RAB_OFFSET) +#endif +#define SAM_TC5_CV (SAM_TC5_BASE+SAM_TC_CV_OFFSET) +#define SAM_TC5_RA (SAM_TC5_BASE+SAM_TC_RA_OFFSET) +#define SAM_TC5_RB (SAM_TC5_BASE+SAM_TC_RB_OFFSET) +#define SAM_TC5_RC (SAM_TC5_BASE+SAM_TC_RC_OFFSET) +#define SAM_TC5_SR (SAM_TC5_BASE+SAM_TC_SR_OFFSET) +#define SAM_TC5_IER (SAM_TC5_BASE+SAM_TC_IER_OFFSET) +#define SAM_TC5_IDR (SAM_TC5_BASE+SAM_TC_IDR_OFFSET) +#define SAM_TC5_IMR (SAM_TC5_BASE+SAM_TC_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC5_EMR (SAM_TC5_BASE+SAM_TC_EMR_OFFSET) +#endif +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC5_FMR (SAM_TC5_BASE+SAM_TC_FMR_OFFSET) +# define SAM_TC5_WPMR (SAM_TC5_BASE+SAM_TC_WPMR_OFFSET) #endif -#define SAM_TC5_CCR (SAM_TC5_BASE+SAM_TCN_CCR_OFFSET) -#define SAM_TC5_CMR (SAM_TC5_BASE+SAM_TCN_CMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TC5_SMMR (SAM_TC5_BASE+SAM_TCN_SMMR_OFFSET) +#define SAM_TC6_CCR (SAM_TC6_BASE+SAM_TC_CCR_OFFSET) +#define SAM_TC6_CMR (SAM_TC6_BASE+SAM_TC_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC6_SMMR (SAM_TC6_BASE+SAM_TC_SMMR_OFFSET) #endif -#define SAM_TC5_CV (SAM_TC5_BASE+SAM_TCN_CV_OFFSET) -#define SAM_TC5_RA (SAM_TC5_BASE+SAM_TCN_RA_OFFSET) -#define SAM_TC5_RB (SAM_TC5_BASE+SAM_TCN_RB_OFFSET) -#define SAM_TC5_RC (SAM_TC5_BASE+SAM_TCN_RC_OFFSET) -#define SAM_TC5_SR (SAM_TC5_BASE+SAM_TCN_SR_OFFSET) -#define SAM_TC5_IER (SAM_TC5_BASE+SAM_TCN_IER_OFFSET) -#define SAM_TC5_IDR (SAM_TC5_BASE+SAM_TCN_IDR_OFFSET) -#define SAM_TC5_IMR (SAM_TC5_BASE+SAM_TCN_IMR_OFFSET) -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# define SAM_TC5_FMR (SAM_TC5_BASE+SAM_TCN_FMR_OFFSET) -# define SAM_TC5_WPMR (SAM_TC5_BASE+SAM_TCN_WPMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC6_RAB (SAM_TC6_BASE+SAM_TC_RAB_OFFSET) +#endif +#define SAM_TC6_CV (SAM_TC6_BASE+SAM_TC_CV_OFFSET) +#define SAM_TC6_RA (SAM_TC6_BASE+SAM_TC_RA_OFFSET) +#define SAM_TC6_RB (SAM_TC6_BASE+SAM_TC_RB_OFFSET) +#define SAM_TC6_RC (SAM_TC6_BASE+SAM_TC_RC_OFFSET) +#define SAM_TC6_SR (SAM_TC6_BASE+SAM_TC_SR_OFFSET) +#define SAM_TC6_IER (SAM_TC6_BASE+SAM_TC_IER_OFFSET) +#define SAM_TC6_IDR (SAM_TC6_BASE+SAM_TC_IDR_OFFSET) +#define SAM_TC6_IMR (SAM_TC6_BASE+SAM_TC_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC6_EMR (SAM_TC6_BASE+SAM_TC_EMR_OFFSET) +#endif + +#define SAM_TC7_CCR (SAM_TC7_BASE+SAM_TC_CCR_OFFSET) +#define SAM_TC7_CMR (SAM_TC7_BASE+SAM_TC_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC7_SMMR (SAM_TC7_BASE+SAM_TC_SMMR_OFFSET) +#endif +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC7_RAB (SAM_TC7_BASE+SAM_TC_RAB_OFFSET) +#endif +#define SAM_TC7_CV (SAM_TC7_BASE+SAM_TC_CV_OFFSET) +#define SAM_TC7_RA (SAM_TC7_BASE+SAM_TC_RA_OFFSET) +#define SAM_TC7_RB (SAM_TC7_BASE+SAM_TC_RB_OFFSET) +#define SAM_TC7_RC (SAM_TC7_BASE+SAM_TC_RC_OFFSET) +#define SAM_TC7_SR (SAM_TC7_BASE+SAM_TC_SR_OFFSET) +#define SAM_TC7_IER (SAM_TC7_BASE+SAM_TC_IER_OFFSET) +#define SAM_TC7_IDR (SAM_TC7_BASE+SAM_TC_IDR_OFFSET) +#define SAM_TC7_IMR (SAM_TC7_BASE+SAM_TC_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC7_EMR (SAM_TC7_BASE+SAM_TC_EMR_OFFSET) +#endif + +#define SAM_TC8_CCR (SAM_TC8_BASE+SAM_TC_CCR_OFFSET) +#define SAM_TC8_CMR (SAM_TC8_BASE+SAM_TC_CMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC8_SMMR (SAM_TC8_BASE+SAM_TC_SMMR_OFFSET) +#endif +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC8_RAB (SAM_TC8_BASE+SAM_TC_RAB_OFFSET) +#endif +#define SAM_TC8_CV (SAM_TC8_BASE+SAM_TC_CV_OFFSET) +#define SAM_TC8_RA (SAM_TC8_BASE+SAM_TC_RA_OFFSET) +#define SAM_TC8_RB (SAM_TC8_BASE+SAM_TC_RB_OFFSET) +#define SAM_TC8_RC (SAM_TC8_BASE+SAM_TC_RC_OFFSET) +#define SAM_TC8_SR (SAM_TC8_BASE+SAM_TC_SR_OFFSET) +#define SAM_TC8_IER (SAM_TC8_BASE+SAM_TC_IER_OFFSET) +#define SAM_TC8_IDR (SAM_TC8_BASE+SAM_TC_IDR_OFFSET) +#define SAM_TC8_IMR (SAM_TC8_BASE+SAM_TC_IMR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC8_EMR (SAM_TC8_BASE+SAM_TC_EMR_OFFSET) #endif /* Timer common registers */ @@ -224,9 +303,212 @@ #define SAM_TC_QIMR (SAM_TC_BASE+SAM_TC_QIMR_OFFSET) #define SAM_TC_QISR (SAM_TC_BASE+SAM_TC_QISR_OFFSET) -/* TC register bit definitions ******************************************************************/ +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TC_FMR (SAM_TC_BASE+SAM_TC_FMR_OFFSET) +# define SAM_TC_WPMR (SAM_TC_BASE+SAM_TC_WPMR_OFFSET) +#endif -/* Timer common registers */ +/* TC register bit definitions ******************************************************************/ +/* Timer channel registers **********************************************************************/ + +/* TC Channel Control Register */ + +#define TC_CCR_CLKEN (1 << 0) /* Bit 0: Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (1 << 1) /* Bit 1: Counter Clock Disable Command */ +#define TC_CCR_SWTRG (1 << 2) /* Bit 2: Software Trigger Command */ + +/* TC Channel Mode Register -- Common */ + +#define TC_CMR_TCCLKS_SHIFT (0) /* Bits 0-2: Clock Selection */ +#define TC_CMR_TCCLKS_MASK (7 << TC_CMR_TCCLKS_SHIFT) +# define TC_CMR_TCCLKS_TIMERCLOCK1 (0 << TC_CMR_TCCLKS_SHIFT) +# define TC_CMR_TCCLKS_TIMERCLOCK2 (1 << TC_CMR_TCCLKS_SHIFT) +# define TC_CMR_TCCLKS_TIMERCLOCK3 (2 << TC_CMR_TCCLKS_SHIFT) +# define TC_CMR_TCCLKS_TIMERCLOCK4 (3 << TC_CMR_TCCLKS_SHIFT) +# define TC_CMR_TCCLKS_TIMERCLOCK5 (4 << TC_CMR_TCCLKS_SHIFT) +# define TC_CMR_TCCLKS_XC0 (5 << TC_CMR_TCCLKS_SHIFT) +# define TC_CMR_TCCLKS_XC1 (6 << TC_CMR_TCCLKS_SHIFT) +# define TC_CMR_TCCLKS_XC2 (7 << TC_CMR_TCCLKS_SHIFT) +#define TC_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert */ +#define TC_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection */ +#define TC_CMR_BURST_MASK (3 << TC_CMR_BURST_MASK) +# define TC_CMR_BURST_NOTGATED (0 << TC_CMR_BURST_MASK) /* Nott gated by external signal */ +# define TC_CMR_BURST_XC0 (1 << TC_CMR_BURST_MASK) /* XC0 ANDed with selected clock */ +# define TC_CMR_BURST_XC1 (2 << TC_CMR_BURST_MASK) /* XC1 ANDed with selected clock */ +# define TC_CMR_BURST_XC2 (3 << TC_CMR_BURST_MASK) /* XC2 ANDed with selected clock */ +#define TC_CMR_WAVE (1 << 15) /* Bit 15: Waveform Mode */ + +/* TC Channel Mode Register -- Capture mode only */ + +#define TC_CMR_LDBSTOP (1 << 6) /* Bit 6: Counter stopped with RB Loading */ +#define TC_CMR_LDBDIS (1 << 7) /* Bit 7: Counter disable with RB Loading */ +#define TC_CMR_ETRGEDG_SHIFT (8) /* Bits 8-9: External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG_MASK (3 << TC_CMR_ETRGEDG_SHIFT) +# define TC_CMR_ETRGEDG_NONE (0 << TC_CMR_ETRGEDG_SHIFT) /* None */ +# define TC_CMR_ETRGEDG_REDGE (1 << TC_CMR_ETRGEDG_SHIFT) /* Rising edge */ +# define TC_CMR_ETRGEDG_FEDGE (2 << TC_CMR_ETRGEDG_SHIFT) /* Falling edge */ +# define TC_CMR_ETRGEDG_EACH (3 << TC_CMR_ETRGEDG_SHIFT) /* Each */ +#define TC_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable */ +#define TC_CMR_LDRA_SHIFT (16) /* Bits 16-17: RA Loading Selection */ +#define TC_CMR_LDRA_MASK (3 << TC_CMR_LDRA_SHIFT) +# define TC_CMR_LDRA_NONE (0 << TC_CMR_LDRA_SHIFT) /* None */ +# define TC_CMR_LDRA_REDGE (1 << TC_CMR_LDRA_SHIFT) /* Rising edge of TIOA */ +# define TC_CMR_LDRA_FEDGE (2 << TC_CMR_LDRA_SHIFT) /* Falling edge of TIOA */ +# define TC_CMR_LDRA_EACH (3 << TC_CMR_LDRA_SHIFT) /* Each edge of TIOA */ +#define TC_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Selection */ +#define TC_CMR_LDRB_MASK (3 << TC_CMR_LDRB_SHIFT) +# define TC_CMR_LDRB_NONE (0 << TC_CMR_LDRB_SHIFT) /* None */ +# define TC_CMR_LDRB_REDGE (1 << TC_CMR_LDRB_SHIFT) /* Rising edge of TIOB */ +# define TC_CMR_LDRB_FEDGE (2 << TC_CMR_LDRB_SHIFT) /* Falling edge of TIOB */ +# define TC_CMR_LDRB_EACH (3 << TC_CMR_LDRB_SHIFT) /* Each edge of TIOB */ + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +#define TC_CMR_SBSMPLR_SHIFT (20) /* Bits 20-22: Loading Edge Subsampling Ratio */ +#define TC_CMR_SBSMPLR_MASK (7 << TC_CMR_SBSMPLR_SHIFT) +# define TC_CMR_SBSMPLR_ ONE (0 << TC_CMR_SBSMPLR_SHIFT) /* Load on each selected edge */ +# define TC_CMR_SBSMPLR_ HALF (1 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 2 selected edges */ +# define TC_CMR_SBSMPLR_ 4TH (2 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 4 selected edges */ +# define TC_CMR_SBSMPLR_ 8TH (3 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 8 selected edges */ +# define TC_CMR_SBSMPLR_ 16TH (4 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 16 selected edges */ +#endif + +/* TC Channel Mode Register -- Waveform mode only */ + +#define TC_CMR_CPCSTOP (1 << 6) /* Bit 6: Counter Clock Stopped with RC Compare (Waveform mode) */ +#define TC_CMR_CPCDIS (1 << 7) /* Bit 7: Counter Clock Disable with RC Compare (Waveform mode) */ +#define TC_CMR_EEVTEDG_SHIFT (8) /* Bits 8-9: External Event Edge Selection (Waveform mode) */ +#define TC_CMR_EEVTEDG_MASK (3 << TC_CMR_EEVTEDG_SHIFT) +# define TC_CMR_EEVTEDG_NONE (0 << TC_CMR_EEVTEDG_SHIFT) /* None */ +# define TC_CMR_EEVTEDG_REDGE (1 << TC_CMR_EEVTEDG_SHIFT) /* Rising edge */ +# define TC_CMR_EEVTEDG_FEDGE (2 << TC_CMR_EEVTEDG_SHIFT) /* Falling edge */ +# define TC_CMR_EEVTEDG_EACH (3 << TC_CMR_EEVTEDG_SHIFT) /* Each edge */ +#define TC_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection (Waveform mode) */ +#define TC_CMR_EEVT_MASK (3 << TC_CMR_EEVT_SHIFT) +# define TC_CMR_EEVT_TIOB (0 << TC_CMR_EEVT_SHIFT) /* TIOB input */ +# define TC_CMR_EEVT_XC0 (1 << TC_CMR_EEVT_SHIFT) /* XC0 output */ +# define TC_CMR_EEVT_XC1 (2 << TC_CMR_EEVT_SHIFT) /* XC1 output */ +# define TC_CMR_EEVT_XC2 (3 << TC_CMR_EEVT_SHIFT) /* XC2 output */ +#define TC_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable (Waveform mode) */ +#define TC_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection (Waveform mode) */ +#define TC_CMR_WAVSEL_MASK (3 << TC_CMR_WAVSEL_SHIFT) +# define TC_CMR_WAVSEL_UP (0 << TC_CMR_WAVSEL_SHIFT) /* UP mode w/o auto trigger (Waveform mode) */ +# define TC_CMR_WAVSEL_UPAUTO (1 << TC_CMR_WAVSEL_SHIFT) /* UP mode with auto trigger (Waveform mode) */ +# define TC_CMR_WAVSEL_UPDWN (2 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o auto trigger (Waveform mode) */ +# define TC_CMR_WAVSEL_UPDWNAUTO (3 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode with auto trigger (Waveform mode) */ +#define TC_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA (Waveform mode) */ +#define TC_CMR_ACPA_MASK (3 << TC_CMR_ACPA_SHIFT) +# define TC_CMR_ACPA_NONE (0 << TC_CMR_ACPA_SHIFT) +# define TC_CMR_ACPA_SET (1 << TC_CMR_ACPA_SHIFT) +# define TC_CMR_ACPA_CLEAR (2 << TC_CMR_ACPA_SHIFT) +# define TC_CMR_ACPA_TOGGLE (3 << TC_CMR_ACPA_SHIFT) +#define TC_CMR_ACPC_SHIFT (18) /* Bits 18-19: RC Compare Effect on TIOA (Waveform mode) */ +#define TC_CMR_ACPC_MASK (3 << TC_CMR_ACPC_SHIFT) +# define TC_CMR_ACPC_NONE (0 << TC_CMR_ACPC_SHIFT) +# define TC_CMR_ACPC_SET (1 << TC_CMR_ACPC_SHIFT) +# define TC_CMR_ACPC_CLEAR (2 << TC_CMR_ACPC_SHIFT) +# define TC_CMR_ACPC_TOGGLE (3 << TC_CMR_ACPC_SHIFT) +#define TC_CMR_AEEVT_SHIFT (20) /* Bits 20-21: External Event Effect on TIOA (Waveform mode) */ +#define TC_CMR_AEEVT_MASK (3 << TC_CMR_AEEVT_SHIFT) +# define TC_CMR_AEEVT_NONE (0 << TC_CMR_AEEVT_SHIFT) +# define TC_CMR_AEEVT_SET (1 << TC_CMR_AEEVT_SHIFT) +# define TC_CMR_AEEVT_CLEAR (2 << TC_CMR_AEEVT_SHIFT) +# define TC_CMR_AEEVT_TOGGLE (3 << TC_CMR_AEEVT_SHIFT) +#define TC_CMR_ASWTRG_SHIFT (22) /* Bits 22-23: Software Trigger Effect on TIOA (Waveform mode) */ +#define TC_CMR_ASWTRG_MASK (3 << TC_CMR_ASWTRG_SHIFT) +# define TC_CMR_ASWTRG_NONE (0 << TC_CMR_ASWTRG_SHIFT) +# define TC_CMR_ASWTRG_SET (1 << TC_CMR_ASWTRG_SHIFT) +# define TC_CMR_ASWTRG_CLEAR (2 << TC_CMR_ASWTRG_SHIFT) +# define TC_CMR_ASWTRG_TOGGLE (3 << TC_CMR_ASWTRG_SHIFT) +#define TC_CMR_BCPB_SHIFT (24) /* Bits 24-25: RB Compare Effect on TIOB (Waveform mode) */ +#define TC_CMR_BCPB_MASK (3 << TC_CMR_BCPB_SHIFT) +# define TC_CMR_BCPB_NONE (0 << TC_CMR_BCPB_SHIFT) +# define TC_CMR_BCPB_SET (1 << TC_CMR_BCPB_SHIFT) +# define TC_CMR_BCPB_CLEAR (2 << TC_CMR_BCPB_SHIFT) +# define TC_CMR_BCPB_TOGGLE (3 << TC_CMR_BCPB_SHIFT) +#define TC_CMR_BCPC_SHIFT (26) /* Bits 26-27: RC Compare Effect on TIOB (Waveform mode) */ +#define TC_CMR_BCPC_MASK (3 << TC_CMR_BCPC_SHIFT) +# define TC_CMR_BCPC_NONE (0 << TC_CMR_BCPC_SHIFT) +# define TC_CMR_BCPC_SET (1 << TC_CMR_BCPC_SHIFT) +# define TC_CMR_BCPC_CLEAR (2 << TC_CMR_BCPC_SHIFT) +# define TC_CMR_BCPC_TOGGLE (3 << TC_CMR_BCPC_SHIFT) +#define TC_CMR_BEEVT_SHIFT (28) /* Bits 28-29: External Event Effect on TIOB (Waveform mode) */ +#define TC_CMR_BEEVT_MASK (3 << TC_CMR_BEEVT_SHIFT) +# define TC_CMR_BEEVT_NONE (0 << TC_CMR_BEEVT_SHIFT) +# define TC_CMR_BEEVT_SET (1 << TC_CMR_BEEVT_SHIFT) +# define TC_CMR_BEEVT_CLEAR (2 << TC_CMR_BEEVT_SHIFT) +# define TC_CMR_BEEVT_TOGGLE (3 << TC_CMR_BEEVT_SHIFT) +#define TC_CMR_BSWTRG_SHIFT (30) /* Bits 30-31: Software Trigger Effect on TIOB (Waveform mode) */ +#define TC_CMR_BSWTRG_MASK (3 << TC_CMR_BSWTRG_SHIFT) +# define TC_CMR_BSWTRG_NONE (0 << TC_CMR_BSWTRG_SHIFT) +# define TC_CMR_BSWTRG_SET (1 << TC_CMR_BSWTRG_SHIFT) +# define TC_CMR_BSWTRG_CLEAR (2 << TC_CMR_BSWTRG_SHIFT) +# define TC_CMR_BSWTRG_TOGGLE (3 << TC_CMR_BSWTRG_SHIFT) + +/* Stepper Motor Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define TC_SMMR_GCEN (1 << 0) /* Bit 0: Gray Count Enable */ +# define TC_SMMR_DOWN (1 << 1) /* Bit 1: DOWN Count */ +#endif + +/* Register AB -- 32-bit value */ + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define TC_RAB_MASK (0xffffffff) +#endif + +/* TC Counter Value Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define TC_CV_MASK (0xffffffff) +#else +# define TC_CV_MASK (0x0000ffff) +#endif + +/* TC Register A, B, C */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define TC_RVALUE_MASK (0xffffffff) +#else +# define TC_RVALUE_MASK (0x0000ffff) +#endif + +/* TC Status Register, TC Interrupt Enable Register, TC Interrupt Disable Register, and TC Interrupt Mask Register common bit-field definitions */ + +#define TC_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow */ +#define TC_INT_LOVRS (1 << 1) /* Bit 1: Load Overrun */ +#define TC_INT_CPAS (1 << 2) /* Bit 2: RA Compare */ +#define TC_INT_CPBS (1 << 3) /* Bit 3: RB Compare */ +#define TC_INT_CPCS (1 << 4) /* Bit 4: RC Compare */ +#define TC_INT_LDRAS (1 << 5) /* Bit 5: RA Loading */ +#define TC_INT_LDRBS (1 << 6) /* Bit 6: RB Loading */ +#define TC_INT_ETRGS (1 << 7) /* Bit 7: External Trigger */ + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define TC_INT_ENDRX (1 << 8) /* Bit 8: End of Receiver Transfer */ +# define TC_INT_RXBUFF (1 << 9) /* Bit 9: Reception Buffer Full */ +#endif + +#define TC_INT_CLKSTA (1 << 16) /* Bit 16: Clock Enabling (SR only) */ +#define TC_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror (SR only) */ +#define TC_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror (SR only)*/ + +/* Extended Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define TC_EMR_TRIGSRCA_SHIFT (0) /* Bits 0-1: Trigger source for input A */ +# define TC_EMR_TRIGSRCA_MASK (3 << TC_EMR_TRIGSRCA_SHIFT) +# define TC_EMR_TRIGSRCA_TIOA (0 << TC_EMR_TRIGSRCA_SHIFT) /* Input A driven by pin TIOAx */ +# define TC_EMR_TRIGSRCA_PWM (1 << TC_EMR_TRIGSRCA_SHIFT) /* Input A driven by PWMx */ +# define TC_EMR_TRIGSRCB_SHIFT (5) /* Bits 4-5: Trigger source for input B */ +# define TC_EMR_TRIGSRCB_MASK (3 << TC_EMR_TRIGSRCB_SHIFT) +# define TC_EMR_TRIGSRCB_TIOA (0 << TC_EMR_TRIGSRCB_SHIFT) /* Input B driven by pin TIOBx */ +# define TC_EMR_TRIGSRCB_PWM (1 << TC_EMR_TRIGSRCB_SHIFT) /* Input B driven by PWMx */ +# define TC_EMR_NODIVCLK (1 << 8) /* Bit 8: NO DIVided CLocK */ +#endif + +/* Timer common registers ***********************************************************************/ /* TC Block Control Register */ #define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command @@ -247,10 +529,16 @@ # define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT) #define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */ #define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT) +#if defined(CONFIG_ARCH_CHIP_SAM4s) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_TIOA1 (2 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_TIOA2 (3 << TC_BMR_TC2XC2S_SHIFT) +#else # define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT) # define TC_BMR_TC2XC2S_NONE (1 << TC_BMR_TC2XC2S_SHIFT) # define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT) # define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT) +#endif #define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder Enabled */ #define TC_BMR_POSEN (1 << 9) /* Bit 9: Position Enabled */ #define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: Speed Enabled */ @@ -258,12 +546,13 @@ #define TC_BMR_EDGPHA (1 << 12) /* Bit 12: Edge on PHA count mode */ #define TC_BMR_INVA (1 << 13) /* Bit 13: Inverted PHA */ #define TC_BMR_INVB (1 << 14) /* Bit 14: Inverted PHB */ -#define TC_BMR_SWAP (1 << 15) /* Bit 15: Swap PHA and PHB */ -#define TC_BMR_INVIDX (1 << 16) /* Bit 16: Inverted Index */ +#define TC_BMR_INVIDX (1 << 15) /* Bit 15: Inverted Index */ +#define TC_BMR_SWAP (1 << 16) /* Bit 16: Swap PHA and PHB */ #define TC_BMR_IDXPHB (1 << 17) /* Bit 17: Index pin is PHB pin */ #define TC_BMR_FILTER (1 << 19) /* Bit 19 */ #define TC_BMR_MAXFILT_SHIFT (20) /* Bits 20-25: Maximum Filter */ #define TC_BMR_MAXFILT_MASK (63 << TC_BMR_MAXFILT_SHIFT) +# define TC_BMR_MAXFILT(n) ((uint32_t)(n) << TC_BMR_MAXFILT_SHIFT) /* TC QDEC Interrupt Enable Register, TC QDEC Interrupt Disable Register, * TC QDEC Interrupt Mask Register, TC QDEC Interrupt Status Register common @@ -275,168 +564,20 @@ #define TC_QINT_QERR (1 << 2) /* Bit 2: Quadrature Error (Common) */ #define TC_QISR_DIR (1 << 8) /* Bit 8: Direction (QISR only) */ -/* Timer Channel Registers */ -/* TC Channel Control Register */ - -#define TCN_CCR_CLKEN (1 << 0) /* Bit 0: Counter Clock Enable Command */ -#define TCN_CCR_CLKDIS (1 << 1) /* Bit 1: Counter Clock Disable Command */ -#define TCN_CCR_SWTRG (1 << 2) /* Bit 2: Software Trigger Command */ - -/* TC Channel Mode Register */ - -#define TCN_CMR_TCCLKS_SHIFT (0) /* Bits 0-2: Clock Selection (Common) */ -#define TCN_CMR_TCCLKS_MASK (7 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_TIMERCLOCK1 (0 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_TIMERCLOCK2 (1 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_TIMERCLOCK3 (2 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_TIMERCLOCK4 (3 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_TIMERCLOCK5 (4 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_XC0 (5 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_XC1 (6 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_XC2 (7 << TCN_CMR_TCCLKS_SHIFT) -#define TCN_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert (Common) */ -#define TCN_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection (Common) */ -#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK) -#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK) -# define TCN_CMR_BURST_NOTGATED (0 << TCN_CMR_BURST_MASK) /* Nott gated by external signal */ -# define TCN_CMR_BURST_XC0 (1 << TCN_CMR_BURST_MASK) /* XC0 ANDed with selected clock */ -# define TCN_CMR_BURST_XC1 (2 << TCN_CMR_BURST_MASK) /* XC1 ANDed with selected clock */ -# define TCN_CMR_BURST_XC2 (3 << TCN_CMR_BURST_MASK) /* XC2 ANDed with selected clock */ -#define TCN_CMR_WAVE (1 << 15) /* Bit 15: (Common) */ - -#define TCN_CMR_LDBSTOP (1 << 6) /* Bit 6: Counter stopped with RB Loading (Capture mode) */ -#define TCN_CMR_LDBDIS (1 << 7) /* Bit 7: Counter disable with RB Loading (Capture mode) */ -#define TCN_CMR_ETRGEDG_SHIFT (8) /* Bits 8-9: External Trigger Edge Selection (Capture mode) */ -#define TCN_CMR_ETRGEDG_MASK (3 << TCN_CMR_ETRGEDG_SHIFT) -# define TCN_CMR_ETRGEDG_NONE (0 << TCN_CMR_ETRGEDG_SHIFT) /* None */ -# define TCN_CMR_ETRGEDG_REDGE (1 << TCN_CMR_ETRGEDG_SHIFT) /* Rising edge */ -# define TCN_CMR_ETRGEDG_FEDGE (2 << TCN_CMR_ETRGEDG_SHIFT) /* Falling edge */ -# define TCN_CMR_ETRGEDG_EACH (3 << TCN_CMR_ETRGEDG_SHIFT) /* Each */ -#define TCN_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection (Capture mode) */ -#define TCN_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable (Capture mode) */ -#define TCN_CMR_LDRA_SHIFT (16) /* Bits 16-17: RA Loading Selection (Capture mode) */ -#define TCN_CMR_LDRA_MASK (3 << TCN_CMR_LDRA_SHIFT) -# define TCN_CMR_LDRA_NONE (0 << TCN_CMR_LDRA_SHIFT) /* None */ -# define TCN_CMR_LDRA_REDGE (1 << TCN_CMR_LDRA_SHIFT) /* Rising edge of TIOA */ -# define TCN_CMR_LDRA_FEDGE (2 << TCN_CMR_LDRA_SHIFT) /* Falling edge of TIOA */ -# define TCN_CMR_LDRA_EACH (3 << TCN_CMR_LDRA_SHIFT) /* Each edge of TIOA */ -#define TCN_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Selection (Capture mode) */ -#define TCN_CMR_LDRB_MASK (3 << TCN_CMR_LDRB_SHIFT) -# define TCN_CMR_LDRB_NONE (0 << TCN_CMR_LDRB_SHIFT) /* None */ -# define TCN_CMR_LDRB_REDGE (1 << TCN_CMR_LDRB_SHIFT) /* Rising edge of TIOB */ -# define TCN_CMR_LDRB_FEDGE (2 << TCN_CMR_LDRB_SHIFT) /* Falling edge of TIOB */ -# define TCN_CMR_LDRB_EACH (3 << TCN_CMR_LDRB_SHIFT) /* Each edge of TIOB */ - -#define TCN_CMR_CPCSTOP (1 << 6) /* Bit 6: Counter Clock Stopped with RC Compare (Waveform mode) */ -#define TCN_CMR_CPCDIS (1 << 7) /* Bit 7: Counter Clock Disable with RC Compare (Waveform mode) */ -#define TCN_CMR_EEVTEDG_SHIFT (8) /* Bits 8-9: External Event Edge Selection (Waveform mode) */ -#define TCN_CMR_EEVTEDG_MASK (3 << TCN_CMR_EEVTEDG_SHIFT) -# define TCN_CMR_EEVTEDG_NONE (0 << TCN_CMR_EEVTEDG_SHIFT) /* None */ -# define TCN_CMR_EEVTEDG_REDGE (1 << TCN_CMR_EEVTEDG_SHIFT) /* Rising edge */ -# define TCN_CMR_EEVTEDG_FEDGE (2 << TCN_CMR_EEVTEDG_SHIFT) /* Falling edge */ -# define TCN_CMR_EEVTEDG_EACH (3 << TCN_CMR_EEVTEDG_SHIFT) /* Each edge */ -#define TCN_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection (Waveform mode) */ -#define TCN_CMR_EEVT_MASK (3 << TCN_CMR_EEVT_SHIFT) -# define TCN_CMR_EEVT_TIOB (0 << TCN_CMR_EEVT_SHIFT) /* TIOB input */ -# define TCN_CMR_EEVT_XC0 (1 << TCN_CMR_EEVT_SHIFT) /* XC0 output */ -# define TCN_CMR_EEVT_XC1 (2 << TCN_CMR_EEVT_SHIFT) /* XC1 output */ -# define TCN_CMR_EEVT_XC2 (3 << TCN_CMR_EEVT_SHIFT) /* XC2 output */ -#define TCN_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable (Waveform mode) */ -#define TCN_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection (Waveform mode) */ -#define TCN_CMR_WAVSEL_MASK (3 << TCN_CMR_WAVSEL_SHIFT) -# define TCN_CMR_WAVSEL_UP (0 << TCN_CMR_WAVSEL_SHIFT) /* UP mode w/o auto trigger (Waveform mode) */ -# define TCN_CMR_WAVSEL_UPAUTO (1 << TCN_CMR_WAVSEL_SHIFT) /* UP mode with auto trigger (Waveform mode) */ -# define TCN_CMR_WAVSEL_UPDWN (2 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o auto trigger (Waveform mode) */ -# define TCN_CMR_WAVSEL_UPDWNAUTO (3 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode with auto trigger (Waveform mode) */ -#define TCN_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA (Waveform mode) */ -#define TCN_CMR_ACPA_MASK (3 << TCN_CMR_ACPA_SHIFT) -# define TCN_CMR_ACPA_NONE (0 << TCN_CMR_ACPA_SHIFT) -# define TCN_CMR_ACPA_SET (1 << TCN_CMR_ACPA_SHIFT) -# define TCN_CMR_ACPA_CLEAR (2 << TCN_CMR_ACPA_SHIFT) -# define TCN_CMR_ACPA_TOGGLE (3 << TCN_CMR_ACPA_SHIFT) -#define TCN_CMR_ACPC_SHIFT (18) /* Bits 18-19: RC Compare Effect on TIOA (Waveform mode) */ -#define TCN_CMR_ACPC_MASK (3 << TCN_CMR_ACPC_SHIFT) -# define TCN_CMR_ACPC_NONE (0 << TCN_CMR_ACPC_SHIFT) -# define TCN_CMR_ACPC_SET (1 << TCN_CMR_ACPC_SHIFT) -# define TCN_CMR_ACPC_CLEAR (2 << TCN_CMR_ACPC_SHIFT) -# define TCN_CMR_ACPC_TOGGLE (3 << TCN_CMR_ACPC_SHIFT) -#define TCN_CMR_AEEVT_SHIFT (20) /* Bits 20-21: External Event Effect on TIOA (Waveform mode) */ -#define TCN_CMR_AEEVT_MASK (3 << TCN_CMR_AEEVT_SHIFT) -# define TCN_CMR_AEEVT_NONE (0 << TCN_CMR_AEEVT_SHIFT) -# define TCN_CMR_AEEVT_SET (1 << TCN_CMR_AEEVT_SHIFT) -# define TCN_CMR_AEEVT_CLEAR (2 << TCN_CMR_AEEVT_SHIFT) -# define TCN_CMR_AEEVT_TOGGLE (3 << TCN_CMR_AEEVT_SHIFT) -#define TCN_CMR_ASWTRG_SHIFT (22) /* Bits 22-23: Software Trigger Effect on TIOA (Waveform mode) */ -#define TCN_CMR_ASWTRG_MASK (3 << TCN_CMR_ASWTRG_SHIFT) -# define TCN_CMR_ASWTRG_NONE (0 << TCN_CMR_ASWTRG_SHIFT) -# define TCN_CMR_ASWTRG_SET (1 << TCN_CMR_ASWTRG_SHIFT) -# define TCN_CMR_ASWTRG_CLEAR (2 << TCN_CMR_ASWTRG_SHIFT) -# define TCN_CMR_ASWTRG_TOGGLE (3 << TCN_CMR_ASWTRG_SHIFT) -#define TCN_CMR_BCPB_SHIFT (24) /* Bits 24-25: RB Compare Effect on TIOB (Waveform mode) */ -#define TCN_CMR_BCPB_MASK (3 << TCN_CMR_BCPB_SHIFT) -# define TCN_CMR_BCPB_NONE (0 << TCN_CMR_BCPB_SHIFT) -# define TCN_CMR_BCPB_SET (1 << TCN_CMR_BCPB_SHIFT) -# define TCN_CMR_BCPB_CLEAR (2 << TCN_CMR_BCPB_SHIFT) -# define TCN_CMR_BCPB_TOGGLE (3 << TCN_CMR_BCPB_SHIFT) -#define TCN_CMR_BCPC_SHIFT (26) /* Bits 26-27: RC Compare Effect on TIOB (Waveform mode) */ -#define TCN_CMR_BCPC_MASK (3 << TCN_CMR_BCPC_SHIFT) -# define TCN_CMR_BCPC_NONE (0 << TCN_CMR_BCPC_SHIFT) -# define TCN_CMR_BCPC_SET (1 << TCN_CMR_BCPC_SHIFT) -# define TCN_CMR_BCPC_CLEAR (2 << TCN_CMR_BCPC_SHIFT) -# define TCN_CMR_BCPC_TOGGLE (3 << TCN_CMR_BCPC_SHIFT) -#define TCN_CMR_BEEVT_SHIFT (28) /* Bits 28-29: External Event Effect on TIOB (Waveform mode) */ -#define TCN_CMR_BEEVT_MASK (3 << TCN_CMR_BEEVT_SHIFT) -# define TCN_CMR_BEEVT_NONE (0 << TCN_CMR_BEEVT_SHIFT) -# define TCN_CMR_BEEVT_SET (1 << TCN_CMR_BEEVT_SHIFT) -# define TCN_CMR_BEEVT_CLEAR (2 << TCN_CMR_BEEVT_SHIFT) -# define TCN_CMR_BEEVT_TOGGLE (3 << TCN_CMR_BEEVT_SHIFT) -#define TCN_CMR_BSWTRG_SHIFT (30) /* Bits 30-31: Software Trigger Effect on TIOB (Waveform mode) */ -#define TCN_CMR_BSWTRG_MASK (3 << TCN_CMR_BSWTRG_SHIFT) -# define TCN_CMR_BSWTRG_NONE (0 << TCN_CMR_BSWTRG_SHIFT) -# define TCN_CMR_BSWTRG_SET (1 << TCN_CMR_BSWTRG_SHIFT) -# define TCN_CMR_BSWTRG_CLEAR (2 << TCN_CMR_BSWTRG_SHIFT) -# define TCN_CMR_BSWTRG_TOGGLE (3 << TCN_CMR_BSWTRG_SHIFT) - -/* Stepper Motor Mode Register */ - -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# warning SAM4S not yet integrated -#endif - -/* TC Counter Value Register */ - -#define TCN_CV_SHIFT (0) /* Bits 0-15: Counter Value */ -#define TCN_CV_MASK (0xffff << TCN_CV_SHIFT) - -/* TC Register A, B, C */ - -#define TCN_RVALUE_SHIFT (0) /* Bits 0-15: Register A, B, or C value */ -#define TCN_RVALUE_MASK (0xffff << TCN_RVALUE_SHIFT) - -/* TC Status Register, TC Interrupt Enable Register, TC Interrupt Disable Register, and TC Interrupt Mask Register common bit-field definitions */ - -#define TCN_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow */ -#define TCN_INT_LOVRS (1 << 1) /* Bit 1: Load Overrun */ -#define TCN_INT_CPAS (1 << 2) /* Bit 2: RA Compare */ -#define TCN_INT_CPBS (1 << 3) /* Bit 3: RB Compare */ -#define TCN_INT_CPCS (1 << 4) /* Bit 4: RC Compare */ -#define TCN_INT_LDRAS (1 << 5) /* Bit 5: RA Loading */ -#define TCN_INT_LDRBS (1 << 6) /* Bit 6: RB Loading */ -#define TCN_INT_ETRGS (1 << 7) /* Bit 7: External Trigger */ -#define TCN_INT_CLKSTA (1 << 16) /* Bit 16: Clock Enabling (SR only) */ -#define TCN_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror (SR only) */ -#define TCN_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror (SR only)*/ - /* Fault Mode Register */ -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# warning SAM4S not yet integrated +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define TC_FMR_ENCF0 (1 << 0) /* Bit 0: Enable compare fault channel 0 */ +# define TC_FMR_ENCF1 (1 << 1) /* Bit 1: Enable compare fault channel 1 */ #endif /* Write Protect Mode Register */ -#if defined(CONFIG_ARCH_CHIP_SAM4S) -# warning SAM4S not yet integrated +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) +# define TC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +# define TC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +# define TC_WPMR_WPKEY_MASK (0x00ffffff << TC_WPMR_WPKEY_SHIFT) +# define TC_WPMR_WPKEY (0x0054494d << TC_WPMR_WPKEY_SHIFT) #endif /************************************************************************************************ diff --git a/arch/arm/src/sam34/chip/sam_twi.h b/arch/arm/src/sam34/chip/sam_twi.h index 1b6b11ce73..38dc9cf128 100644 --- a/arch/arm/src/sam34/chip/sam_twi.h +++ b/arch/arm/src/sam34/chip/sam_twi.h @@ -1,8 +1,8 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_twi.h - * Two-wire Interface (TWI) definitions for the SAM3U and SAM4S + * Two-wire Interface (TWI) definitions for the SAM3U, SAM4E, and SAM4S * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,19 +52,22 @@ /* TWI register offsets *****************************************************************/ -#define SAM_TWI_CR_OFFSET 0x00 /* Control Register */ -#define SAM_TWI_MMR_OFFSET 0x04 /* Master Mode Register */ -#define SAM_TWI_SMR_OFFSET 0x08 /* Slave Mode Register */ -#define SAM_TWI_IADR_OFFSET 0x0c /* Internal Address Register */ -#define SAM_TWI_CWGR_OFFSET 0x10 /* Clock Waveform Generator Register */ -#define SAM_TWI_SR_OFFSET 0x20 /* Status Register */ -#define SAM_TWI_IER_OFFSET 0x24 /* Interrupt Enable Register */ -#define SAM_TWI_IDR_OFFSET 0x28 /* Interrupt Disable Register */ -#define SAM_TWI_IMR_OFFSET 0x2c /* Interrupt Mask Register */ -#define SAM_TWI_RHR_OFFSET 0x30 /* Receive Holding Register */ -#define SAM_TWI_THR_OFFSET 0x34 /* Transmit Holding Register */ - /* 0x38-0xfc: Reserved */ - /* 0x100-0x124: Reserved for the PDC */ +#define SAM_TWI_CR_OFFSET 0x0000 /* Control Register */ +#define SAM_TWI_MMR_OFFSET 0x0004 /* Master Mode Register */ +#define SAM_TWI_SMR_OFFSET 0x0008 /* Slave Mode Register */ +#define SAM_TWI_IADR_OFFSET 0x000c /* Internal Address Register */ +#define SAM_TWI_CWGR_OFFSET 0x0010 /* Clock Waveform Generator Register */ +#define SAM_TWI_SR_OFFSET 0x0020 /* Status Register */ +#define SAM_TWI_IER_OFFSET 0x0024 /* Interrupt Enable Register */ +#define SAM_TWI_IDR_OFFSET 0x0028 /* Interrupt Disable Register */ +#define SAM_TWI_IMR_OFFSET 0x002c /* Interrupt Mask Register */ +#define SAM_TWI_RHR_OFFSET 0x0030 /* Receive Holding Register */ +#define SAM_TWI_THR_OFFSET 0x0034 /* Transmit Holding Register */ + /* 0x38-0xfc: Reserved */ +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TWI_WPMR_OFFSET 0x00e4 /* Protection Mode Register */ +# define SAM_TWI_WPSR_OFFSET 0x00e8 /* Protection Status Register */ +#endif /* TWI register adresses ****************************************************************/ @@ -79,6 +82,10 @@ #define SAM_TWI_IMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_IMR_OFFSET) #define SAM_TWI_RHR(n) (SAM_TWIN_BASE(n)+SAM_TWI_RHR_OFFSET) #define SAM_TWI_THR(n) (SAM_TWIN_BASE(n)+SAM_TWI_THR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TWI_WPMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_WPMR_OFFSET) +# define SAM_TWI_WPSR(n) (SAM_TWIN_BASE(n)+SAM_TWI_WPSR_OFFSET) +#endif #define SAM_TWI0_CR (SAM_TWI0_BASE+SAM_TWI_CR_OFFSET) #define SAM_TWI0_MMR (SAM_TWI0_BASE+SAM_TWI_MMR_OFFSET) @@ -91,6 +98,10 @@ #define SAM_TWI0_IMR (SAM_TWI0_BASE+SAM_TWI_IMR_OFFSET) #define SAM_TWI0_RHR (SAM_TWI0_BASE+SAM_TWI_RHR_OFFSET) #define SAM_TWI0_THR (SAM_TWI0_BASE+SAM_TWI_THR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TWI0_WPMR (SAM_TWI0_BASE+SAM_TWI_WPMR_OFFSET) +# define SAM_TWI0_WPSR (SAM_TWI0_BASE)+SAM_TWI_WPSR_OFFSET) +#endif #define SAM_TWI1_CR (SAM_TWI1_BASE+SAM_TWI_CR_OFFSET) #define SAM_TWI1_MMR (SAM_TWI1_BASE+SAM_TWI_MMR_OFFSET) @@ -103,6 +114,10 @@ #define SAM_TWI1_IMR (SAM_TWI1_BASE+SAM_TWI_IMR_OFFSET) #define SAM_TWI1_RHR (SAM_TWI1_BASE+SAM_TWI_RHR_OFFSET) #define SAM_TWI1_THR (SAM_TWI1_BASE+SAM_TWI_THR_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define SAM_TWI1_WPMR (SAM_TWI1_BASE+SAM_TWI_WPMR_OFFSET) +# define SAM_TWI1_WPSR (SAM_TWI1_BASE)+SAM_TWI_WPSR_OFFSET) +#endif /* TWI register bit definitions *********************************************************/ @@ -143,10 +158,13 @@ #define TWI_CWGR_CLDIV_SHIFT (0) /* Bits 0-7: Clock Low Divider */ #define TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT) +# define TWI_CWGR_CLDIV(n) ((uint32_t)(n) << TWI_CWGR_CLDIV_SHIFT) #define TWI_CWGR_CHDIV_SHIFT (8) /* Bits 8-15: Clock High Divider */ #define TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT) +# define TWI_CWGR_CHDIV(n) ((uint32_t)(n) << TWI_CWGR_CLDIV_SHIFT) #define TWI_CWGR_CKDIV_SHIFT (16) /* Bits 16-18: Clock Divider */ #define TWI_CWGR_CKDIV_MASK (7 << TWI_CWGR_CLDIV_SHIFT) +# define TWI_CWGR_CKDIV(n) ((uint32_t)(n) << TWI_CWGR_CLDIV_SHIFT) /* TWI Status Register, TWI Interrupt Enable Register, TWI Interrupt Disable * Register, and TWI Interrupt Mask Register common bit fields. @@ -178,6 +196,23 @@ #define TWI_THR_TXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Transmit Holding Data */ #define TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT) +/* Protection Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define TWI_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +# define TWI_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect Key */ +# define TWI_WPMR_WPKEY_MASK (0x00ffffff << TWI_WPMR_WPKEY_SHIFT) +# define TWI_WPMR_WPKEY (0x00545749 << TWI_WPMR_WPKEY_SHIFT) +#endif + +/* Protection Status Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4E) +# define TWI_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +# define TWI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +# define TWI_WPSR_WPVSRC_MASK (0xffff << TWI_WPSR_WPVSRC_SHIFT) +#endif + /**************************************************************************************** * Public Types ****************************************************************************************/ diff --git a/arch/arm/src/sam34/sam3u_dmac.c b/arch/arm/src/sam34/sam_dmac.c similarity index 99% rename from arch/arm/src/sam34/sam3u_dmac.c rename to arch/arm/src/sam34/sam_dmac.c index f2304c9318..ff9e55c630 100644 --- a/arch/arm/src/sam34/sam3u_dmac.c +++ b/arch/arm/src/sam34/sam_dmac.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/sam34/sam3u_dmac.c + * arch/arm/src/sam34/sam_dmac.c * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -58,7 +58,7 @@ #include "sam_dmac.h" #include "sam_periphclks.h" #include "chip/sam_pmc.h" -#include "chip/sam3u_dmac.h" +#include "chip/sam_dmac.h" /**************************************************************************** * Pre-processor Definitions @@ -68,7 +68,7 @@ /* Condition out the whole file unless DMA is selected in the configuration */ -#ifdef CONFIG_SAM34_DMA +#ifdef CONFIG_SAM34_DMAC /* If AT90SAM3U support is enabled, then OS DMA support should also be enabled */ @@ -1715,4 +1715,4 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, dmadbg(" CFG[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CFG_OFFSET, regs->cfg); } #endif /* CONFIG_DEBUG_DMA */ -#endif /* CONFIG_SAM34_DMA */ +#endif /* CONFIG_SAM34_DMAC */ diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c index 5a406752cd..f619f1bd00 100644 --- a/arch/arm/src/sam34/sam_hsmci.c +++ b/arch/arm/src/sam34/sam_hsmci.c @@ -64,7 +64,7 @@ #include "sam_dmac.h" #include "sam_hsmci.h" #include "sam_periphclks.h" -#include "chip/sam3u_dmac.h" +#include "chip/sam_dmac.h" #include "chip/sam_pmc.h" #include "chip/sam_hsmci.h" #include "chip/sam_pinmap.h" @@ -77,8 +77,8 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_SAM34_DMA -# warning "HSMCI driver requires CONFIG_SAM34_DMA" +#ifndef CONFIG_SAM34_DMAC +# warning "HSMCI driver requires CONFIG_SAM34_DMAC" #endif #ifndef CONFIG_SCHED_WORKQUEUE diff --git a/configs/arduino-due/README.txt b/configs/arduino-due/README.txt index 923db50542..6336d637de 100644 --- a/configs/arduino-due/README.txt +++ b/configs/arduino-due/README.txt @@ -817,7 +817,7 @@ Arduino DUE-specific Configuration Options CONFIG_SAM34_PWM - Pulse Width Modulation CONFIG_SAM34_ADC12B - 12-bit Analog To Digital Converter CONFIG_SAM34_DACC - Digital To Analog Converter - CONFIG_SAM34_DMA - DMA Controller + CONFIG_SAM34_DMAC - DMA Controller CONFIG_SAM34_UOTGHS - USB OTG High Speed CONFIG_SAM34_TRNG - True Random Number Generator CONFIG_SAM34_EMAC - Ethernet MAC diff --git a/configs/arduino-due/nsh/defconfig b/configs/arduino-due/nsh/defconfig index 704f852872..8521661f13 100644 --- a/configs/arduino-due/nsh/defconfig +++ b/configs/arduino-due/nsh/defconfig @@ -165,7 +165,7 @@ CONFIG_SAM34_UART0=y # CONFIG_SAM34_CAN1 is not set # CONFIG_SAM34_SMC is not set # CONFIG_SAM34_SDRAMC is not set -# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_DMAC is not set # CONFIG_SAM34_UOTGHS is not set # CONFIG_SAM34_RTC is not set # CONFIG_SAM34_RTT is not set diff --git a/configs/arduino-due/ostest/defconfig b/configs/arduino-due/ostest/defconfig index 1e1f66771f..64cb4a92b8 100644 --- a/configs/arduino-due/ostest/defconfig +++ b/configs/arduino-due/ostest/defconfig @@ -165,7 +165,7 @@ CONFIG_SAM34_UART0=y # CONFIG_SAM34_CAN1 is not set # CONFIG_SAM34_SMC is not set # CONFIG_SAM34_SDRAMC is not set -# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_DMAC is not set # CONFIG_SAM34_UOTGHS is not set # CONFIG_SAM34_RTC is not set # CONFIG_SAM34_RTT is not set diff --git a/configs/sam3u-ek/README.txt b/configs/sam3u-ek/README.txt index fc5874b30e..a8d23ba7e0 100644 --- a/configs/sam3u-ek/README.txt +++ b/configs/sam3u-ek/README.txt @@ -381,7 +381,7 @@ SAM3U-EK-specific Configuration Options CONFIG_SAM34_PWM - Pulse Width Modulation Controller CONFIG_SAM34_ADC12B - 12-bit ADC Controller CONFIG_SAM34_ADC - 10-bit ADC Controller - CONFIG_SAM34_DMA - DMA Controller + CONFIG_SAM34_DMAC - DMA Controller CONFIG_SAM34_UDPHS - USB Device High Speed Some subsystems can be configured to operate in different ways. The drivers @@ -646,7 +646,7 @@ Configurations System Type->ATSAM3/4 Peripheral Support CONFIG_SAM34_HSMCI=y : Enable HSMCI support - CONFIG_SAM34_DMA=y : DMAC support is needed by HSMCI + CONFIG_SAM34_DMAC=y : DMAC support is needed by HSMCI System Type CONFIG_SAM34_GPIO_IRQ=y : PIO interrupts needed diff --git a/configs/sam3u-ek/knsh/defconfig b/configs/sam3u-ek/knsh/defconfig index 4ac7345fcb..865f020752 100644 --- a/configs/sam3u-ek/knsh/defconfig +++ b/configs/sam3u-ek/knsh/defconfig @@ -154,7 +154,7 @@ CONFIG_SAM34_UART0=y # CONFIG_SAM34_ADC is not set # CONFIG_SAM34_SMC is not set # CONFIG_SAM34_NAND is not set -# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_DMAC is not set # CONFIG_SAM34_UDPHS is not set # CONFIG_SAM34_RTC is not set # CONFIG_SAM34_RTT is not set diff --git a/configs/sam3u-ek/nsh/defconfig b/configs/sam3u-ek/nsh/defconfig index f48ed59386..8acd63b071 100644 --- a/configs/sam3u-ek/nsh/defconfig +++ b/configs/sam3u-ek/nsh/defconfig @@ -165,7 +165,7 @@ CONFIG_SAM34_UART0=y # CONFIG_SAM34_ADC is not set # CONFIG_SAM34_SMC is not set # CONFIG_SAM34_NAND is not set -# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_DMAC is not set # CONFIG_SAM34_UDPHS is not set # CONFIG_SAM34_UOTGHS is not set # CONFIG_SAM34_RTC is not set diff --git a/configs/sam3u-ek/nx/defconfig b/configs/sam3u-ek/nx/defconfig index 11314604a3..92ef5066c7 100644 --- a/configs/sam3u-ek/nx/defconfig +++ b/configs/sam3u-ek/nx/defconfig @@ -146,7 +146,7 @@ CONFIG_SAM34_UART0=y # CONFIG_SAM34_ADC is not set # CONFIG_SAM34_SMC is not set # CONFIG_SAM34_NAND is not set -# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_DMAC is not set # CONFIG_SAM34_UDPHS is not set # CONFIG_SAM34_RTC is not set # CONFIG_SAM34_RTT is not set diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig index 1214e2fafc..eab2923394 100644 --- a/configs/sam3u-ek/nxwm/defconfig +++ b/configs/sam3u-ek/nxwm/defconfig @@ -180,7 +180,7 @@ CONFIG_SAM34_UART0=y # CONFIG_SAM34_ADC is not set # CONFIG_SAM34_SMC is not set # CONFIG_SAM34_NAND is not set -# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_DMAC is not set # CONFIG_SAM34_UDPHS is not set # CONFIG_SAM34_UOTGHS is not set # CONFIG_SAM34_RTC is not set diff --git a/configs/sam3u-ek/ostest/defconfig b/configs/sam3u-ek/ostest/defconfig index 40b1816aca..190306f591 100644 --- a/configs/sam3u-ek/ostest/defconfig +++ b/configs/sam3u-ek/ostest/defconfig @@ -146,7 +146,7 @@ CONFIG_SAM34_UART0=y # CONFIG_SAM34_ADC is not set # CONFIG_SAM34_SMC is not set # CONFIG_SAM34_NAND is not set -# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_DMAC is not set # CONFIG_SAM34_UDPHS is not set # CONFIG_SAM34_RTC is not set # CONFIG_SAM34_RTT is not set