diff --git a/arch/arm/src/sama5/sam_dmac.h b/arch/arm/src/sama5/sam_dmac.h
index 0fa1919a24..307276f0f6 100644
--- a/arch/arm/src/sama5/sam_dmac.h
+++ b/arch/arm/src/sama5/sam_dmac.h
@@ -323,6 +323,7 @@ struct sam_dmaregs_s
 
   /* Channel Registers */
 
+  uint32_t cim;     /* Channel Interrupt Mask Register */
   uint32_t cis;     /* Channel Interrupt Status Register */
   uint32_t csa;     /* Channel Source Address Register */
   uint32_t cda;     /* Channel Destination Address Register */
diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c
index 92f11b1583..423fc40ce5 100644
--- a/arch/arm/src/sama5/sam_xdmac.c
+++ b/arch/arm/src/sama5/sam_xdmac.c
@@ -1133,11 +1133,13 @@ static inline uint32_t sam_txcc(struct sam_xdmach_s *xdmach)
       field   = sam_sink_channel(xdmach, pid);
       regval |= (field << XDMACH_CC_CSIZE_SHIFT);
 
+#if 0 /* Not supported */
       /* 10. Set SWREQ to use software request (only relevant for a
        *     peripheral synchronized transfer).
        */
 
       regval |= XDMACH_CC_SWREQ;
+#endif
     }
 
   return regval;
@@ -1287,11 +1289,13 @@ static inline uint32_t sam_rxcc(struct sam_xdmach_s *xdmach)
       field   = sam_source_channel(xdmach, pid);
       regval |= (field << XDMACH_CC_CSIZE_SHIFT);
 
+#if 0 /* Not supported */
       /* 10. Set SWREQ to use software request (only relevant for a
        *     peripheral synchronized transfer).
        */
 
       regval |= XDMACH_CC_SWREQ;
+#endif
     }
 
   return regval;
@@ -2421,6 +2425,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
 
   /* Sample channel registers */
 
+  regs->cim    = sam_getdmach(xdmach, SAM_XDMACH_CIM_OFFSET);
   regs->cis    = sam_getdmach(xdmach, SAM_XDMACH_CIS_OFFSET);
   regs->csa    = sam_getdmach(xdmach, SAM_XDMACH_CSA_OFFSET);
   regs->cda    = sam_getdmach(xdmach, SAM_XDMACH_CDA_OFFSET);
@@ -2467,6 +2472,7 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
   dmadbg("       GWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWS_OFFSET, regs->gws);
   dmadbg("      GSWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GSWS_OFFSET, regs->gsws);
   dmadbg("  DMA Channel Registers:\n");
+  dmadbg("       CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim);
   dmadbg("       CIS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIS_OFFSET, regs->cis);
   dmadbg("       CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa);
   dmadbg("       CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda);