arch/arm/src/imxrt/chip: Add more eDMA register definitions. Still missing TCD definitions.
This commit is contained in:
Gregory Nutt
parent
8f0b87a2d9
commit
3b355d52f2
@ -964,67 +964,272 @@
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/* eDMA Bit-Field Definitions ***********************************************************************/
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/* Control */
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#define EDMA_CR_
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/* Bit 0: Reserved */
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#define EDMA_CR_EDBG (1 << 1) /* Bit 1: Enable Debug */
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#define EDMA_CR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration */
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#define EDMA_CR_ERGA (1 << 3) /* Bit 3: Enable Round Robin Group Arbitration */
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#define EDMA_CR_HOE (1 << 4) /* Bit 4: Halt On Error */
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#define EDMA_CR_HALT (1 << 5) /* Bit 5: Halt DMA Operations */
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#define EDMA_CR_CLM (1 << 6) /* Bit 6: Continuous Link Mode */
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#define EDMA_CR_EMLM (1 << 7) /* Bit 7: Enable Minor Loop Mapping */
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#define EDMA_CR_GRP0PRI (1 << 8) /* Bit 8: Channel Group 0 Priority */
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/* Bit 9: Reserved */
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#define EDMA_CR_GRP1PRI (1 << 10) /* Bit 10: Channel Group 1 Priority */
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/* Bits 11-15: Reserved */
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#define EDMA_CR_ECX (1 << 16) /* Bit 16: Error Cancel Transfer */
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#define EDMA_CR_CX (1 << 17) /* Bit 17: Cancel Transfer */
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/* Bits 18-23: Reserved */
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/* Bits 24-30: eDMA version number (reserved) */
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#define EDMA_CR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status */
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/* Error Status */
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#define EDMA_ES_
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#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error */
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#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error */
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#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error */
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#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error */
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#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error */
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#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error */
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#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error */
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#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error */
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#define EDMA_ES_ERRCHN_SHIFT (8) /* Bits 8-12: Error Channel Number or
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* Canceled Channel Number */
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#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT)
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/* Bit 13: Reserved */
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#define EDMA_ES_CPE (1 << 14) /* Bit 14: Channel Priority Error */
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#define EDMA_ES_GPE (1 << 15) /* Bit 15: Group Priority Error */
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#define EDMA_ES_ECX (1 << 16) /* Bit 16: Transfer Canceled */
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/* Bits 17-30: Reserved */
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#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status bits */
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/* Enable Request */
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#define EDMA_ERQ_
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#define EDMA_ERQ(n) ((uint32_t)1 << (n)) /* Bit n: Enable DMA request n */
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/* Enable Error Interrupt */
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#define EDMA_EEI_
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#define EDMA_EEI(n) ((uint32_t)1 << (n)) /* Bit n: Enable error interrupt n */
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/* Clear Enable Error Interrupt */
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#define EDMA_CEEI_
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#define EDMA_CEEI_SHIFT (0) /* Bits 0-4: Clear Enable Error Interrupt */
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#define EDMA_CEEI_MASK (0x1f << EDMA_CEEI_SHIFT)
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# define EDMA_CEEI(n) ((uint32_t)(n) << EDMA_CEEI_SHIFT)
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/* Bit 5: Reserved */
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#define EDMA_CEEI_CAEE (1 << 6) /* Bit 6: Clear All Enable Error Interrupts */
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#define EDMA_CEEI_NOP (1 << 7) /* Bit 7: No Op enable */
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/* Set Enable Error Interrupt */
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#define EDMA_SEEI_
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#define EDMA_SEEI_SHIFT (0) /* Bits 0-4: Set Enable Error Interrupt */
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#define EDMA_SEEI_MASK (0x1f << EDMA_SEEI_SHIFT)
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# define EDMA_SEEI(n) ((uint32_t)(n) << EDMA_SEEI_SHIFT)
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/* Bit 5: Reserved */
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#define EDMA_SEEI_SAEE (1 << 6) /* Bit 6: Set All Enable Error Interrupts */
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#define EDMA_SEEI_NOP (1 << 7) /* Bit 7: No Op enable */
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/* Clear Enable Request */
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#define EDMA_CERQ_
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#define EDMA_CERQ_SHIFT (0) /* Bits 0-4: Clear Enable Request */
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#define EDMA_CERQ_MASK (0x1f << EDMA_CERQ_SHIFT)
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# define EDMA_CERQ(n) ((uint32_t)(n) << EDMA_CERQ_SHIFT)
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/* Bit 5: Reserved */
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#define EDMA_CERQ_CAER (1 << 6) /* Bit 6: Clear All Enable Requests */
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#define EDMA_CERQ_NOP (1 << 7) /* Bit 7: No Op enable */
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/* Set Enable Request */
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#define EDMA_SERQ_
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#define EDMA_SERQ_SHIFT (0) /* Bits 0-4: Set Enable Request */
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#define EDMA_SERQ_MASK (0x1f << EDMA_SERQ_SHIFT)
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# define EDMA_SERQ(n) ((uint32_t)(n) << EDMA_SERQ_SHIFT)
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/* Bit 5: Reserved */
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#define EDMA_SERQ_SAER (1 << 6) /* Bit 6: Set All Enable Requests */
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#define EDMA_SERQ_NOP (1 << 7) /* Bit 7: No Op enable */
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/* Clear DONE Status Bit */
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#define EDMA_CDNE_
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#define EDMA_CDNE_SHIFT (0) /* Bits 0-4: Clear DONE Bit */
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#define EDMA_CDNE_MASK (0x1f << EDMA_CDNE_SHIFT)
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# define EDMA_CDNE(n) ((uint32_t)(n) << EDMA_CDNE_SHIFT)
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/* Bit 5: Reserved */
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#define EDMA_CDNE_CADN (1 << 6) /* Bit 6: Clears All DONE Bits */
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#define EDMA_CDNE_NOP (1 << 7) /* Bit 7: No Op enable */
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/* Set START Bit */
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#define EDMA_SSRT_
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#define EDMA_SSRT_SHIFT (0) /* Bits 0-4: Set START Bit */
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#define EDMA_SSRT_MASK (0x1f << EDMA_SSRT_SHIFT)
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# define EDMA_SSRT(n) ((uint32_t)(n) << EDMA_SSRT_SHIFT)
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/* Bit 5: Reserved */
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#define EDMA_SSRT_SAST (1 << 6) /* Bit 6: Set All START Bits (activates all channels) */
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#define EDMA_SSRT_NOP (1 << 7) /* Bit 7: No Op enable */
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/* Clear Error */
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#define EDMA_CERR_
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#define EDMA_CERR_SHIFT (0) /* Bits 0-4: Clear Error Indicator */
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#define EDMA_CERR_MASK (0x1f << EDMA_CERR_SHIFT)
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# define EDMA_CERR(n) ((uint32_t)(n) << EDMA_CERR_SHIFT)
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/* Bit 5: Reserved */
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#define EDMA_CERR_CAEI (1 << 6) /* Bit 6: Clear All Error Indicators */
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#define EDMA_CERR_NOP (1 << 7) /* Bit 7: No Op enable */
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/* Clear Interrupt Request */
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#define EDMA_CINT_
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#define EDMA_CINT_SHIFT (0) /* Bits 0-4: Clear Interrupt Request */
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#define EDMA_CINT_MASK (0x1f << EDMA_CINT_SHIFT)
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# define EDMA_CINT(n) ((uint32_t)(n) << EDMA_CINT_SHIFT)
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/* Bit 5: Reserved */
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#define EDMA_CINT_CAIR (1 << 6) /* Bit 6: Clear All Interrupt Requests */
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#define EDMA_CINT_NOP (1 << 7) /* Bit 7: No Op enable */
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/* Interrupt Request */
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#define EDMA_INT_
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#define EDMA_INT(n) ((uint32_t)1 << (n)) /* Bit n: Interrupt Request n */
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/* Error */
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#define EDMA_ERR_
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#define EDMA_ERR(n) ((uint32_t)1 << (n)) /* Bit n: Error In Channel n */
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/* Hardware Request Status */
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#define EDMA_HRS_
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#define EDMA_HRS(n) ((uint32_t)1 << (n)) /* Bit n: Hardware Request Status
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* Channel n */
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/* Enable Asynchronous Request in Stop */
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#define EDMA_EARS_
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#define EDMA_EARS(n) ((uint32_t)1 << (n)) /* Bit n: Enable asynchronous DMA
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* request in stop mode for channel n */
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/* Channel n Priority */
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#define EDMA_DCHPRI_
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/* TCD Source Address */
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#define EDMA_TCD_SADDR_
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/* TCD Signed Source Address Offset */
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#define EDMA_TCD_SOFF_
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#define EDMA_DCHPRI_CHPRI_SHIFT (0) /* Bits 0-3: Channel n Arbitration Priority */
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#define EDMA_DCHPRI_CHPRI_MASK (15 << EDMA_DCHPRI_CHPRI_SHIFT)
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# define EDMA_DCHPRI_CHPRI(n) ((uint32_t)(n) << EDMA_DCHPRI_CHPRI_SHIFT)
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#define EDMA_DCHPRI_GRPPRI_SHIFT (4) /* Bits 4-5: Channel n Current Group Priority */
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#define EDMA_DCHPRI_GRPPRI_MASK (3 << EDMA_DCHPRI_GRPPRI_SHIFT)
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# define EDMA_DCHPRI_GRPPRI(n) ((uint32_t)(n) << EDMA_DCHPRI_GRPPRI_SHIFT)
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#define EDMA_DCHPRI_DPA (1 << 6) /* Bit 6: Disable Preempt Ability */
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#define EDMA_DCHPRI_ECP (1 << 7) /* Bit 7: Enable Channel Preemption */
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/* TCD Source Address (32-bit address) */
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/* TCD Signed Source Address Offset (16-bit offset) */
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/* TCD Transfer Attributes */
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#define EDMA_TCD_ATTR_
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#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination data transfer size */
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#define EDMA_TCD_ATTR_DSIZE_MASK (7 << EDMA_TCD_ATTR_DSIZE_SHIFT)
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# define EDMA_TCD_ATTR_DSIZE_8BIT (0 << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 8-bit */
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# define EDMA_TCD_ATTR_DSIZE_16BIT (1 << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 16-bit */
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# define EDMA_TCD_ATTR_DSIZE_32BIT (2 << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-bit */
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# define EDMA_TCD_ATTR_DSIZE_64BIT (3 << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 64-bit */
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# define EDMA_TCD_ATTR_DSIZE_4x64BIT (5 << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-byte burst (4
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* beats of 64 bits) */
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#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo */
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#define EDMA_TCD_ATTR_DMOD_MASK (31 << EDMA_TCD_ATTR_DMOD_SHIFT)
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# define EDMA_TCD_ATTR_DMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DMOD_SHIFT)
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#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source data transfer size */
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#define EDMA_TCD_ATTR_SSIZE_MASK (7 << EDMA_TCD_ATTR_SSIZE_SHIFT)
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# define EDMA_TCD_ATTR_SSIZE_8BIT (0 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
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# define EDMA_TCD_ATTR_SSIZE_16BIT (1 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
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# define EDMA_TCD_ATTR_SSIZE_32BIT (2 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
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# define EDMA_TCD_ATTR_SSIZE_64BIT (3 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
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# define EDMA_TCD_ATTR_SSIZE_4x64BIT (5 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte burst (4
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* beats of 64 bits) */
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#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo */
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#define EDMA_TCD_ATTR_SMOD_MASK (31 << EDMA_TCD_ATTR_SMOD_SHIFT)
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# define EDMA_TCD_ATTR_SMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_SMOD_SHIFT)
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/* TCD Signed Minor Loop Offset / Byte Count */
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#define EDMA_TCD_NBYTES_MLOFFNO_
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#define EDMA_TCD_NBYTES_MLOFFYES_
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#define EDMA_TCD_NBYTES_MLNO_
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/* TCD Last Source Address Adjustment */
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#define EDMA_TCD_SLAST_
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/* TCD Destination Address */
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#define EDMA_TCD_DADDR_
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/* TCD Signed Destination Address Offset */
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#define EDMA_TCD_DOFF_
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/* TCD Current Minor Loop Link, Major Loop Count */
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#define EDMA_TCD_CITER_ELINKYES_
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#define EDMA_TCD_CITER_ELINKNO_
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/* TCD Last Destination Address Adjustment/Scatter Gather Address */
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#define EDMA_TCD_DLASTSGA_
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/* Minor Byte Count (Minor Loop Mapping Disabled -- 32-bit byte count) */
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/* TCD Signed Minor Loop Offset / Byte Count */
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/* Minor Byte Count (Minor Loop Mapping Enabled, offset disabled) */
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#define EDMA_TCD_NBYTES_ML_NBYTES_SHIFT (0) /* Bits 0-29: Minor Byte Transfer Count */
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#define EDMA_TCD_NBYTES_ML_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_ML_NBYTES_SHIFT)
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# define EDMA_TCD_NBYTES_ML_NBYTES(n) ((uint32_t)(n) << EDMA_TCD_NBYTES_ML_NBYTES_SHIFT)
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#define EDMA_TCD_NBYTES_ML_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset enable */
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#define EDMA_TCD_NBYTES_ML_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */
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/* TCD Signed Minor Loop Offset / Byte Count */
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/* Minor Byte Count (Minor Loop Mapping Enabled, offset enabled) */
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#define EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT (0) /* Bits 0-9: Minor Byte Transfer Count */
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#define EDMA_TCD_NBYTES_MLOFF_NBYTES_MASK (0x3ff << EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT)
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# define EDMA_TCD_NBYTES_MLOFF_NBYTES(n) ((uint32_t)(n) << EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT)
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#define EDMA_TCD_NBYTES_MLOFF_MLOFF_SHIFT (10) /* Bits 10-29: Minor Byte Transfer Count */
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#define EDMA_TCD_NBYTES_MLOFF_MLOFF_MASK (0xfffff << EDMA_TCD_NBYTES_MLOFF_MLOFF_SHIFT)
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# define EDMA_TCD_NBYTES_MLOFF_MLOFF(n) ((uint32_t)(n) << EDMA_TCD_NBYTES_MLOFF_MLOFF_SHIFT)
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#define EDMA_TCD_NBYTES_MLOFF_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset enable */
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#define EDMA_TCD_NBYTES_MLOFF_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */
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/* TCD Last Source Address Adjustment (32-bit address adjustment */
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/* TCD Destination Address (32-bit address) */
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/* TCD Signed Destination Address Offset (32-bit signed address offset) */
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/* TCD Current Minor Loop Link, Major Loop Count (Channel linking disabled) */
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#define EDMA_TCD_CITER_CITER_SHIFT (0) /* Bit 0-14: Starting Major Iteration Count */
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#define EDMA_TCD_CITER_CITER_MASK (0x7fff << EDMA_TCD_CITER_CITER_SHIFT)
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# define EDMA_TCD_CITER_CITER(n) ((uint32_t)(n) << EDMA_TCD_CITER_CITER_SHIFT)
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#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
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* on minor-loop complete */
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/* TCD Current Minor Loop Link, Major Loop Count (Channel linking enabled) */
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#define EDMA_TCD_CITER_ELINK_CITER_SHIFT (0) /* Bit 0-8: Current major iteration count */
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#define EDMA_TCD_CITER_ELINK_CITER_MASK (0x1ff << EDMA_TCD_CITER_ELINK_CITER_SHIFT)
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# define EDMA_TCD_CITER_ELINK_CITER(n) ((uint32_t)(n) << EDMA_TCD_CITER_ELINK_CITER_SHIFT)
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#define EDMA_TCD_CITER_ELINK_LINKCH_SHIFT (9) /* Bit 9-13: Minor Loop Link Channel Number */
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#define EDMA_TCD_CITER_ELINK_LINKCH_MASK (31 << EDMA_TCD_CITER_ELINK_LINKCH_SHIFT)
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# define EDMA_TCD_CITER_ELINK_LINKCH(n) ((uint32_t)(n) << EDMA_TCD_CITER_ELINK_LINKCH_SHIFT)
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/* Bit 14: Reserved */
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#define EDMA_TCD_CITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
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* on minor-loop complete */
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/* TCD Last Destination Address Adjustment/Scatter Gather Address (32-bit address) */
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/* TCD Control and Status */
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#define EDMA_TCD_CSR_
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/* TCD Beginning Minor Loop Link, Major Loop Count */
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#define EDMA_TCD_BITER_ELINKYES_
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#define EDMA_TCD_BITER_ELINKNO_
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#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start */
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#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable an interrupt when major
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* iteration count completes */
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#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable an interrupt when major
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* counter is half complete */
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#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request */
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#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing */
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#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable channel-to-channel linking
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* on major loop complete */
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#define EDMA_TCD_CSR_ACTIVE (1 << 6) /* Bit 6: Channel Active */
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#define EDMA_TCD_CSR_DONE (1 << 7) /* Bit 7: Channel Done */
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#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number */
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/* Bit 13: Reserved */
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#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control */
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#define EDMA_TCD_CSR_BWC_MASK (3 << EDMA_TCD_CSR_BWC_SHIFT)
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# define EDMA_TCD_CSR_BWC_NONE (0 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */
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# define EDMA_TCD_CSR_BWC_4CYCLES (2 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4
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* cycles after each R/W */
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# define EDMA_TCD_CSR_BWC_8CYCLES (3 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8
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* cycles after each R/W */
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/* TCD Beginning Minor Loop Link, Major Loop Count (Channel linking disabled) */
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#define EDMA_TCD_BITER_BITER_SHIFT (0) /* Bit 0-14: Starting Major Iteration Count */
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#define EDMA_TCD_BITER_BITER_MASK (0x7fff << EDMA_TCD_BITER_BITER_SHIFT)
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# define EDMA_TCD_BITER_BITER(n) ((uint32_t)(n) << EDMA_TCD_BITER_BITER_SHIFT)
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#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
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* on minor-loop complete */
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/* TCD Beginning Minor Loop Link, Major Loop Count (Channel linking enabled) */
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#define EDMA_TCD_BITER_ELINK_BITER_SHIFT (0) /* Bit 0-8: Current major iteration count */
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#define EDMA_TCD_BITER_ELINK_BITER_MASK (0x1ff << EDMA_TCD_BITER_ELINK_BITER_SHIFT)
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# define EDMA_TCD_BITER_ELINK_BITER(n) ((uint32_t)(n) << EDMA_TCD_BITER_ELINK_BITER_SHIFT)
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#define EDMA_TCD_BITER_ELINK_LINKCH_SHIFT (9) /* Bit 9-13: Link Channel Number */
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#define EDMA_TCD_BITER_ELINK_LINKCH_MASK (31 << EDMA_TCD_BITER_ELINK_LINKCH_SHIFT)
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# define EDMA_TCD_BITER_ELINK_LINKCH(n) ((uint32_t)(n) << EDMA_TCD_BITER_ELINK_LINKCH_SHIFT)
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/* Bit 14: Reserved */
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#define EDMA_TCD_BITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
|
||||
* on minor-loop complete */
|
||||
|
||||
/* TCD Structure Definitions ************************************************************************/
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user