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SAMA5 UDPHS: Support USPHS clock configuration

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This commit is contained in:
Gregory Nutt 2013-09-01 11:29:51 -06:00
parent 06355a17e1
commit 3ba3dfd9bc
2 changed files with 13 additions and 5 deletions
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14
arch/arm/src/sama5/sam_clockconfig.c
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@ -330,7 +330,14 @@ static inline void sam_selectplla(void)
static inline void sam_usbclockconfig(void)
{
#if defined(CONFIG_SAMA5_EHCI)
#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
defined(CONFIG_SAMA5_UDPHS)
/* We can either get the clock from the UPLL or from PLLA. In this latter
* case, however, the PLLACK frequency must be a multiple of 48MHz.
*/
#if defined(BOARD_USE_UPLL)
uint32_t regval;
/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the
@ -395,7 +402,7 @@ static inline void sam_usbclockconfig(void)
regval |= PMC_USB_USBDIV(9);
putreg32(regval, SAM_PMC_USB);
#elif defined(CONFIG_SAMA5_OHCI)
#else /* BOARD_USE_UPLL */
/* For OHCI Full-speed operations only, the user has to perform the
* following:
*
@ -415,7 +422,8 @@ static inline void sam_usbclockconfig(void)
putreg32(BOARD_OHCI_INPUT | BOARD_OHCI_DIVIDER << PMC_USB_USBDIV_SHIFT,
SAM_PMC_USB);
#endif
#endif /* BOARD_USE_UPLL */
#endif /* CONFIG_SAMA5_EHCI ||CONFIG_SAMA5_OHCI) || CONFIG_SAMA5_UDPHS */
}
/****************************************************************************

4
arch/arm/src/sama5/sam_periphclks.h
View File

@ -52,8 +52,8 @@
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0)
#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0)