STM32 OTGFS device: Various changes to try to reduce that amount of time in interrupts handles and with interrupts disbled. Needs verification on other platforms. From Petteri Aimonen
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@ -1,7 +1,7 @@
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/*******************************************************************************
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* arch/arm/src/stm32/stm32_otgfsdev.c
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*
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* Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2012-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -4055,7 +4055,7 @@ static void stm32_epout_disable(FAR struct stm32_ep_s *privep)
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while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0);
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#else
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/* REVISIT: */
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up_mdelay(50);
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up_udelay(10);
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#endif
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/* Clear the EPDISD interrupt indication */
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@ -4113,7 +4113,6 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep)
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*/
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#if 0
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/* Make sure that there is no pending IPEPNE interrupt (because we are
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* to poll this bit below).
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*/
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@ -4136,7 +4135,6 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep)
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/* Clear the INEPNE interrupt indication */
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stm32_putreg(OTGFS_DIEPINT_INEPNE, regaddr);
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#endif
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/* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits
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@ -4174,7 +4172,6 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep)
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/* Cancel any queued write requests */
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stm32_req_cancel(privep, -ESHUTDOWN);
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irqrestore(flags);
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}
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@ -4197,6 +4194,7 @@ static int stm32_ep_disable(FAR struct usbdev_ep_s *ep)
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return -EINVAL;
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}
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#endif
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usbtrace(TRACE_EPDISABLE, privep->epphy);
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/* Is this an IN or an OUT endpoint */
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@ -4236,6 +4234,7 @@ static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep)
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return NULL;
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}
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#endif
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usbtrace(TRACE_EPALLOCREQ, ((FAR struct stm32_ep_s *)ep)->epphy);
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privreq = (FAR struct stm32_req_s *)kmalloc(sizeof(struct stm32_req_s));
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@ -4485,7 +4484,7 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep)
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while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0);
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#else
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/* REVISIT: */
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up_mdelay(50);
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up_udelay(10);
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#endif
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/* Disable Global OUT NAK mode */
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@ -4870,7 +4869,7 @@ static int stm32_wakeup(struct usbdev_s *dev)
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* Name: stm32_selfpowered
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*
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* Description:
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* Sets/clears the device selfpowered feature
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* Sets/clears the device self-powered feature
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*
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*******************************************************************************/
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@ -4926,8 +4925,6 @@ static int stm32_pullup(struct usbdev_s *dev, bool enable)
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}
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stm32_putreg(regval, STM32_OTGFS_DCTL);
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up_mdelay(3);
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irqrestore(flags);
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return OK;
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}
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@ -5133,7 +5130,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
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uint32_t address;
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int i;
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/* At startup the core is in FS mode. */
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/* At start-up the core is in FS mode. */
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/* Disable global interrupts by clearing the GINTMASK bit in the GAHBCFG
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* register; Set the TXFELVL bit in the GAHBCFG register so that TxFIFO
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@ -5204,7 +5201,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
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up_mdelay(50);
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/* Initialize device mode */
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/* Restart the Phy Clock */
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/* Restart the PHY Clock */
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stm32_putreg(0, STM32_OTGFS_PCGCCTL);
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@ -5215,7 +5212,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
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regval |= OTGFS_DCFG_PFIVL_80PCT;
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stm32_putreg(regval, STM32_OTGFS_DCFG);
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/* Set full speed phy */
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/* Set full speed PHY */
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regval = stm32_getreg(STM32_OTGFS_DCFG);
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regval &= ~OTGFS_DCFG_DSPD_MASK;
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@ -5637,6 +5634,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
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flags = irqsave();
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stm32_usbreset(priv);
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irqrestore(flags);
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/* Unbind the class driver */
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@ -5644,6 +5642,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
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/* Disable USB controller interrupts */
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flags = irqsave();
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up_disable_irq(STM32_IRQ_OTGFS);
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/* Disconnect device */
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