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risc-v/mpfs: Add MSSIO GPIO pinmap configuration

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Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This commit is contained in:
Jukka Laitinen 2021-12-01 15:42:13 +02:00 committed by Xiang Xiao
parent 2de22980e5
commit 3beecbe905
9 changed files with 216 additions and 8 deletions
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27
arch/risc-v/src/mpfs/Kconfig
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@ -5,6 +5,33 @@
comment "Polarfire Configuration Options"
choice
prompt "MPFS Chip Selection"
default ARCH_CHIP_MPFS250T_FCVG484
depends on ARCH_CHIP_MPFS
config ARCH_CHIP_MPFS250T_FCVG484
bool "MPFS250T_FCVG484"
---help---
MPFS250T 484, 19x19x0.8 mm package
config CONFIG_ARCH_CHIP_MPFS250T_FCG484
bool "MPFS250T_FCG484"
---help---
MPFS250T 484, 23x23x1 mm package
config CONFIG_ARCH_CHIP_MPFS250T_FCSG325
bool "MPFS250T_FCSG325"
---help---
MPFS250T 325, 11x11 / 11x14.5, 0.5 mm package
config CONFIG_ARCH_CHIP_MPFS250T_FCSG536
bool "MPFS250T_FCSG536"
---help---
MPFS250T 536, 16x16x0.5 mm package
endchoice # MPFS Chip Selection
config MPFS_ENABLE_DPFPU
bool "MPFS DP_FPU Support"
default n

135
arch/risc-v/src/mpfs/hardware/mpfs250t_484_pinmap.h Normal file
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@ -0,0 +1,135 @@
/****************************************************************************
* arch/risc-v/src/mpfs/hardware/mpfs250t_484_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS250T_PINMAP_H
#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS250T_PINMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IO Mux setting for each IO pad */
#define MSSIO_AF_SDIO (0x0 << GPIO_AF_SHIFT)
#define MSSIO_AF_EMMC (0x1 << GPIO_AF_SHIFT)
#define MSSIO_AF_QSPI (0x2 << GPIO_AF_SHIFT)
#define MSSIO_AF_SPI (0x3 << GPIO_AF_SHIFT)
#define MSSIO_AF_USB (0x4 << GPIO_AF_SHIFT)
#define MSSIO_AF_MMUART (0x5 << GPIO_AF_SHIFT)
#define MSSIO_AF_I2C (0x6 << GPIO_AF_SHIFT)
#define MSSIO_AF_CAN (0x7 << GPIO_AF_SHIFT)
#define MSSIO_AF_MDIO (0x8 << GPIO_AF_SHIFT)
#define MSSIO_AF_MISC (0x9 << GPIO_AF_SHIFT)
#define MSSIO_AF_RSVD (0xA << GPIO_AF_SHIFT)
#define MSSIO_AF_GPIO (0xB << GPIO_AF_SHIFT)
#define MSSIO_AF_FABRIC_TEST (0xC << GPIO_AF_SHIFT)
#define MSSIO_AF_LOW (0xD << GPIO_AF_SHIFT)
#define MSSIO_AF_HIGH (0xE << GPIO_AF_SHIFT)
#define MSSIO_AF_TRISTATE (0xF << GPIO_AF_SHIFT)
/* Each 32-bit register has 2 16-bit configurations for consecutive pins */
#define MSSIO_IO_CFG_CR_SHIFT(pin) (pin & 1 ? 16 : 0)
#define MSSIO_IO_CFG_CR_MASK(pin) (0xFFFF << MSSIO_IO_CFG_CR_SHIFT(pin))
/* First offset register of the bank + (pin / 2) * 4 */
#define MSSIO_IO_CFG_BANK0_CR_OFFSET(pin) (0x00000234 + ((pin >> 1) * 4))
#define MSSIO_IO_CFG_BANK1_CR_OFFSET(pin) (0x00000254 + ((pin >> 1) * 4))
#define MSSIO_IO_CFG_CR(bank, pin) (MPFS_SYSREG_BASE + \
(bank == 0 ? \
MSSIO_IO_CFG_BANK0_CR_OFFSET(pin) : \
MSSIO_IO_CFG_BANK1_CR_OFFSET(pin)))
/* Each 32-bit register has 8 4-bit configurations for consecutive pins */
#define MSSIO_MUX_SHIFT(pin) ((pin & 7) * 4)
#define MSSIO_MUX_MASK(pin) (0xF << MSSIO_MUX_SHIFT(pin))
/* First offset register of the bank + pin / 8 * 4 */
#define MSSIO_MUX_BANK0_REG_OFFSET(pin) (MPFS_SYSREG_IOMUX1_CR_OFFSET + \
(pin >> 3) * 4)
#define MSSIO_MUX_BANK1_REG_OFFSET(pin) (MPFS_SYSREG_IOMUX3_CR_OFFSET + \
(pin >> 3) * 4)
#define MSSIO_MUX_BANK_REG_OFFSET(bank,pin) (bank == 0 ? \
MSSIO_MUX_BANK0_REG_OFFSET(pin) : \
MSSIO_MUX_BANK1_REG_OFFSET(pin))
#define MSSIO_MUX_BANK_REG(bank,pin) (MPFS_SYSREG_BASE + \
MSSIO_MUX_BANK_REG_OFFSET(bank,pin))
/* Default EC configuration for all GPIOS */
#define MSSIO_EC_DEFAULT (0x0428 << GPIO_EC_SHIFT)
/* Basic GPIO definitions for MSSIO */
#if defined(CONFIG_ARCH_CHIP_MPFS250T_FCVG484) || defined(CONFIG_ARCH_CHIP_MPFS250T_FCG484)
/* MSSIO GPIO BANK 0 */
#define MSSIO_GPIO_PAD0_J1 (GPIO_BANK0 | GPIO_PIN0 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD1_K5 (GPIO_BANK0 | GPIO_PIN1 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD2_H1 (GPIO_BANK0 | GPIO_PIN2 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD3_J4 (GPIO_BANK0 | GPIO_PIN3 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD4_K4 (GPIO_BANK0 | GPIO_PIN4 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD5_J7 (GPIO_BANK0 | GPIO_PIN5 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD6_K3 (GPIO_BANK0 | GPIO_PIN6 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD7_H4 (GPIO_BANK0 | GPIO_PIN7 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD8_J6 (GPIO_BANK0 | GPIO_PIN8 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD9_H6 (GPIO_BANK0 | GPIO_PIN9 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD10_J3 (GPIO_BANK0 | GPIO_PIN10 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD11_H2 (GPIO_BANK0 | GPIO_PIN11 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD12_H5 (GPIO_BANK0 | GPIO_PIN12 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD13_J2 (GPIO_BANK0 | GPIO_PIN13 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
/* MSSIO GPIO BANK 1 */
#define MSSIO_GPIO_PAD14_G2 (GPIO_BANK1 | GPIO_PIN0 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD15_F1 (GPIO_BANK1 | GPIO_PIN1 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD16_G5 (GPIO_BANK1 | GPIO_PIN2 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD17_G4 (GPIO_BANK1 | GPIO_PIN3 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD18_F2 (GPIO_BANK1 | GPIO_PIN4 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD19_E1 (GPIO_BANK1 | GPIO_PIN5 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD20_G3 (GPIO_BANK1 | GPIO_PIN6 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD21_F5 (GPIO_BANK1 | GPIO_PIN7 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD22_D1 (GPIO_BANK1 | GPIO_PIN8 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD23_D2 (GPIO_BANK1 | GPIO_PIN9 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD24_F6 (GPIO_BANK1 | GPIO_PIN10 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD25_F3 (GPIO_BANK1 | GPIO_PIN11 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD26_C1 (GPIO_BANK1 | GPIO_PIN12 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD27_B1 (GPIO_BANK1 | GPIO_PIN13 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD28_D3 (GPIO_BANK1 | GPIO_PIN14 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD29_C2 (GPIO_BANK1 | GPIO_PIN15 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD30_E5 (GPIO_BANK1 | GPIO_PIN16 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD31_E4 (GPIO_BANK1 | GPIO_PIN17 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD32_B2 (GPIO_BANK1 | GPIO_PIN18 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD33_A2 (GPIO_BANK1 | GPIO_PIN19 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD34_B3 (GPIO_BANK1 | GPIO_PIN20 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD35_A3 (GPIO_BANK1 | GPIO_PIN21 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD36_E3 (GPIO_BANK1 | GPIO_PIN22 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#define MSSIO_GPIO_PAD37_D4 (GPIO_BANK1 | GPIO_PIN23 | MSSIO_AF_GPIO | MSSIO_EC_DEFAULT)
#endif
#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS250T_PINMAP_H */

6
arch/risc-v/src/mpfs/hardware/mpfs_gpio.h
View File

@ -28,6 +28,12 @@
#include <nuttx/config.h>
#include "hardware/mpfs_memorymap.h"
#if defined(CONFIG_ARCH_CHIP_MPFS250T_FCVG484) || defined(CONFIG_ARCH_CHIP_MPFS250T_FCG484)
#include "hardware/mpfs250t_484_pinmap.h"
#else
#error The selected MPFS variant is not impelemented
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/

21
arch/risc-v/src/mpfs/mpfs_gpio.c
View File

@ -63,6 +63,8 @@ int mpfs_configgpio(gpio_pinset_t cfgset)
uint8_t pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
uint8_t bank = (cfgset & GPIO_BANK_MASK) >> GPIO_BANK_SHIFT;
uint8_t irq_mode = (cfgset & GPIO_IRQ_MASK) >> GPIO_IRQ_SHIFT;
uint8_t mux = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
uint16_t ec = (cfgset & GPIO_EC_MASK) >> GPIO_EC_SHIFT;
if (bank == 3)
{
@ -75,6 +77,25 @@ int mpfs_configgpio(gpio_pinset_t cfgset)
* bank2 0 - 31
*/
if (bank == 0 || bank == 1)
{
/* Mux the relevant GPIO to IO PAD */
baseaddr = MPFS_SYSREG_BASE + MSSIO_MUX_BANK_REG_OFFSET(bank, pin);
modifyreg32(baseaddr, MSSIO_MUX_MASK(pin),
mux << MSSIO_MUX_SHIFT(pin));
/* Set EC configuration for MSSIO pin */
baseaddr = MSSIO_IO_CFG_CR(bank, pin);
modifyreg32(baseaddr, MSSIO_IO_CFG_CR_MASK(pin),
ec << MSSIO_IO_CFG_CR_SHIFT(pin));
}
else
{
/* TODO: Always enable to fabric */
}
baseaddr = g_gpio_base[bank] + (pin * sizeof(uint32_t));
if (cfgset & GPIO_INPUT)

29
arch/risc-v/src/mpfs/mpfs_gpio.h
View File

@ -55,6 +55,7 @@
* - Input with irq level low
* - Input with irq edge positive
* - Input with irq edge negative
* - Alternate Function IO (pad) mux
*
* 16-bit Encoding: 1111 1100 0000 0000
* 5432 1098 7654 3210
@ -70,11 +71,27 @@
* MM.. .... .... ....
*/
#define GPIO_MODE_SHIFT (14) /* Bit 14-15: IO Mode */
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
# define GPIO_NOINOUT (0 << GPIO_MODE_SHIFT) /* No input or output */
# define GPIO_INPUT (1 << GPIO_MODE_SHIFT) /* Input Enable */
# define GPIO_OUTPUT (2 << GPIO_MODE_SHIFT) /* Output Enable */
#define GPIO_EC_SHIFT (20) /* Bits 20-31 Electrical Configuration */
#define GPIO_EC_MASK (0xFFF << GPIO_EC_SHIFT)
#define GPIO_EC_PUPD_SHIFT (30) /* Bit 30-31 Electrical Configuration PUPD */
#define GPIO_EC_PUPD_MASK (3 << GPIO_EC_PUPD_SHIFT)
#define GPIO_EC_LOCKDN_SHIFT (29) /* Bit 29 Electrical Configuration Lockdn */
#define GPIO_EC_LOCKDN_MASK (1 << GPIO_EC_LOCKDN_SHIFT)
#define GPIO_EC_ENHYST_SHIFT (28) /* Bit 28 Electrical Configuration Hyst */
#define GPIO_EC_ENHYST_MASK (1 << GPIO_EC_ENHYST_SHIFT)
#define GPIO_CLAMP_SHIFT (27) /* Bit 27 Electrical Configuration Clamp */
#define GPIO_EC_CLAMP_MASK (1 << GPIO_CLAMP_SHIFT)
#define GPIO_EC_DRVSTR_SHIFT (23) /* Bit 23-26 Electrical Configuration drive strength */
#define GPIO_EC_DRVSTR_MASK (0xF << GPIO_EC_SHIFT)
#define GPIO_EC_BUFM_SHIFT (20) /* Bit 20-22 Electrical Configuration Buffer Mode*/
#define GPIO_EC_BUFM_MASK (0x7 << GPIO_EC_BUFM_SHIFT)
#define GPIO_AF_SHIFT (16) /* Bit 16-19 Alternate Function */
#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT)
#define GPIO_MODE_SHIFT (14) /* Bit 14-15: IO Mode */
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
# define GPIO_NOINOUT (0 << GPIO_MODE_SHIFT) /* No input or output */
# define GPIO_INPUT (1 << GPIO_MODE_SHIFT) /* Input Enable */
# define GPIO_OUTPUT (2 << GPIO_MODE_SHIFT) /* Output Enable */
/* Output buffer:
*
@ -170,7 +187,7 @@
/* The smallest integer type that can hold the GPIO encoding */
typedef uint16_t gpio_pinset_t;
typedef uint32_t gpio_pinset_t;
/****************************************************************************
* Public Data

1
boards/risc-v/mpfs/icicle/configs/hwtest/defconfig
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@ -14,6 +14,7 @@ CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="icicle"
CONFIG_ARCH_BOARD_ICICLE_MPFS=y
CONFIG_ARCH_CHIP="mpfs"
CONFIG_ARCH_CHIP_MPFS250T_FCVG484=y
CONFIG_ARCH_CHIP_MPFS=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_RISCV=y

1
boards/risc-v/mpfs/icicle/configs/nsh/defconfig
View File

@ -12,6 +12,7 @@ CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="icicle"
CONFIG_ARCH_BOARD_ICICLE_MPFS=y
CONFIG_ARCH_CHIP="mpfs"
CONFIG_ARCH_CHIP_MPFS250T_FCVG484=y
CONFIG_ARCH_CHIP_MPFS=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_RISCV=y

3
boards/risc-v/mpfs/icicle/configs/opensbi/defconfig
View File

@ -12,6 +12,7 @@ CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="icicle"
CONFIG_ARCH_BOARD_ICICLE_MPFS=y
CONFIG_ARCH_CHIP="mpfs"
CONFIG_ARCH_CHIP_MPFS250T_FCVG484=y
CONFIG_ARCH_CHIP_MPFS=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_RISCV=y
@ -74,7 +75,6 @@ CONFIG_NSH_DISABLE_MKDIR=y
CONFIG_NSH_DISABLE_MKRD=y
CONFIG_NSH_DISABLE_MOUNT=y
CONFIG_NSH_DISABLE_MV=y
CONFIG_NSH_DISABLE_PRINTF=y
CONFIG_NSH_DISABLE_PS=y
CONFIG_NSH_DISABLE_PUT=y
CONFIG_NSH_DISABLE_PWD=y
@ -86,7 +86,6 @@ CONFIG_NSH_DISABLE_SOURCE=y
CONFIG_NSH_DISABLE_TELNETD=y
CONFIG_NSH_DISABLE_TEST=y
CONFIG_NSH_DISABLE_TIME=y
CONFIG_NSH_DISABLE_TRUNCATE=y
CONFIG_NSH_DISABLE_UMOUNT=y
CONFIG_NSH_DISABLE_UNAME=y
CONFIG_NSH_DISABLE_UNSET=y

1
boards/risc-v/mpfs/m100pfsevp/configs/nsh/defconfig
View File

@ -12,6 +12,7 @@ CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="icicle"
CONFIG_ARCH_BOARD_ICICLE_MPFS=y
CONFIG_ARCH_CHIP="mpfs"
CONFIG_ARCH_CHIP_MPFS250T_FCVG484=y
CONFIG_ARCH_CHIP_MPFS=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_RISCV=y