diff --git a/arch/arm/src/samd/chip/sam_i2c.h b/arch/arm/src/samd/chip/sam_i2c.h new file mode 100644 index 0000000000..0ab8b7796a --- /dev/null +++ b/arch/arm/src/samd/chip/sam_i2c.h @@ -0,0 +1,235 @@ +/******************************************************************************************** + * arch/arm/src/samd/chip/sam_usart.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMD_CHIP_SAM_I2C_H +#define __ARCH_ARM_SRC_SAMD_CHIP_SAM_I2C_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_sercom.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ +/* I2C register offsets *********************************************************************/ + +#define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */ +#define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */ +#define SAM_I2C_BAUD_OFFSET 0x000a /* Baud register */ +#define SAM_I2C_DBGCTRL_OFFSET 0x0008 /* Debug control register */ +#define SAM_I2C_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */ +#define SAM_I2C_INTENSET_OFFSET 0x000d /* Interrupt enable set register */ +#define SAM_I2C_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */ +#define SAM_I2C_STATUS_OFFSET 0x0010 /* Status register */ +#define SAM_I2C_ADDR_OFFSET 0x0014 /* Address register */ +#define SAM_I2C_DATA_OFFSET 0x0018 /* Data register */ + +/* I2C register addresses *******************************************************************/ + +#define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE+SAM_I2C_CTRLA_OFFSET) +#define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE+SAM_I2C_CTRLB_OFFSET) +#define SAM_I2C0_BAUD (SAM_SERCOM0_BASE+SAM_I2C_BAUD_OFFSET) +#define SAM_I2C0_DBGCTRL (SAM_SERCOM0_BASE+SAM_I2C_DBGCTRL_OFFSET) +#define SAM_I2C0_INTENCLR (SAM_SERCOM0_BASE+SAM_I2C_INTENCLR_OFFSET) +#define SAM_I2C0_INTENSET (SAM_SERCOM0_BASE+SAM_I2C_INTENSET_OFFSET) +#define SAM_I2C0_INTFLAG (SAM_SERCOM0_BASE+SAM_I2C_INTFLAG_OFFSET) +#define SAM_I2C0_STATUS (SAM_SERCOM0_BASE+SAM_I2C_STATUS_OFFSET) +#define SAM_I2C0_ADDR (SAM_SERCOM0_BASE+SAM_I2C_ADDR_OFFSET) +#define SAM_I2C0_DATA (SAM_SERCOM0_BASE+SAM_I2C_DATA_OFFSET) + +#define SAM_I2C1_CTRLA (SAM_SERCOM1_BASE+SAM_I2C_CTRLA_OFFSET) +#define SAM_I2C1_CTRLB (SAM_SERCOM1_BASE+SAM_I2C_CTRLB_OFFSET) +#define SAM_I2C1_BAUD (SAM_SERCOM1_BASE+SAM_I2C_BAUD_OFFSET) +#define SAM_I2C1_DBGCTRL (SAM_SERCOM1_BASE+SAM_I2C_DBGCTRL_OFFSET) +#define SAM_I2C1_INTENCLR (SAM_SERCOM1_BASE+SAM_I2C_INTENCLR_OFFSET) +#define SAM_I2C1_INTENSET (SAM_SERCOM1_BASE+SAM_I2C_INTENSET_OFFSET) +#define SAM_I2C1_INTFLAG (SAM_SERCOM1_BASE+SAM_I2C_INTFLAG_OFFSET) +#define SAM_I2C1_STATUS (SAM_SERCOM1_BASE+SAM_I2C_STATUS_OFFSET) +#define SAM_I2C1_ADDR (SAM_SERCOM1_BASE+SAM_I2C_ADDR_OFFSET) +#define SAM_I2C1_DATA (SAM_SERCOM1_BASE+SAM_I2C_DATA_OFFSET) + +#define SAM_I2C2_CTRLA (SAM_SERCOM2_BASE+SAM_I2C_CTRLA_OFFSET) +#define SAM_I2C2_CTRLB (SAM_SERCOM2_BASE+SAM_I2C_CTRLB_OFFSET) +#define SAM_I2C2_BAUD (SAM_SERCOM2_BASE+SAM_I2C_BAUD_OFFSET) +#define SAM_I2C2_DBGCTRL (SAM_SERCOM2_BASE+SAM_I2C_DBGCTRL_OFFSET) +#define SAM_I2C2_INTENCLR (SAM_SERCOM2_BASE+SAM_I2C_INTENCLR_OFFSET) +#define SAM_I2C2_INTENSET (SAM_SERCOM2_BASE+SAM_I2C_INTENSET_OFFSET) +#define SAM_I2C2_INTFLAG (SAM_SERCOM2_BASE+SAM_I2C_INTFLAG_OFFSET) +#define SAM_I2C2_STATUS (SAM_SERCOM2_BASE+SAM_I2C_STATUS_OFFSET) +#define SAM_I2C2_ADDR (SAM_SERCOM2_BASE+SAM_I2C_ADDR_OFFSET) +#define SAM_I2C2_DATA (SAM_SERCOM2_BASE+SAM_I2C_DATA_OFFSET) + +#define SAM_I2C3_CTRLA (SAM_SERCOM3_BASE+SAM_I2C_CTRLA_OFFSET) +#define SAM_I2C3_CTRLB (SAM_SERCOM3_BASE+SAM_I2C_CTRLB_OFFSET) +#define SAM_I2C3_BAUD (SAM_SERCOM3_BASE+SAM_I2C_BAUD_OFFSET) +#define SAM_I2C3_DBGCTRL (SAM_SERCOM3_BASE+SAM_I2C_DBGCTRL_OFFSET) +#define SAM_I2C3_INTENCLR (SAM_SERCOM3_BASE+SAM_I2C_INTENCLR_OFFSET) +#define SAM_I2C3_INTENSET (SAM_SERCOM3_BASE+SAM_I2C_INTENSET_OFFSET) +#define SAM_I2C3_INTFLAG (SAM_SERCOM3_BASE+SAM_I2C_INTFLAG_OFFSET) +#define SAM_I2C3_STATUS (SAM_SERCOM3_BASE+SAM_I2C_STATUS_OFFSET) +#define SAM_I2C3_ADDR (SAM_SERCOM3_BASE+SAM_I2C_ADDR_OFFSET) +#define SAM_I2C3_DATA (SAM_SERCOM3_BASE+SAM_I2C_DATA_OFFSET) + +#define SAM_I2C4_CTRLA (SAM_SERCOM4_BASE+SAM_I2C_CTRLA_OFFSET) +#define SAM_I2C4_CTRLB (SAM_SERCOM4_BASE+SAM_I2C_CTRLB_OFFSET) +#define SAM_I2C4_BAUD (SAM_SERCOM4_BASE+SAM_I2C_BAUD_OFFSET) +#define SAM_I2C4_DBGCTRL (SAM_SERCOM4_BASE+SAM_I2C_DBGCTRL_OFFSET) +#define SAM_I2C4_INTENCLR (SAM_SERCOM4_BASE+SAM_I2C_INTENCLR_OFFSET) +#define SAM_I2C4_INTENSET (SAM_SERCOM4_BASE+SAM_I2C_INTENSET_OFFSET) +#define SAM_I2C4_INTFLAG (SAM_SERCOM4_BASE+SAM_I2C_INTFLAG_OFFSET) +#define SAM_I2C4_STATUS (SAM_SERCOM4_BASE+SAM_I2C_STATUS_OFFSET) +#define SAM_I2C4_ADDR (SAM_SERCOM4_BASE+SAM_I2C_ADDR_OFFSET) +#define SAM_I2C4_DATA (SAM_SERCOM4_BASE+SAM_I2C_DATA_OFFSET) + +#define SAM_I2C5_CTRLA (SAM_SERCOM5_BASE+SAM_I2C_CTRLA_OFFSET) +#define SAM_I2C5_CTRLB (SAM_SERCOM5_BASE+SAM_I2C_CTRLB_OFFSET) +#define SAM_I2C5_BAUD (SAM_SERCOM5_BASE+SAM_I2C_BAUD_OFFSET) +#define SAM_I2C5_DBGCTRL (SAM_SERCOM5_BASE+SAM_I2C_DBGCTRL_OFFSET) +#define SAM_I2C5_INTENCLR (SAM_SERCOM5_BASE+SAM_I2C_INTENCLR_OFFSET) +#define SAM_I2C5_INTENSET (SAM_SERCOM5_BASE+SAM_I2C_INTENSET_OFFSET) +#define SAM_I2C5_INTFLAG (SAM_SERCOM5_BASE+SAM_I2C_INTFLAG_OFFSET) +#define SAM_I2C5_STATUS (SAM_SERCOM5_BASE+SAM_I2C_STATUS_OFFSET) +#define SAM_I2C5_ADDR (SAM_SERCOM5_BASE+SAM_I2C_ADDR_OFFSET) +#define SAM_I2C5_DATA (SAM_SERCOM5_BASE+SAM_I2C_DATA_OFFSET) + +/* I2C register bit definitions *************************************************************/ + +/* Control A register */ + +#define I2C_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */ +#define I2C_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */ +#define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */ +#define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT) +# define I2C_CTRLA_MODE_MASTER (5 << I2C_CTRLA_MODE_SHIFT) /* I2C master mode */ +#define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ +#define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Transmit data pinout */ +# define I2C_CTRLA_1WIRE (0) /* 4-wire operation disable */ +# define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enable */ +#define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */ +#define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT) +# define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */ +# define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */ +# define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */ +# define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */ +#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */ +#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT) +# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */ +# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */ +# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */ +# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */ +Value Name +#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */ + +/* Control B register */ + +#define I2C_CTRLB_SMEN (1 << 8) /* Bit 8: Smart Mode Enable */ +#define I2C_CTRLB_QCEN (1 << 9) /* Bit 9: Quick Command Enable */ +#define I2C_CTRLB_CMD_SHIFT (16) /* Bits 16-17: Command */ +#define I2C_CTRLB_CMD_MASK (3 << I2C_CTRLB_CMD_SHIFT) +# define I2C_CTRLB_CMD_NOACTION (0 << I2C_CTRLB_CMD_SHIFT) /* No action */ +# define I2C_CTRLB_CMD_ACKREP (1 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by repeated START */ +# define I2C_CTRLB_CMD_ACKREAD (2 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by read operation */ +# define I2C_CTRLB_CMD_ACKSTOP (3 << I2C_CTRLB_CMD_SHIFT) /* ACK follwed by STOP */ +#define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */ +# define I2C_CTRLB_ACK (0) /* Send ACK */ +# define I2C_CTRLB_NCK I2C_CTRLB_ACKACT /* Send NACK */ + +/* Debug control register */ + +#define I2C_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */ + +/* Baud register (16-bit baud value) */ + +#define I2C_BAUD_SHIFT (0) /* Bits 0-7: Master Baud Rate */ +#define I2C_BAUD_MASK (0xff << I2C_BAUD_SHIFT) +# define I2C_BAUD(n) ((uint16)(n) << I2C_BAUD_SHIFT) +#define I2C_BAUDLOW_SHIFT (8) /* Bits 8-15: Master Baud Rate Low */ +#define I2C_BAUDLOW_MASK (0xff << I2C_BAUDLOW_SHIFT) +# define I2C_BAUDLOW(n) (uint16)(n) << I2C_BAUDLOW_SHIFT) + +/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and + * status clear registers. + */ + +#define I2C_INT_MB (1 << 0) /* Bit 0: Master on Bus Interrupt Enable */ +#define I2C_INT_SB (1 << 1) /* Bit 1: Slave on Bus Interrupt Enable */ + +#define I2C_INT_ALL (0x03) + +/* Status register */ + +#define I2C_STATUS_BUSERR (1 << 0) /* Bit 0: Bus Error */ +#define I2C_STATUS_FARBLOST (1 << 1) /* Bit 1: Arbitration Lost */ +#define I2C_STATUS_RXNACK (1 << 2) /* Bit 2: Received Not Acknowledge */ +#define I2C_STATUS_BUSSTATE_SHIFT (4) /* Bits 4-5: Bus State */ +#define I2C_STATUS_BUSSTATE_MASK (3 << I2C_STATUS_BUSSTATE_SHIFT) +# define I2C_STATUS_BUSSTATE_UNKNOWN (0 << I2C_STATUS_BUSSTATE_SHIFT) /* Unknown to master */ +# define I2C_STATUS_BUSSTATE_IDLE (1 << I2C_STATUS_BUSSTATE_SHIFT) /* Waiting for transaction */ +# define I2C_STATUS_BUSSTATE_OWNER (2 << I2C_STATUS_BUSSTATE_SHIFT) /* Master of bus owner */ +# define I2C_STATUS_BUSSTATE_BUSY (3 << I2C_STATUS_BUSSTATE_SHIFT) /* Other master owns */ +#define I2C_STATUS_LOWTOUT (1 << 6) /* Bit 6: SCL Low Time-Out */ +#define I2C_STATUS_CLKHOLD (1 << 7) /* Bit 7: Clock Hold */ +#define I2C_STATUS_SYNCBUSY (1 << 15) /* Bit 15: Synchronization busy */ + +/* Address register */ + +#define I2C_ADDR_MASK (0xff) /* Bits 0-7: Address */ + +/* Data register */ + +#define I2C_DATA_MASK (0xff) /* Bits 0-7: Data */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAMD_CHIP_SAM_I2C_H */ diff --git a/arch/arm/src/samd/chip/sam_spi.h b/arch/arm/src/samd/chip/sam_spi.h new file mode 100644 index 0000000000..e8477efc3f --- /dev/null +++ b/arch/arm/src/samd/chip/sam_spi.h @@ -0,0 +1,230 @@ +/******************************************************************************************** + * arch/arm/src/samd/chip/sam_spi.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMD_CHIP_SAM_SPI_H +#define __ARCH_ARM_SRC_SAMD_CHIP_SAM_SPI_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/sam_sercom.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ +/* SPI register offsets *********************************************************************/ + +#define SAM_SPI_CTRLA_OFFSET 0x0000 /* Control A register */ +#define SAM_SPI_CTRLB_OFFSET 0x0004 /* Control B register */ +#define SAM_SPI_DBGCTRL_OFFSET 0x0008 /* Debug control register */ +#define SAM_SPI_BAUD_OFFSET 0x000a /* Baud register */ +#define SAM_SPI_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */ +#define SAM_SPI_INTENSET_OFFSET 0x000d /* Interrupt enable set register */ +#define SAM_SPI_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */ +#define SAM_SPI_STATUS_OFFSET 0x0010 /* Status register */ +#define SAM_SPI_ADDR_OFFSET 0x0014 /* Address register */ +#define SAM_SPI_DATA_OFFSET 0x0018 /* Data register */ + +/* SPI register addresses *******************************************************************/ + +#define SAM_SPI0_CTRLA (SAM_SERCOM0_BASE+SAM_SPI_CTRLA_OFFSET) +#define SAM_SPI0_CTRLB (SAM_SERCOM0_BASE+SAM_SPI_CTRLB_OFFSET) +#define SAM_SPI0_DBGCTRL (SAM_SERCOM0_BASE+SAM_SPI_DBGCTRL_OFFSET) +#define SAM_SPI0_BAUD (SAM_SERCOM0_BASE+SAM_SPI_BAUD_OFFSET) +#define SAM_SPI0_INTENCLR (SAM_SERCOM0_BASE+SAM_SPI_INTENCLR_OFFSET) +#define SAM_SPI0_INTENSET (SAM_SERCOM0_BASE+SAM_SPI_INTENSET_OFFSET) +#define SAM_SPI0_INTFLAG (SAM_SERCOM0_BASE+SAM_SPI_INTFLAG_OFFSET) +#define SAM_SPI0_STATUS (SAM_SERCOM0_BASE+SAM_SPI_STATUS_OFFSET) +#define SAM_SPI0_ADDR (SAM_SERCOM0_BASE+SAM_SPI_ADDR_OFFSET) +#define SAM_SPI0_DATA (SAM_SERCOM0_BASE+SAM_SPI_DATA_OFFSET) + +#define SAM_SPI1_CTRLA (SAM_SERCOM1_BASE+SAM_SPI_CTRLA_OFFSET) +#define SAM_SPI1_CTRLB (SAM_SERCOM1_BASE+SAM_SPI_CTRLB_OFFSET) +#define SAM_SPI1_DBGCTRL (SAM_SERCOM1_BASE+SAM_SPI_DBGCTRL_OFFSET) +#define SAM_SPI1_BAUD (SAM_SERCOM1_BASE+SAM_SPI_BAUD_OFFSET) +#define SAM_SPI1_INTENCLR (SAM_SERCOM1_BASE+SAM_SPI_INTENCLR_OFFSET) +#define SAM_SPI1_INTENSET (SAM_SERCOM1_BASE+SAM_SPI_INTENSET_OFFSET) +#define SAM_SPI1_INTFLAG (SAM_SERCOM1_BASE+SAM_SPI_INTFLAG_OFFSET) +#define SAM_SPI1_STATUS (SAM_SERCOM1_BASE+SAM_SPI_STATUS_OFFSET) +#define SAM_SPI1_ADDR (SAM_SERCOM1_BASE+SAM_SPI_ADDR_OFFSET) +#define SAM_SPI1_DATA (SAM_SERCOM1_BASE+SAM_SPI_DATA_OFFSET) + +#define SAM_SPI2_CTRLA (SAM_SERCOM2_BASE+SAM_SPI_CTRLA_OFFSET) +#define SAM_SPI2_CTRLB (SAM_SERCOM2_BASE+SAM_SPI_CTRLB_OFFSET) +#define SAM_SPI2_DBGCTRL (SAM_SERCOM2_BASE+SAM_SPI_DBGCTRL_OFFSET) +#define SAM_SPI2_BAUD (SAM_SERCOM2_BASE+SAM_SPI_BAUD_OFFSET) +#define SAM_SPI2_INTENCLR (SAM_SERCOM2_BASE+SAM_SPI_INTENCLR_OFFSET) +#define SAM_SPI2_INTENSET (SAM_SERCOM2_BASE+SAM_SPI_INTENSET_OFFSET) +#define SAM_SPI2_INTFLAG (SAM_SERCOM2_BASE+SAM_SPI_INTFLAG_OFFSET) +#define SAM_SPI2_STATUS (SAM_SERCOM2_BASE+SAM_SPI_STATUS_OFFSET) +#define SAM_SPI2_ADDR (SAM_SERCOM2_BASE+SAM_SPI_ADDR_OFFSET) +#define SAM_SPI2_DATA (SAM_SERCOM2_BASE+SAM_SPI_DATA_OFFSET) + +#define SAM_SPI3_CTRLA (SAM_SERCOM3_BASE+SAM_SPI_CTRLA_OFFSET) +#define SAM_SPI3_CTRLB (SAM_SERCOM3_BASE+SAM_SPI_CTRLB_OFFSET) +#define SAM_SPI3_DBGCTRL (SAM_SERCOM3_BASE+SAM_SPI_DBGCTRL_OFFSET) +#define SAM_SPI3_BAUD (SAM_SERCOM3_BASE+SAM_SPI_BAUD_OFFSET) +#define SAM_SPI3_INTENCLR (SAM_SERCOM3_BASE+SAM_SPI_INTENCLR_OFFSET) +#define SAM_SPI3_INTENSET (SAM_SERCOM3_BASE+SAM_SPI_INTENSET_OFFSET) +#define SAM_SPI3_INTFLAG (SAM_SERCOM3_BASE+SAM_SPI_INTFLAG_OFFSET) +#define SAM_SPI3_STATUS (SAM_SERCOM3_BASE+SAM_SPI_STATUS_OFFSET) +#define SAM_SPI3_ADDR (SAM_SERCOM3_BASE+SAM_SPI_ADDR_OFFSET) +#define SAM_SPI3_DATA (SAM_SERCOM3_BASE+SAM_SPI_DATA_OFFSET) + +#define SAM_SPI4_CTRLA (SAM_SERCOM4_BASE+SAM_SPI_CTRLA_OFFSET) +#define SAM_SPI4_CTRLB (SAM_SERCOM4_BASE+SAM_SPI_CTRLB_OFFSET) +#define SAM_SPI4_DBGCTRL (SAM_SERCOM4_BASE+SAM_SPI_DBGCTRL_OFFSET) +#define SAM_SPI4_BAUD (SAM_SERCOM4_BASE+SAM_SPI_BAUD_OFFSET) +#define SAM_SPI4_INTENCLR (SAM_SERCOM4_BASE+SAM_SPI_INTENCLR_OFFSET) +#define SAM_SPI4_INTENSET (SAM_SERCOM4_BASE+SAM_SPI_INTENSET_OFFSET) +#define SAM_SPI4_INTFLAG (SAM_SERCOM4_BASE+SAM_SPI_INTFLAG_OFFSET) +#define SAM_SPI4_STATUS (SAM_SERCOM4_BASE+SAM_SPI_STATUS_OFFSET) +#define SAM_SPI4_ADDR (SAM_SERCOM4_BASE+SAM_SPI_ADDR_OFFSET) +#define SAM_SPI4_DATA (SAM_SERCOM4_BASE+SAM_SPI_DATA_OFFSET) + +#define SAM_SPI5_CTRLA (SAM_SERCOM5_BASE+SAM_SPI_CTRLA_OFFSET) +#define SAM_SPI5_CTRLB (SAM_SERCOM5_BASE+SAM_SPI_CTRLB_OFFSET) +#define SAM_SPI5_DBGCTRL (SAM_SERCOM5_BASE+SAM_SPI_DBGCTRL_OFFSET) +#define SAM_SPI5_BAUD (SAM_SERCOM5_BASE+SAM_SPI_BAUD_OFFSET) +#define SAM_SPI5_INTENCLR (SAM_SERCOM5_BASE+SAM_SPI_INTENCLR_OFFSET) +#define SAM_SPI5_INTENSET (SAM_SERCOM5_BASE+SAM_SPI_INTENSET_OFFSET) +#define SAM_SPI5_INTFLAG (SAM_SERCOM5_BASE+SAM_SPI_INTFLAG_OFFSET) +#define SAM_SPI5_STATUS (SAM_SERCOM5_BASE+SAM_SPI_STATUS_OFFSET) +#define SAM_SPI5_ADDR (SAM_SERCOM5_BASE+SAM_SPI_ADDR_OFFSET) +#define SAM_SPI5_DATA (SAM_SERCOM5_BASE+SAM_SPI_DATA_OFFSET) + +/* SPI register bit definitions *************************************************************/ + +/* Control A register */ + +#define SPI_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */ +#define SPI_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */ +#define SPI_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */ +#define SPI_CTRLA_MODE_MASK (7 << SPI_CTRLA_MODE_SHIFT) +# define SPI_CTRLA_MODE_SLAVE (2 << SPI_CTRLA_MODE_SHIFT) /* SPI slave operation */ +# define SPI_CTRLA_MODE_MASTER (3 << SPI_CTRLA_MODE_SHIFT) /* SPI master operation */ +#define SPI_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ +#define SPI_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */ +#define SPI_CTRLA_DOPO (1 << 16) /* Bit 16: Data out pinout */ +# define SPI_CTRLA_DOPAD0 (0) +# define SPI_CTRLA_DOPAD2 SPI_CTRLA_DOPO +#define SPI_CTRLA_DIPO_SHIFT (20) /* Bits 20-21: Data in pinout */ +#define SPI_CTRLA_DIPO_MASK (3 << SPI_CTRLA_DIPO_SHIFT) +# define SPI_CTRLA_DIPAD0 (0 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD[0] for DI */ +# define SPI_CTRLA_DIPAD1 (1 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD[1] for DI */ +# define SPI_CTRLA_DIPAD2 (2 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD[2] for DI */ +# define SPI_CTRLA_DIPAD3 (3 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD[3] for DI */ +#define SPI_CTRLA_FORM_SHIFT (24) /* Bits 24-27: Frame format */ +#define SPI_CTRLA_FORM_MASK (7 << SPI_CTRLA_FORM_SHIFT) +# define SPI_CTRLA_FORM_SPI (0 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (no address) */ +# define SPI_CTRLA_FORM_ADDR (2 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (w/address) */ +#define SPI_CTRLA_CMODE (1 << 28) /* Bit 28: Communication mode */ +# define SPI_CTRLA_ASYNCH (0) +# define SPI_CTRLA_SYNCH SPI_CTRLA_CMODE +#define SPI_CTRLA_CPHA (1 << 28) /* Bit 28: Clock phase */ +#define SPI_CTRLA_CPOL (1 << 29) /* Bit 29: Clock polarity */ +#define SPI_CTRLA_DORD (1 << 30) /* Bit 30: Data order */ +# define SPI_CTRLA_MSBFIRST (0) +# define SPI_CTRLA_LSBFIRST SPI_CTRLA_DORD + +/* Control B register */ + +#define SPI_CTRLB_CHSIZE_SHIFT (0) /* Bits 0-2: Character Size */ +#define SPI_CTRLB_CHSIZE_MASK (7 << SPI_CTRLB_CHSIZE_SHIFT) +# define SPI_CTRLB_CHSIZE_8BITS (0 << SPI_CTRLB_CHSIZE_SHIFT) /* 8 bits */ +# define SPI_CTRLB_CHSIZE_9BITS (1 << SPI_CTRLB_CHSIZE_SHIFT) /* 9 bits */ +#define SPI_CTRLB_PLOADEN (1 << 6) /* Bit 6: Slave Data Preload Enable */ +#define SPI_CRLB_AMODE_SHIFT (14) /* Bits 14-15: Address Mode */ +#define SPI_CRLB_AMODE_MASK (3 << SPI_CRLB_AMODE_SHIFT) +# define SPI_CRLB_AMODE_MASK (0 << SPI_CRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */ +# define SPI_CRLB_AMODE_2ADDRS (1 << SPI_CRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */ +# define SPI_CRLB_AMODE_RANGE (2 << SPI_CRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */ +#define SPI_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */ + +/* Debug control register */ + +#define SPI_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */ + +/* Baud register (8-bit baud value) */ + +/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and + * status clear registers. + */ + +#define SPI_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */ +#define SPI_INT_TXC (1 << 1) /* Bit 1: Transmit complete interrupt */ +#define SPI_INT_RXC (1 << 2) /* Bit 2: Receive complete interrupt */ +# +#define SPI_INT_ALL (0x07) + +/* Status register */ + +#define SPI_STATUS_BUFOVF (1 << 2) /* Bit 2: Buffer overflow */ +#define SPI_STATUS_SYNCBUSY (1 << 15) /* Bit 15: Synchronization busy */ + +/* Address register */ + +#define SPI_ADDR_SHIFT (0) /* Bits 0-7: Address */ +#define SPI_ADDR_MASK (0xff << SPI_ADDR_SHIFT) +# define SPI_ADDR(n) ((uint32_t)(n) << SPI_ADDR_SHIFT) +#define SPI_ADDRMASK_SHIFT (16) /* Bits 16-23: Address Mask */ +#define SPI_ADDRMASK_MASK (0xff << SPI_ADDRMASK_SHIFT) +# define SPI_ADDRMASK(n) (uint32_t)(n) << SPI_ADDRMASK_SHIFT) + +/* Data register */ + +#define SPI_DATA_MASK (0x1ff) /* Bits 0-8: Data */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAMD_CHIP_SAM_SPI_H */ diff --git a/arch/arm/src/samd/chip/sam_usart.h b/arch/arm/src/samd/chip/sam_usart.h index 03539d0dc6..990e9513a0 100644 --- a/arch/arm/src/samd/chip/sam_usart.h +++ b/arch/arm/src/samd/chip/sam_usart.h @@ -55,14 +55,14 @@ /* USART register offsets *******************************************************************/ #define SAM_USART_CTRLA_OFFSET 0x0000 /* Control A register */ -#define SAM_USART_CTRLB_OFFSET 0x0000 /* Control B register */ -#define SAM_USART_DBGCTRL_OFFSET 0x0000 /* Debug control register */ -#define SAM_USART_BAUD_OFFSET 0x0000 /* Baud register */ -#define SAM_USART_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear register */ -#define SAM_USART_INTENSET_OFFSET 0x0000 /* Interrupt enable set register */ -#define SAM_USART_INTFLAG_OFFSET 0x0000 /* Interrupt flag and status clear register */ -#define SAM_USART_STATUS_OFFSET 0x0000 /* Status register */ -#define SAM_USART_DATA_OFFSET 0x0000 /* Data register */ +#define SAM_USART_CTRLB_OFFSET 0x0004 /* Control B register */ +#define SAM_USART_DBGCTRL_OFFSET 0x0008 /* Debug control register */ +#define SAM_USART_BAUD_OFFSET 0x000a /* Baud register */ +#define SAM_USART_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */ +#define SAM_USART_INTENSET_OFFSET 0x000d /* Interrupt enable set register */ +#define SAM_USART_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */ +#define SAM_USART_STATUS_OFFSET 0x0010 /* Status register */ +#define SAM_USART_DATA_OFFSET 0x0018 /* Data register */ /* USART register addresses *****************************************************************/ @@ -137,7 +137,7 @@ # define USART_CTRLA_MODE_EXTUSART (0 << USART_CTRLA_MODE_SHIFT) /* USART with external clock */ # define USART_CTRLA_MODE_INTUSART (1 << USART_CTRLA_MODE_SHIFT) /* USART with internal clock */ #define USART_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ -#define USART_CTRLA_IBON (1 << 8) /* Bit 8: Immediate buffer overflow notification */ +#define USART_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */ #define USART_CTRLA_TXPO (1 << 16) /* Bit 16: Transmit data pinout */ # define USART_CTRLA_TXPAD0 (0) # define USART_CTRLA_TXPAD2 USART_CTRLA_TXPO @@ -170,15 +170,15 @@ # define USART_CTRLB_CHSIZE_5BITS (5 << USART_CTRLB_CHSIZE_SHIFT) /* 5 bits */ # define USART_CTRLB_CHSIZE_6BITS (6 << USART_CTRLB_CHSIZE_SHIFT) /* 6 bits */ # define USART_CTRLB_CHSIZE_7BITS (7 << USART_CTRLB_CHSIZE_SHIFT) /* 7 bits */ -#define USART_CTRLB_SBMODE (1 << 6) /* Bit 6: Stop bit mode */ +#define USART_CTRLB_SBMODE (1 << 6) /* Bit 6: Stop bit mode */ # define USART_CTRLB_SBMODE_1 (0) # define USART_CTRLB_SBMODE_2 USART_CTRLB_SBMODE -#define USART_CTRLB_SFDE (1 << 9) /* Bit 9: Start of frame detection enable */ -#define USART_CTRLB_PMODE (1 << 13) /* Bit 13: Parity mode */ +#define USART_CTRLB_SFDE (1 << 9) /* Bit 9: Start of frame detection enable */ +#define USART_CTRLB_PMODE (1 << 13) /* Bit 13: Parity mode */ # define USART_CTRLB_PEVEN (0) # define USART_CTRLB_PODD USART_CTRLB_PMODE -#define USART_CTRLB_TXEN (1 << 16) /* Bit 16: Transmitter enable */ -#define USART_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */ +#define USART_CTRLB_TXEN (1 << 16) /* Bit 16: Transmitter enable */ +#define USART_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */ /* Debug control register */