arch/arm: Remove g_irqtmp, g_undeftmp and g_aborttmp
to avoid multiple CPU access them concurrently in SMP case Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao
Masayuki Ishikawa
parent
822bb3ff78
commit
3c30c8b90b
@ -39,25 +39,6 @@
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* Private Data
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****************************************************************************/
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.data
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g_irqtmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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g_undeftmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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g_aborttmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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#ifdef CONFIG_ARMV7A_DECODEFIQ
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g_fiqtmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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#endif
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/****************************************************************************
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* Assembly Macros
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****************************************************************************/
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@ -134,21 +115,12 @@ arm_vectorirq:
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* and r14.
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*/
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ldr r13, .Lirqtmp
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sub lr, lr, #4
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str lr, [r13] /* Save lr_IRQ */
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mrs lr, spsr
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str lr, [r13, #4] /* Save spsr_IRQ */
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/* Then switch back to SVC mode */
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bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
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#ifdef CONFIG_ARMV7A_DECODEFIQ
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orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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mov r13, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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#else
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orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
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mov r13, #(PSR_MODE_SVC | PSR_I_BIT)
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#endif
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msr cpsr_c, lr /* Switch to SVC mode */
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msr cpsr_c, r13 /* Switch to SVC mode */
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/* Create a context structure. First set aside a stack frame
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* and store r0-r12 into the frame.
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@ -157,10 +129,26 @@ arm_vectorirq:
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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#ifdef CONFIG_ARMV7A_DECODEFIQ
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mov r0, #(PSR_MODE_IRQ | PSR_I_BIT | PSR_F_BIT)
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#else
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mov r0, #(PSR_MODE_IRQ | PSR_I_BIT)
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#endif
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msr cpsr_c, r0 /* Switch back IRQ mode */
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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ldr r0, .Lirqtmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r3=lr_IRQ, r4=spsr_IRQ */
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sub r3, lr, #4
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mrs r4, spsr
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/* Then switch back to SVC mode */
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#ifdef CONFIG_ARMV7A_DECODEFIQ
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orr r0, r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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#else
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orr r0, r0, #(PSR_MODE_SVC | PSR_I_BIT)
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#endif
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msr cpsr_c, r0
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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@ -268,17 +256,14 @@ arm_vectorirq:
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ldmia r0, {r0-r15}^ /* Return */
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.Lirqtmp:
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.word g_irqtmp
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#if CONFIG_ARCH_INTERRUPTSTACK > 7
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#ifndef CONFIG_SMP
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.Lirqstackbase:
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.word g_intstackbase
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#endif
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#endif /* CONFIG_ARCH_INTERRUPTSTACK > 7 */
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.size arm_vectorirq, . - arm_vectorirq
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.align 5
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/****************************************************************************
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@ -400,7 +385,6 @@ arm_vectorsvc:
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/* Life is simple when everything is SVC mode */
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ldmia r0, {r0-r15}^ /* Return */
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.size arm_vectorsvc, . - arm_vectorsvc
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.align 5
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@ -425,17 +409,8 @@ arm_vectordata:
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* r13 and r14
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*/
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ldr r13, .Ldaborttmp /* Points to temp storage */
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sub lr, lr, #8 /* Fixup return */
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str lr, [r13] /* Save in temp storage */
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mrs lr, spsr /* Get SPSR */
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str lr, [r13, #4] /* Save in temp storage */
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/* Then switch back to SVC mode */
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bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
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orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, lr /* Switch to SVC mode */
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mov r13, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r13 /* Switch to SVC mode */
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/* Create a context structure. First set aside a stack frame
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* and store r0-r12 into the frame.
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@ -444,10 +419,18 @@ arm_vectordata:
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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mov r0, #(PSR_MODE_ABT | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r0 /* Switch back ABT mode */
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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ldr r0, .Ldaborttmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r3=lr_ABT, r4=spsr_ABT */
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sub r3, lr, #8
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mrs r4, spsr
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/* Then switch back to SVC mode */
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mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r0
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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@ -544,9 +527,6 @@ arm_vectordata:
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/* Life is simple when everything is SVC mode */
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ldmia r0, {r1-r15}^ /* Return */
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.Ldaborttmp:
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.word g_aborttmp
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.size arm_vectordata, . - arm_vectordata
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.align 5
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@ -571,17 +551,8 @@ arm_vectorprefetch:
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* r13 and r14
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*/
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ldr r13, .Lpaborttmp /* Points to temp storage */
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sub lr, lr, #4 /* Fixup return */
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str lr, [r13] /* Save in temp storage */
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mrs lr, spsr /* Get SPSR */
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str lr, [r13, #4] /* Save in temp storage */
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/* Then switch back to SVC mode */
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bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
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orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, lr /* Switch to SVC mode */
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mov r13, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r13 /* Switch to SVC mode */
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/* Create a context structure. First set aside a stack frame
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* and store r0-r12 into the frame.
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@ -590,10 +561,18 @@ arm_vectorprefetch:
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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mov r0, #(PSR_MODE_ABT | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r0 /* Switch back ABT mode */
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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ldr r0, .Lpaborttmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r3=lr_ABT, r4=spsr_ABT */
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sub r3, lr, #4
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mrs r4, spsr
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/* Then switch back to SVC mode */
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mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r0
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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@ -690,9 +669,6 @@ arm_vectorprefetch:
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/* Life is simple when everything is SVC mode */
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ldmia r0, {r0-r15}^ /* Return */
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.Lpaborttmp:
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.word g_aborttmp
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.size arm_vectorprefetch, . - arm_vectorprefetch
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.align 5
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@ -715,16 +691,8 @@ arm_vectorundefinsn:
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* r13 and r14
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*/
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ldr r13, .Lundeftmp /* Points to temp storage */
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str lr, [r13] /* Save in temp storage */
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mrs lr, spsr /* Get SPSR */
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str lr, [r13, #4] /* Save in temp storage */
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/* Then switch back to SVC mode */
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bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
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orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, lr /* Switch to SVC mode */
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mov r13, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r13 /* Switch to SVC mode */
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/* Create a context structure. First set aside a stack frame
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* and store r0-r12 into the frame.
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@ -733,10 +701,18 @@ arm_vectorundefinsn:
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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mov r0, #(PSR_MODE_UND | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r0 /* Switch back UND mode */
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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ldr r0, .Lundeftmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r3=lr_UND, r4=spsr_UND */
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mov r3, lr
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mrs r4, spsr
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/* Then switch back to SVC mode */
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mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r0
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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@ -831,9 +807,6 @@ arm_vectorundefinsn:
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/* Life is simple when everything is SVC mode */
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ldmia r0, {r0-r15}^ /* Return */
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.Lundeftmp:
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.word g_undeftmp
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.size arm_vectorundefinsn, . - arm_vectorundefinsn
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.align 5
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@ -857,17 +830,8 @@ arm_vectorfiq:
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#ifdef CONFIG_ARMV7A_DECODEFIQ
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/* On entry we are free to use the FIQ mode registers r8 through r14 */
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ldr r13, .Lfiqtmp /* Points to temp storage */
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sub lr, lr, #4 /* Fixup return */
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str lr, [r13] /* Save in temp storage */
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mrs lr, spsr /* Get SPSR_fiq */
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str lr, [r13, #4] /* Save in temp storage */
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/* Then switch back to SVC mode */
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bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
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orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, lr /* Switch to SVC mode */
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mov r13, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r13 /* Switch to SVC mode */
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/* Create a context structure. First set aside a stack frame
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* and store r0-r12 into the frame.
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@ -876,10 +840,18 @@ arm_vectorfiq:
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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mov r0, #(PSR_MODE_FIQ | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r0 /* Switch back FIQ mode */
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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ldr r0, .Lfiqtmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r3=lr_SVC, r4=spsr_SVC */
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sub r3, lr, #4
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mrs r4, spsr
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/* Then switch back to SVC mode */
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mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r0
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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@ -983,9 +955,6 @@ arm_vectorfiq:
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ldmia r0, {r0-r15}^ /* Return */
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.Lfiqtmp:
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.word g_fiqtmp
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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.Lfiqstackbase:
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.word g_fiqstackbase
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@ -38,25 +38,6 @@
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* Private Data
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****************************************************************************/
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.data
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g_irqtmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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g_undeftmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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g_aborttmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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#ifdef CONFIG_ARMV7R_DECODEFIQ
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g_fiqtmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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#endif
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/****************************************************************************
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* Assembly Macros
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****************************************************************************/
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@ -88,21 +69,12 @@ arm_vectorirq:
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* and r14.
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*/
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ldr r13, .Lirqtmp
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sub lr, lr, #4
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str lr, [r13] /* Save lr_IRQ */
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mrs lr, spsr
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str lr, [r13, #4] /* Save spsr_IRQ */
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/* Then switch back to SVC mode */
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bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
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#ifdef CONFIG_ARMV7R_DECODEFIQ
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orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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#ifdef CONFIG_ARMV7A_DECODEFIQ
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mov r13, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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#else
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orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
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mov r13, #(PSR_MODE_SVC | PSR_I_BIT)
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#endif
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msr cpsr_c, lr /* Switch to SVC mode */
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msr cpsr_c, r13 /* Switch to SVC mode */
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/* Create a context structure. First set aside a stack frame
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* and store r0-r12 into the frame.
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@ -111,10 +83,26 @@ arm_vectorirq:
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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#ifdef CONFIG_ARMV7A_DECODEFIQ
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mov r0, #(PSR_MODE_IRQ | PSR_I_BIT | PSR_F_BIT)
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#else
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mov r0, #(PSR_MODE_IRQ | PSR_I_BIT)
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#endif
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msr cpsr_c, r0 /* Switch back IRQ mode */
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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ldr r0, .Lirqtmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r3=lr_IRQ, r4=spsr_IRQ */
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sub r3, lr, #4
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mrs r4, spsr
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/* Then switch back to SVC mode */
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#ifdef CONFIG_ARMV7A_DECODEFIQ
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orr r0, r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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#else
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orr r0, r0, #(PSR_MODE_SVC | PSR_I_BIT)
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#endif
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msr cpsr_c, r0
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#ifdef CONFIG_BUILD_PROTECTED
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/* Did we enter from user mode? If so then we need get the values of
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@ -222,15 +210,12 @@ arm_vectorirq:
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ldmia r0, {r0-r15}^ /* Return */
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.Lirqtmp:
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.word g_irqtmp
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#if CONFIG_ARCH_INTERRUPTSTACK > 7
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.Lirqstackbase:
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.word g_intstackbase
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#endif
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.size arm_vectorirq, . - arm_vectorirq
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.align 5
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/****************************************************************************
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@ -352,7 +337,6 @@ arm_vectorsvc:
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/* Life is simple when everything is SVC mode */
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ldmia r0, {r0-r15}^ /* Return */
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.size arm_vectorsvc, . - arm_vectorsvc
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.align 5
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@ -377,17 +361,8 @@ arm_vectordata:
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* r13 and r14
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*/
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ldr r13, .Ldaborttmp /* Points to temp storage */
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sub lr, lr, #8 /* Fixup return */
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str lr, [r13] /* Save in temp storage */
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mrs lr, spsr /* Get SPSR */
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str lr, [r13, #4] /* Save in temp storage */
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/* Then switch back to SVC mode */
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bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
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orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, lr /* Switch to SVC mode */
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mov r13, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r13 /* Switch to SVC mode */
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/* Create a context structure. First set aside a stack frame
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* and store r0-r12 into the frame.
|
||||
@ -396,10 +371,18 @@ arm_vectordata:
|
||||
sub sp, sp, #XCPTCONTEXT_SIZE
|
||||
stmia sp, {r0-r12} /* Save the SVC mode regs */
|
||||
|
||||
mov r0, #(PSR_MODE_ABT | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r0 /* Switch back ABT mode */
|
||||
|
||||
/* Get the values for r15(pc) and CPSR in r3 and r4 */
|
||||
|
||||
ldr r0, .Ldaborttmp /* Points to temp storage */
|
||||
ldmia r0, {r3, r4} /* Recover r3=lr_ABT, r4=spsr_ABT */
|
||||
sub r3, lr, #8
|
||||
mrs r4, spsr
|
||||
|
||||
/* Then switch back to SVC mode */
|
||||
|
||||
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r0
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Did we enter from user mode? If so then we need get the values of
|
||||
@ -496,9 +479,6 @@ arm_vectordata:
|
||||
/* Life is simple when everything is SVC mode */
|
||||
|
||||
ldmia r0, {r1-r15}^ /* Return */
|
||||
|
||||
.Ldaborttmp:
|
||||
.word g_aborttmp
|
||||
.size arm_vectordata, . - arm_vectordata
|
||||
|
||||
.align 5
|
||||
@ -523,17 +503,8 @@ arm_vectorprefetch:
|
||||
* r13 and r14
|
||||
*/
|
||||
|
||||
ldr r13, .Lpaborttmp /* Points to temp storage */
|
||||
sub lr, lr, #4 /* Fixup return */
|
||||
str lr, [r13] /* Save in temp storage */
|
||||
mrs lr, spsr /* Get SPSR */
|
||||
str lr, [r13, #4] /* Save in temp storage */
|
||||
|
||||
/* Then switch back to SVC mode */
|
||||
|
||||
bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
|
||||
orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, lr /* Switch to SVC mode */
|
||||
mov r13, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r13 /* Switch to SVC mode */
|
||||
|
||||
/* Create a context structure. First set aside a stack frame
|
||||
* and store r0-r12 into the frame.
|
||||
@ -542,10 +513,18 @@ arm_vectorprefetch:
|
||||
sub sp, sp, #XCPTCONTEXT_SIZE
|
||||
stmia sp, {r0-r12} /* Save the SVC mode regs */
|
||||
|
||||
mov r0, #(PSR_MODE_ABT | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r0 /* Switch back ABT mode */
|
||||
|
||||
/* Get the values for r15(pc) and CPSR in r3 and r4 */
|
||||
|
||||
ldr r0, .Lpaborttmp /* Points to temp storage */
|
||||
ldmia r0, {r3, r4} /* Recover r3=lr_ABT, r4=spsr_ABT */
|
||||
sub r3, lr, #4
|
||||
mrs r4, spsr
|
||||
|
||||
/* Then switch back to SVC mode */
|
||||
|
||||
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r0
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Did we enter from user mode? If so then we need get the values of
|
||||
@ -642,9 +621,6 @@ arm_vectorprefetch:
|
||||
/* Life is simple when everything is SVC mode */
|
||||
|
||||
ldmia r0, {r0-r15}^ /* Return */
|
||||
|
||||
.Lpaborttmp:
|
||||
.word g_aborttmp
|
||||
.size arm_vectorprefetch, . - arm_vectorprefetch
|
||||
|
||||
.align 5
|
||||
@ -667,16 +643,8 @@ arm_vectorundefinsn:
|
||||
* r13 and r14
|
||||
*/
|
||||
|
||||
ldr r13, .Lundeftmp /* Points to temp storage */
|
||||
str lr, [r13] /* Save in temp storage */
|
||||
mrs lr, spsr /* Get SPSR */
|
||||
str lr, [r13, #4] /* Save in temp storage */
|
||||
|
||||
/* Then switch back to SVC mode */
|
||||
|
||||
bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
|
||||
orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, lr /* Switch to SVC mode */
|
||||
mov r13, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r13 /* Switch to SVC mode */
|
||||
|
||||
/* Create a context structure. First set aside a stack frame
|
||||
* and store r0-r12 into the frame.
|
||||
@ -685,10 +653,18 @@ arm_vectorundefinsn:
|
||||
sub sp, sp, #XCPTCONTEXT_SIZE
|
||||
stmia sp, {r0-r12} /* Save the SVC mode regs */
|
||||
|
||||
mov r0, #(PSR_MODE_UND | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r0 /* Switch back UND mode */
|
||||
|
||||
/* Get the values for r15(pc) and CPSR in r3 and r4 */
|
||||
|
||||
ldr r0, .Lundeftmp /* Points to temp storage */
|
||||
ldmia r0, {r3, r4} /* Recover r3=lr_UND, r4=spsr_UND */
|
||||
mov r3, lr
|
||||
mrs r4, spsr
|
||||
|
||||
/* Then switch back to SVC mode */
|
||||
|
||||
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r0
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Did we enter from user mode? If so then we need get the values of
|
||||
@ -783,9 +759,6 @@ arm_vectorundefinsn:
|
||||
/* Life is simple when everything is SVC mode */
|
||||
|
||||
ldmia r0, {r0-r15}^ /* Return */
|
||||
|
||||
.Lundeftmp:
|
||||
.word g_undeftmp
|
||||
.size arm_vectorundefinsn, . - arm_vectorundefinsn
|
||||
|
||||
.align 5
|
||||
@ -809,17 +782,8 @@ arm_vectorfiq:
|
||||
#ifdef CONFIG_ARMV7R_DECODEFIQ
|
||||
/* On entry we are free to use the FIQ mode registers r8 through r14 */
|
||||
|
||||
ldr r13, .Lfiqtmp /* Points to temp storage */
|
||||
sub lr, lr, #4 /* Fixup return */
|
||||
str lr, [r13] /* Save in temp storage */
|
||||
mrs lr, spsr /* Get SPSR_fiq */
|
||||
str lr, [r13, #4] /* Save in temp storage */
|
||||
|
||||
/* Then switch back to SVC mode */
|
||||
|
||||
bic lr, lr, #PSR_MODE_MASK /* Keep F and T bits */
|
||||
orr lr, lr, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, lr /* Switch to SVC mode */
|
||||
mov r13, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r13 /* Switch to SVC mode */
|
||||
|
||||
/* Create a context structure. First set aside a stack frame
|
||||
* and store r0-r12 into the frame.
|
||||
@ -828,10 +792,18 @@ arm_vectorfiq:
|
||||
sub sp, sp, #XCPTCONTEXT_SIZE
|
||||
stmia sp, {r0-r12} /* Save the SVC mode regs */
|
||||
|
||||
mov r0, #(PSR_MODE_FIQ | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r0 /* Switch back FIQ mode */
|
||||
|
||||
/* Get the values for r15(pc) and CPSR in r3 and r4 */
|
||||
|
||||
ldr r0, .Lfiqtmp /* Points to temp storage */
|
||||
ldmia r0, {r3, r4} /* Recover r3=lr_SVC, r4=spsr_SVC */
|
||||
sub r3, lr, #4
|
||||
mrs r4, spsr
|
||||
|
||||
/* Then switch back to SVC mode */
|
||||
|
||||
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r0
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Did we enter from user mode? If so then we need get the values of
|
||||
@ -935,9 +907,6 @@ arm_vectorfiq:
|
||||
|
||||
ldmia r0, {r0-r15}^ /* Return */
|
||||
|
||||
.Lfiqtmp:
|
||||
.word g_fiqtmp
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
.Lfiqstackbase:
|
||||
.word g_fiqstackbase
|
||||
|
||||
Loading…
Reference in New Issue
Block a user