Changes for a clean build of configs/sam4s-xplained
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@ -76,14 +76,14 @@
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/* USB UTMI PLL start-up time */
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#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
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#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
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/* Resulting frequencies */
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#define SAM_MAINOSC_FREQUENCY (12000000)
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#define SAM_MCK_FREQUENCY (48000000)
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#define SAM_PLLA_FREQUENCY (96000000)
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#define SAM_CPU_FREQUENCY (48000000)
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#define BOARD_MAINOSC_FREQUENCY (12000000)
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#define BOARD_MCK_FREQUENCY (48000000)
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#define BOARD_PLLA_FREQUENCY (96000000)
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#define BOARD_CPU_FREQUENCY (48000000)
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/* HSMCI clocking
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*
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@ -7,7 +7,8 @@ README
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The SAM4S Xplained features:
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- 12MHz crystal (no 32.768KHz crystal)S
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- 120 MHz Cortex-M4 with MPU
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- 12MHz crystal (no 32.768KHz crystal)
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- Segger J-Link JTAG emulator on-board for program and debug
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- MICRO USB A/B connector for USB connectivity
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- IS66WV51216DBLL ISSI SRAM 8Mb 512K x 16 55ns PSRAM 2.5v-3.6v
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@ -72,35 +72,37 @@
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/* Clocking *************************************************************************/
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/* After power-on reset, the sam3u device is running on a 4MHz internal RC. These
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* definitions will configure clocking with MCK = 48MHz, PLLA = 96, and CPU=48MHz.
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* definitions will configure clocking with MCK = 48MHz, PLLA = 96, and CPU=120MHz.
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*/
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/* Main oscillator register settings */
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#define BOARD_CKGR_MOR_MOSCXTST (63 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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/* PLLA configuration */
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/* PLLA configuration:
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*
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* Source: 12MHz crystall at 12MHz
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* PLLdiv: 10
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* PLLmul: 1 (bypassed)
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* Fpll: (12MHz * 10) / 1 = 120MHz
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*/
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#define BOARD_CKGR_PLLAR_MUL (7 << PMC_CKGR_PLLAR_MUL_SHIFT)
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#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST
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#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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#define BOARD_MAINOSC_FREQUENCY (12000000)
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#define BOARD_CKGR_PLLAR_MUL (9 << PMC_CKGR_PLLAR_MUL_SHIFT)
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#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
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#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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#define BOARD_PLLA_FREQUENCY (10*BOARD_MAINOSC_FREQUENCY)
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/* PMC master clock register settings */
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1
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#define BOARD_MCK_FREQUENCY (BOARD_PLLA_FREQUENCY/1)
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#define BOARD_CPU_FREQUENCY (BOARD_PLLA_FREQUENCY/1)
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/* USB UTMI PLL start-up time */
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#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
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/* Resulting frequencies */
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#define SAM_MAINOSC_FREQUENCY (12000000)
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#define SAM_MCK_FREQUENCY (48000000)
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#define SAM_PLLA_FREQUENCY (96000000)
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#define SAM_CPU_FREQUENCY (48000000)
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#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
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/* HSMCI clocking
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*
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@ -193,7 +193,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
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CONFIG_BOARD_LOOPSPERMSEC=4768
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# CONFIG_ARCH_CALIBRATION is not set
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CONFIG_DRAM_START=0x20000000
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CONFIG_DRAM_SIZE=32768
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CONFIG_DRAM_SIZE=131072
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CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
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CONFIG_ARCH_INTERRUPTSTACK=0
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@ -87,10 +87,10 @@
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*/
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#define GPIO_D9 (GPIO_OUTPUT | GPIO_PULL_UP | GPIO_OUTPUT_SET | \
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GPIO_PORTC | GPIO_PIN10)
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#define GPIO_D10 (GPIO_OUTPUT | GPIO_PULL_UP | GPIO_OUTPUT_SET | \
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GPIO_PORTC | GPIO_PIN17)
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#define GPIO_D9 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \
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GPIO_PORT_PIOC | GPIO_PIN10)
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#define GPIO_D10 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \
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GPIO_PORT_PIOC | GPIO_PIN17)
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/* Mechanical buttons:
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*
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@ -101,9 +101,9 @@
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* PA5 BP2
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*/
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#define GPIO_BP2 (GPIO_INPUT | GPIO_PULL_UP | GPIO_GLITCH_FILTER | \
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GPIO_PORTA | GPIO_PIN5)
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#define IRQ_BP2 SAM_IRQ_PA5
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#define GPIO_BP2 (GPIO_INPUT | GPIO_CFG_PULLUP | GPIO_CFG_DEGLITCH | \
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GPIO_PORT_PIOA | GPIO_PIN5)
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#define IRQ_BP2 SAM_IRQ_PA5
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/************************************************************************************
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* Public Types
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@ -46,7 +46,7 @@
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#include <arch/board/board.h>
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#include "chip.h"
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#include "sam_gpip.h"
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#include "sam_gpio.h"
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#include "sam4s-xplained.h"
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#ifdef CONFIG_ARCH_LEDS
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