sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Standardization of some naming in preparation for a large automated change

Browse Source
This commit is contained in:
Gregory Nutt 2016-02-13 12:57:09 -06:00
parent a884818e32
commit 3caffdd82e
6 changed files with 44 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/src/efm32/efm32_flash.c
View File

@ -636,7 +636,7 @@ ssize_t __ramfunc__ up_progmem_erasepage(size_t page)
int ret = 0;
int timeout;
uint32_t regval;
irqstate_t irqs;
irqstate_t flags;
if (page >= (EFM32_FLASH_NPAGES+EFM32_USERDATA_NPAGES))
{
@ -645,7 +645,7 @@ ssize_t __ramfunc__ up_progmem_erasepage(size_t page)
efm32_flash_unlock();
irqs = irqsave();
flags = irqsave();
/* enable writing to the flash */
@ -706,7 +706,7 @@ ssize_t __ramfunc__ up_progmem_erasepage(size_t page)
}
}
irqrestore(irqs);
irqrestore(flags);
if (ret != 0)
{
@ -787,7 +787,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
{
int page_bytes;
ssize_t page_idx;
irqstate_t irqs;
irqstate_t flags;
/* Compute the number of words to write to the current page. */
@ -813,7 +813,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
page_words = num_words - word_count;
}
irqs = irqsave();
flags = irqsave();
/* First we load address. The address is auto-incremented within a page.
* Therefore the address phase is only needed once for each page.
@ -828,7 +828,7 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size)
ret = msc_load_write_data(p_data, page_words, true);
}
irqrestore(irqs);
irqrestore(flags);
if (ret != 0)
{

14
arch/arm/src/efm32/efm32_i2c.c
View File

@ -1734,7 +1734,7 @@ out:
FAR struct i2c_master_s *efm32_i2cbus_initialize(int port)
{
struct efm32_i2c_priv_s *priv = NULL;
irqstate_t irqs;
irqstate_t flags;
/* Get I2C private structure */
@ -1760,7 +1760,7 @@ FAR struct i2c_master_s *efm32_i2cbus_initialize(int port)
* power-up hardware and configure GPIOs.
*/
irqs = irqsave();
flags = irqsave();
if ((volatile int)priv->refs++ == 0)
{
@ -1768,7 +1768,7 @@ FAR struct i2c_master_s *efm32_i2cbus_initialize(int port)
efm32_i2c_init(priv);
}
irqrestore(irqs);
irqrestore(flags);
return (struct i2c_master_s *)priv;
}
@ -1783,7 +1783,7 @@ FAR struct i2c_master_s *efm32_i2cbus_initialize(int port)
int efm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
{
FAR struct efm32_i2c_priv_s *priv = (struct efm32_i2c_priv_s *)dev;
irqstate_t irqs;
irqstate_t flags;
ASSERT(dev);
@ -1794,15 +1794,15 @@ int efm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
return ERROR;
}
irqs = irqsave();
flags = irqsave();
if (--priv->refs)
{
irqrestore(irqs);
irqrestore(flags);
return OK;
}
irqrestore(irqs);
irqrestore(flags);
/* Disable power and other HW resource (GPIO's) */

18
arch/arm/src/stm32/stm32_i2c.c
View File

@ -1287,7 +1287,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
*/
#ifdef CONFIG_I2C_POLLED
irqstate_t state = irqsave();
irqstate_t flags = irqsave();
#endif
/* Receive a byte */
@ -1302,7 +1302,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
}
#ifdef CONFIG_I2C_POLLED
irqrestore(state);
irqrestore(flags);
#endif
}
else
@ -1944,7 +1944,7 @@ out:
FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
{
struct stm32_i2c_priv_s * priv = NULL;
int irqs;
irqstate_t flags;
#if STM32_PCLK1_FREQUENCY < 4000000
# warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
@ -1982,7 +1982,7 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
* power-up hardware and configure GPIOs.
*/
irqs = irqsave();
flags = irqsave();
if ((volatile int)priv->refs++ == 0)
{
@ -1990,7 +1990,7 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
stm32_i2c_init(priv);
}
irqrestore(irqs);
irqrestore(flags);
return (struct i2c_master_s *)priv;
}
@ -2005,7 +2005,7 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
{
FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev;
int irqs;
irqstate_ flags;
ASSERT(dev);
@ -2016,15 +2016,15 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
return ERROR;
}
irqs = irqsave();
flags = irqsave();
if (--priv->refs)
{
irqrestore(irqs);
irqrestore(flags);
return OK;
}
irqrestore(irqs);
irqrestore(flags);
/* Disable power and other HW resource (GPIO's) */

14
arch/arm/src/stm32/stm32_i2c_alt.c
View File

@ -2389,7 +2389,7 @@ out:
FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
{
struct stm32_i2c_priv_s *priv = NULL;
int irqs;
irqstate_t flags;
#if STM32_PCLK1_FREQUENCY < 4000000
# warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
@ -2427,7 +2427,7 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
* power-up hardware and configure GPIOs.
*/
irqs = irqsave();
flags = irqsave();
if ((volatile int)priv->refs++ == 0)
{
@ -2435,7 +2435,7 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
stm32_i2c_init(priv);
}
irqrestore(irqs);
irqrestore(flags);
return (struct i2c_master_s *)priv;
}
@ -2450,7 +2450,7 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
{
FAR struct stm32_i2c_priv_s *priv = (FAR struct stm32_i2c_priv_s *)dev;
int irqs;
irqstate_t flags;
ASSERT(dev);
@ -2461,15 +2461,15 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
return ERROR;
}
irqs = irqsave();
flags = irqsave();
if (--priv->refs)
{
irqrestore(irqs);
irqrestore(flags);
return OK;
}
irqrestore(irqs);
irqrestore(flags);
/* Disable power and other HW resource (GPIO's) */

18
arch/arm/src/stm32/stm32f30xxx_i2c.c
View File

@ -1346,7 +1346,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
*/
#ifdef CONFIG_I2C_POLLED
irqstate_t state = irqsave();
irqstate_t flags = irqsave();
#endif
/* Receive a byte */
@ -1361,7 +1361,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
}
#ifdef CONFIG_I2C_POLLED
irqrestore(state);
irqrestore(flags);
#endif
}
}
@ -1945,7 +1945,7 @@ out:
FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
{
struct stm32_i2c_priv_s * priv = NULL; /* private data of device with multiple instances */
int irqs;
irqtate_t flags;
#if STM32_PCLK1_FREQUENCY < 4000000
# warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
@ -1983,7 +1983,7 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
* power-up hardware and configure GPIOs.
*/
irqs = irqsave();
flags = irqsave();
if ((volatile int)priv->refs++ == 0)
{
@ -1991,7 +1991,7 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
stm32_i2c_init(priv);
}
irqrestore(irqs);
irqrestore(flags);
return (struct i2c_master_s *)priv;
}
@ -2006,7 +2006,7 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
int stm32_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
{
FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev;
int irqs;
irqstate_t flags;
ASSERT(dev);
@ -2017,15 +2017,15 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
return ERROR;
}
irqs = irqsave();
flags = irqsave();
if (--priv->refs)
{
irqrestore(irqs);
irqrestore(flags);
return OK;
}
irqrestore(irqs);
irqrestore(flags);
/* Disable power and other HW resource (GPIO's) */

12
arch/arm/src/tiva/tiva_i2c.c
View File

@ -2142,7 +2142,7 @@ struct i2c_master_s *tiva_i2cbus_initialize(int port)
{
struct tiva_i2c_priv_s *priv = NULL;
const struct tiva_i2c_config_s *config;
int irqs;
int flags;
i2cvdbg("I2C%d: Initialize\n", port);
@ -2233,7 +2233,7 @@ struct i2c_master_s *tiva_i2cbus_initialize(int port)
* power-up hardware and configure GPIOs.
*/
irqs = irqsave();
flags = irqsave();
priv->refs++;
if (priv->refs == 1)
@ -2248,7 +2248,7 @@ struct i2c_master_s *tiva_i2cbus_initialize(int port)
tiva_i2c_initialize(priv, 100000);
}
irqrestore(irqs);
irqrestore(flags);
return (struct i2c_master_s *)priv;
}
@ -2263,7 +2263,7 @@ struct i2c_master_s *tiva_i2cbus_initialize(int port)
int tiva_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct tiva_i2c_priv_s *priv = (struct tiva_i2c_priv_s *)dev;
int irqs;
int flags;
DEBUGASSERT(priv && priv->config && priv->refs > 0);
@ -2271,7 +2271,7 @@ int tiva_i2cbus_uninitialize(struct i2c_master_s *dev)
/* Decrement reference count and check for underflow */
irqs = irqsave();
flags = irqsave();
/* Check if the reference count will decrement to zero */
@ -2293,7 +2293,7 @@ int tiva_i2cbus_uninitialize(struct i2c_master_s *dev)
priv->refs--;
}
irqrestore(irqs);
irqrestore(flags);
return OK;
}