Add PIM header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2812 42af7a65-404d-4744-a932-0658087f49c3
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/************************************************************************************
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* arch/hc/src/mc9s12ne64/chip.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -74,7 +74,7 @@
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#define HCS12_ATD_BASE 0x0080 /* 0x0080–0x009f: Analog-to-Digital Converter 10-bit, 8-channel (ATD) */
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/* 0x00a0–0x00c7: Reserved */
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#define HCS12_SCI0_BASE 0x00c8 /* 0x00c8–0x00cf: Serial Communications Interface 0 (SCI0) */
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#define HCS12_SCI1_BASE 0x00d0 /* 0x00d0–0x00d7: Serial Communications Interface 1 (SCI1) */
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#define HCS12_SCI1_BASE 0x00d0 /* 0x00d0–0x00d7: Serial Communications Interface 1 (SCI1) */o
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#define HCS12_SPI_BASE 0x00d8 /* 0x00d8–0x00df: Serial Peripheral Interface (SPI) */
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#define HCS12_IIC_BASE 0x00e0 /* 0x00e0–0x00e7: Inter IC Bus (IIC) */
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/* 0x00e8–0x00ff: Reserved */
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/************************************************************************************
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* arch/hc/src/mc9s12ne64/mc9s12ne64_flash.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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226
arch/hc/src/mc9s12ne64/mc9s12ne64_pim.h
Executable file
226
arch/hc/src/mc9s12ne64/mc9s12ne64_pim.h
Executable file
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/************************************************************************************
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* arch/hc/src/mc9s12ne64/mc9s12ne64_pim.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_PIM_H
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#define __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_PIM_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define HCS12_PIM_PORTT_OFFSET (0x0000)
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#define HCS12_PIM_PORTS_OFFSET (0x0008)
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#define HCS12_PIM_PORTG_OFFSET (0x0010)
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#define HCS12_PIM_PORTH_OFFSET (0x0018)
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#define HCS12_PIM_PORTJ_OFFSET (0x0020)
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#define HCS12_PIM_PORTL_OFFSET (0x0028)
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#define HCS12_PIM_IO_OFFSET (0x0000) /* I/O Register (ALL) */
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#define HCS12_PIM_INPUT_OFFSET (0x0001) /* Input Register (ALL) */
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#define HCS12_PIM_DDR_OFFSET (0x0002) /* Data Direction Register (ALL) */
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#define HCS12_PIM_RDR_OFFSET (0x0003) /* Reduced Drive Register (ALL) */
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#define HCS12_PIM_PER_OFFSET (0x0004) /* Pull Device Enable Register (ALL) */
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#define HCS12_PIM_PS_OFFSET (0x0005) /* Polarity Select Register (ALL) */
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#define HCS12_PIM_WOM_OFFSET (0x0006) /* Wired OR Mode Register (PORT S and L) */
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#define HCS12_PIM_IE_OFFSET (0x0006) /* Interrupt Enable Register (PORT G, H, and J) */
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#define HCS12_PIM_IF_OFFSET (0x0007) /* Interrupt Flag Register (PORT G, H, and J) */
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/* Register Addresses ***************************************************************/
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#define PIM_PORTT (0)
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#define PIM_PORTS (1)
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#define PIM_PORTG (2)
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#define PIM_PORTH (3)
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#define PIM_PORTJ (4)
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#define PIM_PORTL (5)
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#define HCS12_PIM_PORT_BASE(n) (HCS12_PIM_BASE + 0x0008*(n))
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#define HCS12_PIM_PORTT_BASE (HCS12_PIM_BASE + HCS12_PIM_PORTT_OFFSET)
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#define HCS12_PIM_PORTS_BASE (HCS12_PIM_BASE + HCS12_PIM_PORTS_OFFSET)
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#define HCS12_PIM_PORTG_BASE (HCS12_PIM_BASE + HCS12_PIM_PORTG_OFFSET)
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#define HCS12_PIM_PORTH_BASE (HCS12_PIM_BASE + HCS12_PIM_PORTH_OFFSET)
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#define HCS12_PIM_PORTJ_BASE (HCS12_PIM_BASE + HCS12_PIM_PORTJ_OFFSET)
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#define HCS12_PIM_PORTL_BASE (HCS12_PIM_BASE + HCS12_PIM_PORTL_OFFSET)
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#define HCS12_PIM_PORT_IO(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_IO_OFFSET)
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#define HCS12_PIM_PORT_INPUT(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_INPUT_OFFSET)
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#define HCS12_PIM_PORT_DDR(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_DDR_OFFSET)
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#define HCS12_PIM_PORT_RDR(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_RDR_OFFSET)
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#define HCS12_PIM_PORT_PER(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_PER_OFFSET)
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#define HCS12_PIM_PORT_PS(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_PS_OFFSET)
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#define HCS12_PIM_PORT_IE(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_IE_OFFSET)
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#define HCS12_PIM_PORT_IF(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_IF_OFFSET)
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#define HCS12_PIM_PORTT_IO (HCS12_PIM_PORTT_BASE + HCS12_PIM_IO_OFFSET)
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#define HCS12_PIM_PORTT_INPUT (HCS12_PIM_PORTT_BASE + HCS12_PIM_INPUT_OFFSET)
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#define HCS12_PIM_PORTT_DDR (HCS12_PIM_PORTT_BASE + HCS12_PIM_DDR_OFFSET)
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#define HCS12_PIM_PORTT_RDR (HCS12_PIM_PORTT_BASE + HCS12_PIM_RDR_OFFSET)
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#define HCS12_PIM_PORTT_PER (HCS12_PIM_PORTT_BASE + HCS12_PIM_PER_OFFSET)
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#define HCS12_PIM_PORTT_PS (HCS12_PIM_PORTT_BASE + HCS12_PIM_PS_OFFSET)
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#define HCS12_PIM_PORTS_IO (HCS12_PIM_PORTS_BASE + HCS12_PIM_IO_OFFSET)
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#define HCS12_PIM_PORTS_INPUT (HCS12_PIM_PORTS_BASE + HCS12_PIM_INPUT_OFFSET)
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#define HCS12_PIM_PORTS_DDR (HCS12_PIM_PORTS_BASE + HCS12_PIM_DDR_OFFSET)
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#define HCS12_PIM_PORTS_RDR (HCS12_PIM_PORTS_BASE + HCS12_PIM_RDR_OFFSET)
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#define HCS12_PIM_PORTS_PER (HCS12_PIM_PORTS_BASE + HCS12_PIM_PER_OFFSET)
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#define HCS12_PIM_PORTS_PS (HCS12_PIM_PORTS_BASE + HCS12_PIM_PS_OFFSET)
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#define HCS12_PIM_PORTS_WOM (HCS12_PIM_PORTS_BASE + HCS12_PIM_WOM_OFFSET)
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#define HCS12_PIM_PORTG_IO (HCS12_PIM_PORTG_BASE + HCS12_PIM_IO_OFFSET)
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#define HCS12_PIM_PORTG_INPUT (HCS12_PIM_PORTG_BASE + HCS12_PIM_INPUT_OFFSET)
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#define HCS12_PIM_PORTG_DDR (HCS12_PIM_PORTG_BASE + HCS12_PIM_DDR_OFFSET)
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#define HCS12_PIM_PORTG_RDR (HCS12_PIM_PORTG_BASE + HCS12_PIM_RDR_OFFSET)
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#define HCS12_PIM_PORTG_PER (HCS12_PIM_PORTG_BASE + HCS12_PIM_PER_OFFSET)
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#define HCS12_PIM_PORTG_PS (HCS12_PIM_PORTG_BASE + HCS12_PIM_PS_OFFSET)
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#define HCS12_PIM_PORTG_IE (HCS12_PIM_PORTG_BASE + HCS12_PIM_IE_OFFSET)
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#define HCS12_PIM_PORTG_IF (HCS12_PIM_PORTG_BASE + HCS12_PIM_IF_OFFSET)
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#define HCS12_PIM_PORTH_IO (HCS12_PIM_PORTH_BASE + HCS12_PIM_IO_OFFSET)
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#define HCS12_PIM_PORTH_INPUT (HCS12_PIM_PORTH_BASE + HCS12_PIM_INPUT_OFFSET)
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#define HCS12_PIM_PORTH_DDR (HCS12_PIM_PORTH_BASE + HCS12_PIM_DDR_OFFSET)
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#define HCS12_PIM_PORTH_RDR (HCS12_PIM_PORTH_BASE + HCS12_PIM_RDR_OFFSET)
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#define HCS12_PIM_PORTH_PER (HCS12_PIM_PORTH_BASE + HCS12_PIM_PER_OFFSET)
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#define HCS12_PIM_PORTH_PS (HCS12_PIM_PORTH_BASE + HCS12_PIM_PS_OFFSET)
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#define HCS12_PIM_PORTH_IE (HCS12_PIM_PORTH_BASE + HCS12_PIM_IE_OFFSET)
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#define HCS12_PIM_PORTH_IF (HCS12_PIM_PORTH_BASE + HCS12_PIM_IF_OFFSET)
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#define HCS12_PIM_PORTJ_IO (HCS12_PIM_PORTJ_BASE + HCS12_PIM_IO_OFFSET)
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#define HCS12_PIM_PORTJ_INPUT (HCS12_PIM_PORTJ_BASE + HCS12_PIM_INPUT_OFFSET)
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#define HCS12_PIM_PORTJ_DDR (HCS12_PIM_PORTJ_BASE + HCS12_PIM_DDR_OFFSET)
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#define HCS12_PIM_PORTJ_RDR (HCS12_PIM_PORTJ_BASE + HCS12_PIM_RDR_OFFSET)
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#define HCS12_PIM_PORTJ_PER (HCS12_PIM_PORTJ_BASE + HCS12_PIM_PER_OFFSET)
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#define HCS12_PIM_PORTJ_PS (HCS12_PIM_PORTJ_BASE + HCS12_PIM_PS_OFFSET)
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#define HCS12_PIM_PORTJ_IE (HCS12_PIM_PORTJ_BASE + HCS12_PIM_IE_OFFSET)
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#define HCS12_PIM_PORTJ_IF (HCS12_PIM_PORTJ_BASE + HCS12_PIM_IF_OFFSET)
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#define HCS12_PIM_PORTL_IO (HCS12_PIM_PORTL_BASE + HCS12_PIM_IO_OFFSET)
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#define HCS12_PIM_PORTL_INPUT (HCS12_PIM_PORTL_BASE + HCS12_PIM_INPUT_OFFSET)
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#define HCS12_PIM_PORTL_DDR (HCS12_PIM_PORTL_BASE + HCS12_PIM_DDR_OFFSET)
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#define HCS12_PIM_PORTL_RDR (HCS12_PIM_PORTL_BASE + HCS12_PIM_RDR_OFFSET)
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#define HCS12_PIM_PORTL_PER (HCS12_PIM_PORTL_BASE + HCS12_PIM_PER_OFFSET)
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#define HCS12_PIM_PORTL_PS (HCS12_PIM_PORTL_BASE + HCS12_PIM_PS_OFFSET)
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#define HCS12_PIM_PORTL_WOM (HCS12_PIM_PORTL_BASE + HCS12_PIM_WOM_OFFSET)
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/* Register Bit Definitions *********************************************************/
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/* Port register bits */
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#define PIM_PIN(n) (1 << (n))
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#define PIM_PIN0 (1 << 0)
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#define PIM_PIN1 (1 << 1)
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#define PIM_PIN2 (1 << 2)
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#define PIM_PIN3 (1 << 3)
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#define PIM_PIN4 (1 << 4)
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#define PIM_PIN5 (1 << 5)
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#define PIM_PIN6 (1 << 6)
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#define PIM_PIN7 (1 << 7)
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/* Port T I/O register aliases */
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#define TIM_IOC4 PIM_PIN4
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#define TIM_IOC5 PIM_PIN5
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#define TIM_IOC6 PIM_PIN6
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#define TIM_IOC7 PIM_PIN7
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/* Port S I/O register aliases */
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#define SCI0_RXD PIM_PIN0
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#define SCI0_TXD PIM_PIN1
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#define SCI1_RXD PIM_PIN2
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#define SCI1_TXD PIM_PIN3
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#define SPI_MISO PIM_PIN4
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#define SPI_MOSI PIM_PIN5
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#define SPI_SCK PIM_PIN6
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#define SPI_SS PIM_PIN7
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/* Port G I/O register aliases */
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#define MII_RXD0 PIM_PIN0
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#define MII_RXD1 PIM_PIN1
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#define MII_RXD2 PIM_PIN2
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#define MII_RXD3 PIM_PIN3
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#define MII_RXCLK PIM_PIN4
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#define MII_RXDV PIM_PIN5
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#define MII_RXER PIM_PIN6
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/* Port H I/O register aliases */
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#define MII_TXD0 PIM_PIN0
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#define MII_TXD1 PIM_PIN1
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#define MII_TXD2 PIM_PIN2
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#define MII_TXD3 PIM_PIN3
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#define MII_TXCLK PIM_PIN4
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#define MII_TXEN PIM_PIN5
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#define MII_TXER PIM_PIN6
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/* Port J I/O register aliases */
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#define MII_MDC PIM_PIN0
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#define MII_MDIO PIM_PIN1
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#define MII_CRS PIM_PIN2
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#define MII_COL PIM_PIN3
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#define IIC_SDA PIM_PIN5
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#define IIC_SCL PIM_PIN6
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/* Port L I/O register aliases */
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#define PHY_ACTLED PIM_PIN0
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#define PHY_LNKLED PIM_PIN1
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#define PHY_SPDLED PIM_PIN2
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#define PHY_DUPLED PIM_PIN3
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#define PHY_COLLED PIM_PIN4
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_PIM_H */
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