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SAMA5 LCDC: Move framebuffer to lower memory; I suspect some corruption by interference

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This commit is contained in:
Gregory Nutt 2013-10-13 10:42:14 -06:00
parent 02f7c5d8d5
commit 3cfe4c2113
2 changed files with 12 additions and 17 deletions
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21
arch/arm/src/sama5/sam_lcd.c
View File

@ -905,8 +905,8 @@ static const uint8_t g_hcrfb[SAMA5_HCR_FBSIZE];
/* Preallocated LCDC layer structures */
#if (CONFIG_SAMA5_LCDC_FBFIXED_BASE & 0x3f) != 0
# error "CONFIG_SAMA5_LCDC_FBFIXED_BASE must be aligned to a 64-byte boundary"
#if (CONFIG_SAMA5_LCDC_FBFIXED_BASE & 7) != 0
# error "CONFIG_SAMA5_LCDC_FBFIXED_BASE must be aligned to a 64-bit boundary"
#endif
/* Base layer */
@ -2081,7 +2081,7 @@ static void sam_layer_color(void)
LAYER_BASE->bpp = 16;
sam_putreg(SAM_LCDC_BASECFG0,
LCDC_BASECFG0_DLBO | LCDC_BASECFG0_BLEN_INCR4);
LCDC_BASECFG0_DLBO | LCDC_BASECFG0_BLEN_INCR16);
sam_putreg(SAM_LCDC_BASECFG1,
LCDC_BASECFG1_16BPP_RGB565);
@ -2096,7 +2096,7 @@ static void sam_layer_color(void)
LAYER_OVR1->bpp = 24;
sam_putreg(SAM_LCDC_OVR1CFG0,
LCDC_OVR1CFG0_DLBO | LCDC_OVR1CFG0_BLEN_INCR16 |
LCDC_OVR1CFG0_DLBO | LCDC_BASECFG0_BLEN_INCR16 |
LCDC_OVR1CFG0_ROTDIS);
sam_putreg(SAM_LCDC_OVR1CFG1,
LCDC_OVR1CFG1_24BPP_RGB888P);
@ -2107,7 +2107,7 @@ static void sam_layer_color(void)
LAYER_OVR1->bpp = 16;
sam_putreg(SAM_LCDC_OVR1CFG0,
LCDC_OVR1CFG0_DLBO | LCDC_OVR1CFG0_BLEN_INCR4 |
LCDC_OVR1CFG0_DLBO | LCDC_BASECFG0_BLEN_INCR16 |
LCDC_OVR1CFG0_ROTDIS);
sam_putreg(SAM_LCDC_OVR1CFG1,
LCDC_OVR1CFG1_16BPP_RGB565);
@ -2126,7 +2126,7 @@ static void sam_layer_color(void)
LAYER_OVR2->bpp = 24;
sam_putreg(SAM_LCDC_OVR2CFG0,
LCDC_OVR2CFG0_DLBO | LCDC_OVR2CFG0_BLEN_INCR16 |
LCDC_OVR2CFG0_DLBO | LCDC_BASECFG0_BLEN_INCR16 |
LCDC_OVR2CFG0_ROTDIS;
sam_putreg(SAM_LCDC_OVR2CFG1,
LCDC_OVR2CFG1_24BPP_RGB888P);
@ -2137,7 +2137,7 @@ static void sam_layer_color(void)
LAYER_OVR2->bpp = 16;
sam_putreg(SAM_LCDC_OVR2CFG0,
LCDC_OVR2CFG0_DLBO | LCDC_OVR2CFG0_BLEN_INCR4 |
LCDC_OVR2CFG0_DLBO | LCDC_BASECFG0_BLEN_INCR16 |
LCDC_OVR2CFG0_ROTDIS);
sam_putreg(SAM_LCDC_OVR2CFG1,
LCDC_OVR2CFG1_16BPP_RGB565);
@ -2167,7 +2167,7 @@ static void sam_layer_color(void)
LAYER_HEO->bpp = 16;
sam_putreg(SAM_LCDC_HEOCFG0,
LCDC_HEOCFG0_DLBO | LCDC_HEOCFG0_BLEN_INCR4 |
LCDC_HEOCFG0_DLBO | LCDC_HEOCFG0_BLEN_INCR16 |
LCDC_HEOCFG0_ROTDIS);
sam_putreg(SAM_LCDC_HEOCFG1,
LCDC_HEOCFG1_16BPP_RGB565);
@ -2200,7 +2200,7 @@ static void sam_layer_color(void)
LAYER_HCR->bpp = 16;
sam_putreg(SAM_LCDC_HCRCFG0,
LCDC_HCRCFG0_DLBO | LCDC_HCRCFG0_BLEN_INCR4 |
LCDC_HCRCFG0_DLBO | LCDC_HCRCFG0_BLEN_INCR16 |
LCDC_HCRCFG0_ROTDIS);
sam_putreg(SAM_LCDC_HCRCFG1,
LCDC_HCRCFG1_16BPP_RGB565);
@ -3080,12 +3080,11 @@ static void sam_show_layer(struct sam_layer_s *layer,
if (buffer)
{
regaddr = g_layerblend[lid];
regval = sam_getreg(regaddr);
regval = sam_getreg(regaddr);
regval |= LCDC_HEOCFG12_DMA | LCDC_HEOCFG12_OVR;
sam_putreg(regaddr, regval);
}
/* Enable and Update */
/* 5. Enable the relevant channel by writing one to the CHEN field of the
* CHXCHER register.
*/

8
configs/sama5d3x-ek/nx/defconfig
View File

@ -176,14 +176,10 @@ CONFIG_SAMA5_MPDDRC=y
CONFIG_SAMA5_LCDC_BACKLIGHT=y
CONFIG_SAMA5_LCDC_DEFBACKLIGHT=0xc8
CONFIG_SAMA5_LCDC_BACKCOLOR=0x7b5d
# CONFIG_SAMA5_LCDC_OUTPUT_12BPP is not set
# CONFIG_SAMA5_LCDC_OUTPUT_16BPP is not set
# CONFIG_SAMA5_LCDC_OUTPUT_18BPP is not set
CONFIG_SAMA5_LCDC_OUTPUT_24BPP=y
# CONFIG_SAMA5_LCDC_FBALLOCATED is not set
CONFIG_SAMA5_LCDC_FBFIXED=y
# CONFIG_SAMA5_LCDC_FBPREALLOCATED is not set
CONFIG_SAMA5_LCDC_FBFIXED_BASE=0x2fa80000
CONFIG_SAMA5_LCDC_FBFIXED_BASE=0x20000000
CONFIG_SAMA5_LCDC_FBFIXED_SIZE=5767168
#
@ -237,7 +233,7 @@ CONFIG_SAMA5_BOOT_CS0FLASH=y
#
CONFIG_SAMA5_ISRAM_HEAP=y
CONFIG_SAMA5_DDRCS_HEAP=y
CONFIG_SAMA5_DDRCS_HEAP_OFFSET=0
CONFIG_SAMA5_DDRCS_HEAP_OFFSET=5767168
CONFIG_SAMA5_DDRCS_HEAP_SIZE=262668288
#