Updates for PIC32MX USB driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4233 42af7a65-404d-4744-a932-0658087f49c3
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@ -57,7 +57,7 @@
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/* GPIO settings used in the configport, readport, writeport, etc.
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*
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* General encoding:
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* MMxV Ixxx RRRx PPPP
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* MMxV IIxx RRRx PPPP
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*/
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#define GPIO_MODE_SHIFT (14) /* Bits 14-15: I/O mode */
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@ -70,7 +70,7 @@
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# define GPIO_VALUE_ONE (1 << 12)
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# define GPIO_VALUE_ZERO (0)
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#define GPIO_INT_SHIFT (14) /* Bits 10-11: Interrupt mode */
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#define GPIO_INT_SHIFT (10) /* Bits 10-11: Interrupt mode */
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#define GPIO_INT_MASK (3 << GPIO_INT_SHIFT)
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# define GPIO_INT_NONE (0 << GPIO_INT_SHIFT) /* Bit 00: No interrupt */
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# define GPIO_INT (1 << GPIO_INT_SHIFT) /* Bit 01: Change notification enable */
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@ -70,7 +70,7 @@
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#define PIC32MX_USB_BDTP3_OFFSET 0x02d0 /* USB Buffer Descriptor Table Pointer Register 3 */
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#define PIC32MX_USB_CNFG1_OFFSET 0x02e0 /* USB Debug and Idle Register */
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#define PIC32MX_USB_EP_OFFSET(n) 0x0300 /* USB Endpoint n Control Register */
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#define PIC32MX_USB_EP_OFFSET(n) (0x0300+((n)<<4))
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#define PIC32MX_USB_EP0_OFFSET 0x0300 /* USB Endpoint 0 Control Register */
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#define PIC32MX_USB_EP1_OFFSET 0x0310 /* USB Endpoint 1 Control Register */
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#define PIC32MX_USB_EP2_OFFSET 0x0320 /* USB Endpoint 2 Control Register */
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@ -184,6 +184,8 @@
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#define USB_INT_ATTACH (1 << 6) /* Bit 6: Peripheral Attach Interrupt */
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#define USB_INT_STALL (1 << 7) /* Bit 7: STALL Handshake Interrupt */
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#define USB_INT_ALL 0xff
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/* USB Pending Error Interrupt Register */
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/* USB Interrupt Error Enable Register */
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@ -197,6 +199,8 @@
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#define USB_EINT_BMX (1 << 6) /* Bit 6: Bus Matrix Error Flag */
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#define USB_EINT_BTS (1 << 7) /* Bit 7: Bit Stuff Error Flag */
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#define USB_EINT_ALL 0xff
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/* USB Status FIFO Register */
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#define USB_STAT_PPBI (1 << 2) /* Bit 2: Ping-Pong BD Pointer Indicator */
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@ -277,18 +281,51 @@
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#define USB_EP_EPHSHK (1 << 0) /* Bit 0: Endpoint Handshake Enable */
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#define USB_EP_EPSTALL (1 << 1) /* Bit 1: Endpoint Stall Status */
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#define USB_EP_EPRXEN (1 << 3) /* Bit 3: Endpoint Receive Enable */
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#define USB_EP_EPTXEN (1 << 2) /* Bit 2: Endpoint Transmit Enable */
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#define USB_EP_EPRXEN (1 << 3) /* Bit 3: Endpoint Receive Enable */
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#define USB_EP_EPCONDIS (1 << 4) /* Bit 4: Bidirectional Endpoint Control */
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#define USB_EP_RETRYDIS (1 << 6) /* Bit 6: Retry Disable (Host mode and U1EP0 only) */
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#define USB_EP_LSPD (1 << 7) /* Bit 7: Low-Speed Direct Connection Enable */
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/* Buffer Descriptor Table (BDT) ****************************************************/
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/* Offset 0: On write (software->hardware) */
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#define USB_BDT_BSTALL (1 << 2) /* Bit 2: Buffer Stall Enable bit */
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#define USB_BDT_DTS (1 << 3) /* Bit 3: Data Toggle Synchronization Enable bit */
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#define USB_BDT_NINC (1 << 4) /* Bit 4: DMA Address Increment Disable bit */
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#define USB_BDT_KEEP (1 << 5) /* Bit 5: BD Keep Enable bit */
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#define USB_BDT_DATA01 (1 << 6) /* Bit 6: Data Toggle Packet bit */
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#define USB_BDT_UOWN (1 << 7) /* Bit 7: USB Own bit */
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#define USB_BDT_BYTECOUNT_SHIFT (16) /* Bits 16-25: Byte Count bits */
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#define USB_BDT_BYTECOUNT_MASK (0x3ff << USB_BDT_BYTECOUNT_SHIFT)
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#define USB_BDT_DATA0 0 /* DATA0 packet expected next */
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#define USB_BDT_DATA1 USB_BDT_DATA01 /* DATA1 packet expected next */
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#define USB_BDT_COWN 0 /* CPU owns the descriptor */
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/* Offset 0: On read (hardware->software) */
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#define USB_BDT_PID_SHIFT (2) /* Bits 2-5: Packet Identifier bits */
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#define USB_BDT_PID_MASK (15 << USB_BDT_BYTECOUNT_SHIFT)
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/* Bit 7: USB Own bit (same) */
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/* Bits 16-25: Byte Count bits (same) */
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/* Offset 4: BUFFER_ADDRESS, 32-bit Buffer Address bits */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/* Buffer Descriptor Status Register layout. */
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struct usbotg_bdtentry_s
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{
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uint32_t status; /* Status, byte count, and PID */
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uint8_t *addr; /* Buffer address */
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};
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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