arch/arm: Add a "cc" flag to instructions that may modify condition flag.

Notify the compiler that the condition flag has changed to prevent the
compiler from optimizing and reordering instructions, which may cause exceptions.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
This commit is contained in:
zhangyuan21 2023-04-26 17:07:24 +08:00 committed by Xiang Xiao
parent f67e50e920
commit 3d47505ec7
5 changed files with 7 additions and 7 deletions

View File

@ -187,7 +187,7 @@ static inline irqstate_t up_irq_save(void)
"\tmsr cpsr_c, %1"
: "=r" (flags), "=r" (temp)
:
: "memory");
: "cc", "memory");
return flags;
}
@ -200,7 +200,7 @@ static inline void up_irq_restore(irqstate_t flags)
"msr cpsr_c, %0"
:
: "r" (flags)
: "memory");
: "cc", "memory");
}
/* Enable IRQs and return the previous IRQ state */
@ -216,7 +216,7 @@ static inline irqstate_t up_irq_enable(void)
"\tmsr cpsr_c, %1"
: "=r" (flags), "=r" (temp)
:
: "memory");
: "cc", "memory");
return flags;
}
#endif /* __ASSEMBLY__ */

View File

@ -457,7 +457,7 @@ static inline void up_irq_restore(irqstate_t flags)
"1:\n"
:
: "r" (flags)
: "memory");
: "cc", "memory");
#endif
}

View File

@ -430,7 +430,7 @@ static inline void up_irq_restore(irqstate_t flags)
"1:\n"
:
: "r" (flags)
: "memory");
: "cc", "memory");
#endif
}

View File

@ -81,7 +81,7 @@ static inline void tiva_delay(uint32_t delay)
__asm__ __volatile__("1:\n"
"\tsubs %0, #1\n"
"\tbne 1b\n"
: "=r"(delay) : "r"(delay));
: "=r"(delay) : "r"(delay) : "cc");
}
/****************************************************************************

View File

@ -164,7 +164,7 @@ static inline void tiva_delay(uint32_t delay)
__asm__ __volatile__("1:\n"
"\tsubs %0, #1\n"
"\tbne 1b\n"
: "=r"(delay) : "r"(delay));
: "=r"(delay) : "r"(delay) : "cc");
}
/****************************************************************************