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Misc SAM4S-related changes from Bob Doison

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This commit is contained in:
Gregory Nutt 2014-04-21 19:32:15 -06:00
parent 61e80ae998
commit 3d8e313995
5 changed files with 66 additions and 36 deletions
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5
arch/arm/src/sam34/sam_hsmci.c
View File

@ -159,6 +159,11 @@
* HSMCI_INT_RINDE Response Index Error
*/
#define HSMCI_STATUS_ERRORS \
(HSMCI_INT_UNRE | HSMCI_INT_OVRE | HSMCI_INT_BLKOVRE | HSMCI_INT_CSTOE | \
HSMCI_INT_DTOE | HSMCI_INT_DCRCE | HSMCI_INT_RTOE | HSMCI_INT_RENDE | \
HSMCI_INT_RCRCE | HSMCI_INT_RDIRE | HSMCI_INT_RINDE)
/* Response errors:
*
* HSMCI_INT_CSTOE Completion signal time-out error (see HSMCI_CSTOR)

8
arch/arm/src/sam34/sam_wdt.c
View File

@ -413,7 +413,6 @@ static int sam34_getstatus(FAR struct watchdog_lowerhalf_s *lower,
{
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
uint32_t elapsed;
uint16_t reload;
wdvdbg("Entry\n");
DEBUGASSERT(priv);
@ -470,7 +469,6 @@ static int sam34_settimeout(FAR struct watchdog_lowerhalf_s *lower,
{
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
uint32_t reload;
uint16_t regval;
DEBUGASSERT(priv);
wdvdbg("Entry: timeout=%d\n", timeout);
@ -538,6 +536,7 @@ static int sam34_settimeout(FAR struct watchdog_lowerhalf_s *lower,
static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
xcpt_t handler)
{
#if 0 // TODO
FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower;
irqstate_t flags;
xcpt_t oldhandler;
@ -548,7 +547,6 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
/* Get the old handler return value */
flags = irqsave();
#if 0 // TODO
oldhandler = priv->handler;
/* Save the new handler */
@ -577,9 +575,11 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
up_disable_irq(STM32_IRQ_WWDG);
}
#endif
irqrestore(flags);
return oldhandler;
#endif
ASSERT(0);
return NULL;
}
/****************************************************************************

48
configs/sam4s-xplained-pro/include/board.h
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@ -62,6 +62,11 @@
#define BOARD_CKGR_MOR_MOSCXTST (63 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
#define BOARD_32KOSC_FREQUENCY (32768)
#define BOARD_SLCK_FREQUENCY (BOARD_32KOSC_FREQUENCY)
#define BOARD_MAINOSC_FREQUENCY (12000000)
#ifdef CONFIG_SAM34_UDP
/* PLLA configuration:
*
* Source: 12MHz crystall at 12MHz
@ -69,25 +74,44 @@
* PLLdiv: 1 (bypassed)
* Fpll: (12MHz * 20) / 1 = 240MHz
*/
#define BOARD_32KOSC_FREQUENCY (32768)
#define BOARD_SLCK_FREQUENCY (BOARD_32KOSC_FREQUENCY)
#define BOARD_MAINOSC_FREQUENCY (12000000)
#define BOARD_CKGR_PLLAR_MUL (19 << PMC_CKGR_PLLAR_MUL_SHIFT)
#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
#define BOARD_PLLA_FREQUENCY (20*BOARD_MAINOSC_FREQUENCY) /* PLLA = 240Mhz */
# define BOARD_CKGR_PLLAR_MUL (19 << PMC_CKGR_PLLAR_MUL_SHIFT)
# define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
# define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
# define BOARD_PLLA_FREQUENCY (20*BOARD_MAINOSC_FREQUENCY) /* PLLA = 240Mhz */
/* PMC master clock register settings */
#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2
#define BOARD_MCK_FREQUENCY (BOARD_PLLA_FREQUENCY/2) /* MCK = 120Mhz */
#define BOARD_CPU_FREQUENCY (BOARD_PLLA_FREQUENCY/2) /* CPU = 120Mhz */
# define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
# define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2
# define BOARD_MCK_FREQUENCY (BOARD_PLLA_FREQUENCY/2) /* MCK = 120Mhz */
# define BOARD_CPU_FREQUENCY (BOARD_PLLA_FREQUENCY/2) /* CPU = 120Mhz */
/* USB UTMI PLL start-up time */
#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
# define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
#else
/* PLLA configuration:
*
* Source: 12MHz crystall at 12MHz
* PLLmul: 10
* PLLdiv: 1 (bypassed)
* Fpll: (12MHz * 10) / 1 = 120MHz
*/
# define BOARD_CKGR_PLLAR_MUL (9 << PMC_CKGR_PLLAR_MUL_SHIFT)
# define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
# define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
# define BOARD_PLLA_FREQUENCY (10*BOARD_MAINOSC_FREQUENCY) /* PLLA = 120Mhz */
/* PMC master clock register settings */
# define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
# define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1
# define BOARD_MCK_FREQUENCY (BOARD_PLLA_FREQUENCY) /* MCK = 120Mhz */
# define BOARD_CPU_FREQUENCY (BOARD_PLLA_FREQUENCY) /* CPU = 120Mhz */
#endif
/* HSMCI clocking
*

12
configs/sam4s-xplained-pro/nsh/defconfig
View File

@ -333,9 +333,8 @@ CONFIG_ARCH_BOARD="sam4s-xplained-pro"
CONFIG_ARCH_HAVE_LEDS=y
CONFIG_ARCH_LEDS=y
CONFIG_ARCH_HAVE_BUTTONS=y
CONFIG_ARCH_BUTTONS=y
# CONFIG_ARCH_BUTTONS is not set
CONFIG_ARCH_HAVE_IRQBUTTONS=y
CONFIG_ARCH_IRQBUTTONS=y
CONFIG_NSH_MMCSDMINOR=0
CONFIG_NSH_MMCSDSLOTNO=0
@ -388,7 +387,9 @@ CONFIG_NPTHREAD_KEYS=4
#
# Performance Monitoring
#
# CONFIG_SCHED_CPULOAD is not set
CONFIG_SCHED_CPULOAD=y
# CONFIG_SCHED_CPULOAD_EXTCLK is not set
CONFIG_SCHED_CPULOAD_TIMECONSTANT=2
# CONFIG_SCHED_INSTRUMENTATION is not set
#
@ -398,8 +399,8 @@ CONFIG_DEV_CONSOLE=y
# CONFIG_FDCLONE_DISABLE is not set
# CONFIG_FDCLONE_STDIO is not set
CONFIG_SDCLONE_DISABLE=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NFILE_DESCRIPTORS=16
CONFIG_NFILE_STREAMS=16
CONFIG_NAME_MAX=32
# CONFIG_PRIORITY_INHERITANCE is not set
@ -642,6 +643,7 @@ CONFIG_FS_PROCFS=y
#
# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set
# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set
# CONFIG_FS_PROCFS_EXCLUDE_CPULOAD is not set
# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set
#

3
fs/procfs/fs_procfsproc.c
View File

@ -556,14 +556,13 @@ static ssize_t proc_loadavg(FAR struct proc_file_s *procfile,
uint32_t fracpart;
size_t linesize;
size_t copysize;
ssize_t ret;
/* Sample the counts for the thread. clock_cpuload should only fail if
* the PID is not valid. This could happen if the thread exited sometime
* after the procfs entry was opened.
*/
ret = (ssize_t)clock_cpuload(procfile->pid, &cpuload);
(void)clock_cpuload(procfile->pid, &cpuload);
/* On the simulator, you may hit cpuload.total == 0, but probably never on
* real hardware.