arch/xtensa/esp32s2: Add missing SENS and RTCCNTL registers

2022-12-28 03:01:11 -03:00 · 2022-12-28 03:01:11 -03:00 · 3dad6b273e
commit 3dad6b273e
parent 9ae3f4cf17
2 changed files with 2363 additions and 12 deletions
--- a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h
+++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h
@ -4262,6 +4262,594 @@
 #define RTC_CNTL_XTAL32K_RETURN_WAIT_V  0x0000000F
 #define RTC_CNTL_XTAL32K_RETURN_WAIT_S  0

+/* RTC_CNTL_ULP_CP_TIMER_REG register
+ * Description
+ */
+
+#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0xf8)
+
+/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W; bitpos: [31]; default: 0;
+ * ULP-coprocessor timer enable bit
+ */
+
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN    (BIT(31))
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M  (RTC_CNTL_ULP_CP_SLP_TIMER_EN_V << RTC_CNTL_ULP_CP_SLP_TIMER_EN_S)
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V  0x00000001
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S  31
+
+/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO; bitpos: [30]; default: 0;
+ * ULP-coprocessor wakeup by GPIO state clear
+ */
+
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR    (BIT(30))
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M  (RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V << RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S)
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V  0x00000001
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S  30
+
+/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W; bitpos: [29]; default: 0;
+ * ULP-coprocessor wakeup by GPIO enable
+ */
+
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA    (BIT(29))
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M  (RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V << RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S)
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V  0x00000001
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S  29
+
+/* RTC_CNTL_ULP_CP_PC_INIT : R/W; bitpos: [10:0]; default: 0;
+ * ULP-coprocessor PC initial address
+ */
+
+#define RTC_CNTL_ULP_CP_PC_INIT    0x000007ff
+#define RTC_CNTL_ULP_CP_PC_INIT_M  (RTC_CNTL_ULP_CP_PC_INIT_V << RTC_CNTL_ULP_CP_PC_INIT_S)
+#define RTC_CNTL_ULP_CP_PC_INIT_V  0x000007ff
+#define RTC_CNTL_ULP_CP_PC_INIT_S  0
+
+/* RTC_CNTL_ULP_CP_CTRL_REG register
+ * Description
+ */
+
+#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0xfc)
+
+/* RTC_CNTL_ULP_CP_START_TOP : R/W; bitpos: [31]; default: 0;
+ * Write 1 to start ULP-coprocessor
+ */
+
+#define RTC_CNTL_ULP_CP_START_TOP    (BIT(31))
+#define RTC_CNTL_ULP_CP_START_TOP_M  (RTC_CNTL_ULP_CP_START_TOP_V << RTC_CNTL_ULP_CP_START_TOP_S)
+#define RTC_CNTL_ULP_CP_START_TOP_V  0x00000001
+#define RTC_CNTL_ULP_CP_START_TOP_S  31
+
+/* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W; bitpos: [30]; default: 0;
+ * 1: ULP-coprocessor is started by SW
+ */
+
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP    (BIT(30))
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M  (RTC_CNTL_ULP_CP_FORCE_START_TOP_V << RTC_CNTL_ULP_CP_FORCE_START_TOP_S)
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V  0x00000001
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S  30
+
+/* RTC_CNTL_ULP_CP_RESET : R/W; bitpos: [29]; default: 0;
+ * ulp coprocessor clk software reset
+ */
+
+#define RTC_CNTL_ULP_CP_RESET    (BIT(29))
+#define RTC_CNTL_ULP_CP_RESET_M  (RTC_CNTL_ULP_CP_RESET_V << RTC_CNTL_ULP_CP_RESET_S)
+#define RTC_CNTL_ULP_CP_RESET_V  0x00000001
+#define RTC_CNTL_ULP_CP_RESET_S  29
+
+/* RTC_CNTL_ULP_CP_CLK_FO : R/W; bitpos: [28]; default: 0;
+ * ulp coprocessor clk force on
+ */
+
+#define RTC_CNTL_ULP_CP_CLK_FO    (BIT(28))
+#define RTC_CNTL_ULP_CP_CLK_FO_M  (RTC_CNTL_ULP_CP_CLK_FO_V << RTC_CNTL_ULP_CP_CLK_FO_S)
+#define RTC_CNTL_ULP_CP_CLK_FO_V  0x00000001
+#define RTC_CNTL_ULP_CP_CLK_FO_S  28
+
+/* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO; bitpos: [22]; default: 0; */
+
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR    (BIT(22))
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M  (RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V << RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S)
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V  0x00000001
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S  22
+
+/* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W; bitpos: [21:11]; default: 512; */
+
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE    0x000007ff
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M  (RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V << RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S)
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V  0x000007ff
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S  11
+
+/* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W; bitpos: [10:0]; default: 512; */
+
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT    0x000007ff
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M  (RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V << RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S)
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V  0x000007ff
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S  0
+
+/* RTC_CNTL_COCPU_CTRL_REG register
+ * Description
+ */
+
+#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x100)
+
+/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO; bitpos: [26]; default: 0;
+ * trigger cocpu register interrupt
+ */
+
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER    (BIT(26))
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M  (RTC_CNTL_COCPU_SW_INT_TRIGGER_V << RTC_CNTL_COCPU_SW_INT_TRIGGER_S)
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V  0x00000001
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S  26
+
+/* RTC_CNTL_COCPU_DONE : R/W; bitpos: [25]; default: 0;
+ * done signal used by riscv to control timer.
+ */
+
+#define RTC_CNTL_COCPU_DONE    (BIT(25))
+#define RTC_CNTL_COCPU_DONE_M  (RTC_CNTL_COCPU_DONE_V << RTC_CNTL_COCPU_DONE_S)
+#define RTC_CNTL_COCPU_DONE_V  0x00000001
+#define RTC_CNTL_COCPU_DONE_S  25
+
+/* RTC_CNTL_COCPU_DONE_FORCE : R/W; bitpos: [24]; default: 0;
+ * 1: select riscv done 0: select ulp done
+ */
+
+#define RTC_CNTL_COCPU_DONE_FORCE    (BIT(24))
+#define RTC_CNTL_COCPU_DONE_FORCE_M  (RTC_CNTL_COCPU_DONE_FORCE_V << RTC_CNTL_COCPU_DONE_FORCE_S)
+#define RTC_CNTL_COCPU_DONE_FORCE_V  0x00000001
+#define RTC_CNTL_COCPU_DONE_FORCE_S  24
+
+/* RTC_CNTL_COCPU_SEL : R/W; bitpos: [23]; default: 1;
+ * 1: old ULP 0: new riscV
+ */
+
+#define RTC_CNTL_COCPU_SEL    (BIT(23))
+#define RTC_CNTL_COCPU_SEL_M  (RTC_CNTL_COCPU_SEL_V << RTC_CNTL_COCPU_SEL_S)
+#define RTC_CNTL_COCPU_SEL_V  0x00000001
+#define RTC_CNTL_COCPU_SEL_S  23
+
+/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W; bitpos: [22]; default: 0;
+ * to reset cocpu
+ */
+
+#define RTC_CNTL_COCPU_SHUT_RESET_EN    (BIT(22))
+#define RTC_CNTL_COCPU_SHUT_RESET_EN_M  (RTC_CNTL_COCPU_SHUT_RESET_EN_V << RTC_CNTL_COCPU_SHUT_RESET_EN_S)
+#define RTC_CNTL_COCPU_SHUT_RESET_EN_V  0x00000001
+#define RTC_CNTL_COCPU_SHUT_RESET_EN_S  22
+
+/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W; bitpos: [21:14]; default: 40;
+ * time from shut cocpu to disable clk
+ */
+
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS    0x000000ff
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M  (RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V << RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S)
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V  0x000000ff
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S  14
+
+/* RTC_CNTL_COCPU_SHUT : R/W; bitpos: [13]; default: 0;
+ * to shut cocpu
+ */
+
+#define RTC_CNTL_COCPU_SHUT    (BIT(13))
+#define RTC_CNTL_COCPU_SHUT_M  (RTC_CNTL_COCPU_SHUT_V << RTC_CNTL_COCPU_SHUT_S)
+#define RTC_CNTL_COCPU_SHUT_V  0x00000001
+#define RTC_CNTL_COCPU_SHUT_S  13
+
+/* RTC_CNTL_COCPU_START_2_INTR_EN : R/W; bitpos: [12:7]; default: 16;
+ * time from start cocpu to give start interrupt
+ */
+
+#define RTC_CNTL_COCPU_START_2_INTR_EN    0x0000003f
+#define RTC_CNTL_COCPU_START_2_INTR_EN_M  (RTC_CNTL_COCPU_START_2_INTR_EN_V << RTC_CNTL_COCPU_START_2_INTR_EN_S)
+#define RTC_CNTL_COCPU_START_2_INTR_EN_V  0x0000003f
+#define RTC_CNTL_COCPU_START_2_INTR_EN_S  7
+
+/* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W; bitpos: [6:1]; default: 8;
+ * time from start cocpu to pull down reset
+ */
+
+#define RTC_CNTL_COCPU_START_2_RESET_DIS    0x0000003f
+#define RTC_CNTL_COCPU_START_2_RESET_DIS_M  (RTC_CNTL_COCPU_START_2_RESET_DIS_V << RTC_CNTL_COCPU_START_2_RESET_DIS_S)
+#define RTC_CNTL_COCPU_START_2_RESET_DIS_V  0x0000003f
+#define RTC_CNTL_COCPU_START_2_RESET_DIS_S  1
+
+/* RTC_CNTL_COCPU_CLK_FO : R/W; bitpos: [0]; default: 0;
+ * cocpu clk force on
+ */
+
+#define RTC_CNTL_COCPU_CLK_FO    (BIT(0))
+#define RTC_CNTL_COCPU_CLK_FO_M  (RTC_CNTL_COCPU_CLK_FO_V << RTC_CNTL_COCPU_CLK_FO_S)
+#define RTC_CNTL_COCPU_CLK_FO_V  0x00000001
+#define RTC_CNTL_COCPU_CLK_FO_S  0
+
+/* RTC_CNTL_TOUCH_CTRL1_REG register
+ * Description
+ */
+
+#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x104)
+
+/* RTC_CNTL_TOUCH_MEAS_NUM : R/W; bitpos: [31:16]; default: 4096;
+ * the meas length (in 8MHz)
+ */
+
+#define RTC_CNTL_TOUCH_MEAS_NUM    0x0000ffff
+#define RTC_CNTL_TOUCH_MEAS_NUM_M  (RTC_CNTL_TOUCH_MEAS_NUM_V << RTC_CNTL_TOUCH_MEAS_NUM_S)
+#define RTC_CNTL_TOUCH_MEAS_NUM_V  0x0000ffff
+#define RTC_CNTL_TOUCH_MEAS_NUM_S  16
+
+/* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 256;
+ * sleep cycles for timer
+ */
+
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES    0x0000ffff
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M  (RTC_CNTL_TOUCH_SLEEP_CYCLES_V << RTC_CNTL_TOUCH_SLEEP_CYCLES_S)
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V  0x0000ffff
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S  0
+
+/* RTC_CNTL_TOUCH_CTRL2_REG register
+ * Description
+ */
+
+#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x108)
+
+/* RTC_CNTL_TOUCH_CLKGATE_EN : R/W; bitpos: [31]; default: 0;
+ * touch clock enable
+ */
+
+#define RTC_CNTL_TOUCH_CLKGATE_EN    (BIT(31))
+#define RTC_CNTL_TOUCH_CLKGATE_EN_M  (RTC_CNTL_TOUCH_CLKGATE_EN_V << RTC_CNTL_TOUCH_CLKGATE_EN_S)
+#define RTC_CNTL_TOUCH_CLKGATE_EN_V  0x00000001
+#define RTC_CNTL_TOUCH_CLKGATE_EN_S  31
+
+/* RTC_CNTL_TOUCH_CLK_FO : R/W; bitpos: [30]; default: 0;
+ * touch clock force on
+ */
+
+#define RTC_CNTL_TOUCH_CLK_FO    (BIT(30))
+#define RTC_CNTL_TOUCH_CLK_FO_M  (RTC_CNTL_TOUCH_CLK_FO_V << RTC_CNTL_TOUCH_CLK_FO_S)
+#define RTC_CNTL_TOUCH_CLK_FO_V  0x00000001
+#define RTC_CNTL_TOUCH_CLK_FO_S  30
+
+/* RTC_CNTL_TOUCH_RESET : R/W; bitpos: [29]; default: 0;
+ * reset upgrade touch
+ */
+
+#define RTC_CNTL_TOUCH_RESET    (BIT(29))
+#define RTC_CNTL_TOUCH_RESET_M  (RTC_CNTL_TOUCH_RESET_V << RTC_CNTL_TOUCH_RESET_S)
+#define RTC_CNTL_TOUCH_RESET_V  0x00000001
+#define RTC_CNTL_TOUCH_RESET_S  29
+
+/* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W; bitpos: [28:27]; default: 0;
+ * force touch timer done
+ */
+
+#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE    0x00000003
+#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M  (RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V << RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S)
+#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V  0x00000003
+#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S  27
+
+/* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W; bitpos: [26:25]; default: 0;
+ * when a touch pad is active, sleep cycle could be divided by this number
+ */
+
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV    0x00000003
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M  (RTC_CNTL_TOUCH_SLP_CYC_DIV_V << RTC_CNTL_TOUCH_SLP_CYC_DIV_S)
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V  0x00000003
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S  25
+
+/* RTC_CNTL_TOUCH_XPD_WAIT : R/W; bitpos: [24:17]; default: 4;
+ * the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
+ */
+
+#define RTC_CNTL_TOUCH_XPD_WAIT    0x000000ff
+#define RTC_CNTL_TOUCH_XPD_WAIT_M  (RTC_CNTL_TOUCH_XPD_WAIT_V << RTC_CNTL_TOUCH_XPD_WAIT_S)
+#define RTC_CNTL_TOUCH_XPD_WAIT_V  0x000000ff
+#define RTC_CNTL_TOUCH_XPD_WAIT_S  17
+
+/* RTC_CNTL_TOUCH_START_FORCE : R/W; bitpos: [16]; default: 0;
+ * 1: to start touch fsm by SW
+ */
+
+#define RTC_CNTL_TOUCH_START_FORCE    (BIT(16))
+#define RTC_CNTL_TOUCH_START_FORCE_M  (RTC_CNTL_TOUCH_START_FORCE_V << RTC_CNTL_TOUCH_START_FORCE_S)
+#define RTC_CNTL_TOUCH_START_FORCE_V  0x00000001
+#define RTC_CNTL_TOUCH_START_FORCE_S  16
+
+/* RTC_CNTL_TOUCH_START_EN : R/W; bitpos: [15]; default: 0;
+ * 1: start touch fsm
+ */
+
+#define RTC_CNTL_TOUCH_START_EN    (BIT(15))
+#define RTC_CNTL_TOUCH_START_EN_M  (RTC_CNTL_TOUCH_START_EN_V << RTC_CNTL_TOUCH_START_EN_S)
+#define RTC_CNTL_TOUCH_START_EN_V  0x00000001
+#define RTC_CNTL_TOUCH_START_EN_S  15
+
+/* RTC_CNTL_TOUCH_START_FSM_EN : R/W; bitpos: [14]; default: 1;
+ * 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm
+ */
+
+#define RTC_CNTL_TOUCH_START_FSM_EN    (BIT(14))
+#define RTC_CNTL_TOUCH_START_FSM_EN_M  (RTC_CNTL_TOUCH_START_FSM_EN_V << RTC_CNTL_TOUCH_START_FSM_EN_S)
+#define RTC_CNTL_TOUCH_START_FSM_EN_V  0x00000001
+#define RTC_CNTL_TOUCH_START_FSM_EN_S  14
+
+/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W; bitpos: [13]; default: 0;
+ * touch timer enable bit
+ */
+
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN    (BIT(13))
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M  (RTC_CNTL_TOUCH_SLP_TIMER_EN_V << RTC_CNTL_TOUCH_SLP_TIMER_EN_S)
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V  0x00000001
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S  13
+
+/* RTC_CNTL_TOUCH_DBIAS : R/W; bitpos: [12]; default: 0;
+ * 1:use self bias 0:use bandgap bias
+ */
+
+#define RTC_CNTL_TOUCH_DBIAS    (BIT(12))
+#define RTC_CNTL_TOUCH_DBIAS_M  (RTC_CNTL_TOUCH_DBIAS_V << RTC_CNTL_TOUCH_DBIAS_S)
+#define RTC_CNTL_TOUCH_DBIAS_V  0x00000001
+#define RTC_CNTL_TOUCH_DBIAS_S  12
+
+/* RTC_CNTL_TOUCH_REFC : R/W; bitpos: [11:9]; default: 0;
+ * TOUCH pad0 reference cap
+ */
+
+#define RTC_CNTL_TOUCH_REFC    0x00000007
+#define RTC_CNTL_TOUCH_REFC_M  (RTC_CNTL_TOUCH_REFC_V << RTC_CNTL_TOUCH_REFC_S)
+#define RTC_CNTL_TOUCH_REFC_V  0x00000007
+#define RTC_CNTL_TOUCH_REFC_S  9
+
+/* RTC_CNTL_TOUCH_XPD_BIAS : R/W; bitpos: [8]; default: 0;
+ * TOUCH_XPD_BIAS
+ */
+
+#define RTC_CNTL_TOUCH_XPD_BIAS    (BIT(8))
+#define RTC_CNTL_TOUCH_XPD_BIAS_M  (RTC_CNTL_TOUCH_XPD_BIAS_V << RTC_CNTL_TOUCH_XPD_BIAS_S)
+#define RTC_CNTL_TOUCH_XPD_BIAS_V  0x00000001
+#define RTC_CNTL_TOUCH_XPD_BIAS_S  8
+
+/* RTC_CNTL_TOUCH_DREFH : R/W; bitpos: [7:6]; default: 3;
+ * TOUCH_DREFH
+ */
+
+#define RTC_CNTL_TOUCH_DREFH    0x00000003
+#define RTC_CNTL_TOUCH_DREFH_M  (RTC_CNTL_TOUCH_DREFH_V << RTC_CNTL_TOUCH_DREFH_S)
+#define RTC_CNTL_TOUCH_DREFH_V  0x00000003
+#define RTC_CNTL_TOUCH_DREFH_S  6
+
+/* RTC_CNTL_TOUCH_DREFL : R/W; bitpos: [5:4]; default: 0;
+ * TOUCH_DREFL
+ */
+
+#define RTC_CNTL_TOUCH_DREFL    0x00000003
+#define RTC_CNTL_TOUCH_DREFL_M  (RTC_CNTL_TOUCH_DREFL_V << RTC_CNTL_TOUCH_DREFL_S)
+#define RTC_CNTL_TOUCH_DREFL_V  0x00000003
+#define RTC_CNTL_TOUCH_DREFL_S  4
+
+/* RTC_CNTL_TOUCH_DRANGE : R/W; bitpos: [3:2]; default: 3;
+ * TOUCH_DRANGE
+ */
+
+#define RTC_CNTL_TOUCH_DRANGE    0x00000003
+#define RTC_CNTL_TOUCH_DRANGE_M  (RTC_CNTL_TOUCH_DRANGE_V << RTC_CNTL_TOUCH_DRANGE_S)
+#define RTC_CNTL_TOUCH_DRANGE_V  0x00000003
+#define RTC_CNTL_TOUCH_DRANGE_S  2
+
+/* RTC_CNTL_TOUCH_SCAN_CTRL_REG register
+ * Description
+ */
+
+#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x10c)
+
+/* RTC_CNTL_TOUCH_OUT_RING : R/W; bitpos: [31:28]; default: 15;
+ * select out ring pad
+ */
+
+#define RTC_CNTL_TOUCH_OUT_RING    0x0000000f
+#define RTC_CNTL_TOUCH_OUT_RING_M  (RTC_CNTL_TOUCH_OUT_RING_V << RTC_CNTL_TOUCH_OUT_RING_S)
+#define RTC_CNTL_TOUCH_OUT_RING_V  0x0000000f
+#define RTC_CNTL_TOUCH_OUT_RING_S  28
+
+/* RTC_CNTL_TOUCH_BUFDRV : R/W; bitpos: [27:25]; default: 0;
+ * touch7 buffer driver strength
+ */
+
+#define RTC_CNTL_TOUCH_BUFDRV    0x00000007
+#define RTC_CNTL_TOUCH_BUFDRV_M  (RTC_CNTL_TOUCH_BUFDRV_V << RTC_CNTL_TOUCH_BUFDRV_S)
+#define RTC_CNTL_TOUCH_BUFDRV_V  0x00000007
+#define RTC_CNTL_TOUCH_BUFDRV_S  25
+
+/* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W; bitpos: [24:10]; default: 0;
+ * touch scan mode pad enable map
+ */
+
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP    0x00007fff
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M  (RTC_CNTL_TOUCH_SCAN_PAD_MAP_V << RTC_CNTL_TOUCH_SCAN_PAD_MAP_S)
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V  0x00007fff
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S  10
+
+/* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W; bitpos: [9]; default: 0;
+ * touch pad14 will be used as shield
+ */
+
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN    (BIT(9))
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M  (RTC_CNTL_TOUCH_SHIELD_PAD_EN_V << RTC_CNTL_TOUCH_SHIELD_PAD_EN_S)
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V  0x00000001
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S  9
+
+/* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W; bitpos: [8]; default: 1;
+ * inactive touch pads connect to 1: gnd 0: HighZ
+ */
+
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION    (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M  (RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V << RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S)
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V  0x00000001
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S  8
+
+/* RTC_CNTL_TOUCH_DENOISE_EN : R/W; bitpos: [2]; default: 0;
+ * touch pad0 will be used to de-noise
+ */
+
+#define RTC_CNTL_TOUCH_DENOISE_EN    (BIT(2))
+#define RTC_CNTL_TOUCH_DENOISE_EN_M  (RTC_CNTL_TOUCH_DENOISE_EN_V << RTC_CNTL_TOUCH_DENOISE_EN_S)
+#define RTC_CNTL_TOUCH_DENOISE_EN_V  0x00000001
+#define RTC_CNTL_TOUCH_DENOISE_EN_S  2
+
+/* RTC_CNTL_TOUCH_DENOISE_RES : R/W; bitpos: [1:0]; default: 2;
+ * De-noise resolution: 12/10/8/4 bit
+ */
+
+#define RTC_CNTL_TOUCH_DENOISE_RES    0x00000003
+#define RTC_CNTL_TOUCH_DENOISE_RES_M  (RTC_CNTL_TOUCH_DENOISE_RES_V << RTC_CNTL_TOUCH_DENOISE_RES_S)
+#define RTC_CNTL_TOUCH_DENOISE_RES_V  0x00000003
+#define RTC_CNTL_TOUCH_DENOISE_RES_S  0
+
+/* RTC_CNTL_TOUCH_SLP_THRES_REG register
+ * Description
+ */
+
+#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x110)
+
+/* RTC_CNTL_TOUCH_SLP_PAD : R/W; bitpos: [31:27]; default: 15;
+ * N/A
+ */
+
+#define RTC_CNTL_TOUCH_SLP_PAD    0x0000001f
+#define RTC_CNTL_TOUCH_SLP_PAD_M  (RTC_CNTL_TOUCH_SLP_PAD_V << RTC_CNTL_TOUCH_SLP_PAD_S)
+#define RTC_CNTL_TOUCH_SLP_PAD_V  0x0000001f
+#define RTC_CNTL_TOUCH_SLP_PAD_S  27
+
+/* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W; bitpos: [26]; default: 0;
+ * sleep pad approach function enable
+ */
+
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN    (BIT(26))
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M  (RTC_CNTL_TOUCH_SLP_APPROACH_EN_V << RTC_CNTL_TOUCH_SLP_APPROACH_EN_S)
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V  0x00000001
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S  26
+
+/* RTC_CNTL_TOUCH_SLP_TH : R/W; bitpos: [21:0]; default: 0;
+ * the threshold for sleep touch pad
+ */
+
+#define RTC_CNTL_TOUCH_SLP_TH    0x003fffff
+#define RTC_CNTL_TOUCH_SLP_TH_M  (RTC_CNTL_TOUCH_SLP_TH_V << RTC_CNTL_TOUCH_SLP_TH_S)
+#define RTC_CNTL_TOUCH_SLP_TH_V  0x003fffff
+#define RTC_CNTL_TOUCH_SLP_TH_S  0
+
+/* RTC_CNTL_TOUCH_APPROACH_REG register
+ * Description
+ */
+
+#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x114)
+
+/* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W; bitpos: [31:24]; default: 80;
+ * approach pads total meas times
+ */
+
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME    0x000000ff
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M  (RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V << RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S)
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V  0x000000ff
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S  24
+
+/* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO; bitpos: [23]; default: 0;
+ * clear touch slp channel
+ */
+
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR    (BIT(23))
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M  (RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V << RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S)
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V  0x00000001
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S  23
+
+/* RTC_CNTL_TOUCH_FILTER_CTRL_REG register
+ * Description
+ */
+
+#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x118)
+
+/* RTC_CNTL_TOUCH_FILTER_EN : R/W; bitpos: [31]; default: 1;
+ * touch filter enable
+ */
+
+#define RTC_CNTL_TOUCH_FILTER_EN    (BIT(31))
+#define RTC_CNTL_TOUCH_FILTER_EN_M  (RTC_CNTL_TOUCH_FILTER_EN_V << RTC_CNTL_TOUCH_FILTER_EN_S)
+#define RTC_CNTL_TOUCH_FILTER_EN_V  0x00000001
+#define RTC_CNTL_TOUCH_FILTER_EN_S  31
+
+/* RTC_CNTL_TOUCH_FILTER_MODE : R/W; bitpos: [30:28]; default: 1;
+ * 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter
+ */
+
+#define RTC_CNTL_TOUCH_FILTER_MODE    0x00000007
+#define RTC_CNTL_TOUCH_FILTER_MODE_M  (RTC_CNTL_TOUCH_FILTER_MODE_V << RTC_CNTL_TOUCH_FILTER_MODE_S)
+#define RTC_CNTL_TOUCH_FILTER_MODE_V  0x00000007
+#define RTC_CNTL_TOUCH_FILTER_MODE_S  28
+
+/* RTC_CNTL_TOUCH_DEBOUNCE : R/W; bitpos: [27:25]; default: 3;
+ * debounce counter
+ */
+
+#define RTC_CNTL_TOUCH_DEBOUNCE    0x00000007
+#define RTC_CNTL_TOUCH_DEBOUNCE_M  (RTC_CNTL_TOUCH_DEBOUNCE_V << RTC_CNTL_TOUCH_DEBOUNCE_S)
+#define RTC_CNTL_TOUCH_DEBOUNCE_V  0x00000007
+#define RTC_CNTL_TOUCH_DEBOUNCE_S  25
+
+/* RTC_CNTL_TOUCH_HYSTERESIS : R/W; bitpos: [24:23]; default: 1;
+ * N/A
+ */
+
+#define RTC_CNTL_TOUCH_HYSTERESIS    0x00000003
+#define RTC_CNTL_TOUCH_HYSTERESIS_M  (RTC_CNTL_TOUCH_HYSTERESIS_V << RTC_CNTL_TOUCH_HYSTERESIS_S)
+#define RTC_CNTL_TOUCH_HYSTERESIS_V  0x00000003
+#define RTC_CNTL_TOUCH_HYSTERESIS_S  23
+
+/* RTC_CNTL_TOUCH_NOISE_THRES : R/W; bitpos: [22:21]; default: 1;
+ * N/A
+ */
+
+#define RTC_CNTL_TOUCH_NOISE_THRES    0x00000003
+#define RTC_CNTL_TOUCH_NOISE_THRES_M  (RTC_CNTL_TOUCH_NOISE_THRES_V << RTC_CNTL_TOUCH_NOISE_THRES_S)
+#define RTC_CNTL_TOUCH_NOISE_THRES_V  0x00000003
+#define RTC_CNTL_TOUCH_NOISE_THRES_S  21
+
+/* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W; bitpos: [20:19]; default: 1;
+ * N/A
+ */
+
+#define RTC_CNTL_TOUCH_NEG_NOISE_THRES    0x00000003
+#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_M  (RTC_CNTL_TOUCH_NEG_NOISE_THRES_V << RTC_CNTL_TOUCH_NEG_NOISE_THRES_S)
+#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_V  0x00000003
+#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S  19
+
+/* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W; bitpos: [18:15]; default: 5;
+ * negative threshold counter limit
+ */
+
+#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT    0x0000000f
+#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_M  (RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V << RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S)
+#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V  0x0000000f
+#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S  15
+
+/* RTC_CNTL_TOUCH_JITTER_STEP : R/W; bitpos: [14:11]; default: 1;
+ * touch jitter step
+ */
+
+#define RTC_CNTL_TOUCH_JITTER_STEP    0x0000000f
+#define RTC_CNTL_TOUCH_JITTER_STEP_M  (RTC_CNTL_TOUCH_JITTER_STEP_V << RTC_CNTL_TOUCH_JITTER_STEP_S)
+#define RTC_CNTL_TOUCH_JITTER_STEP_V  0x0000000f
+#define RTC_CNTL_TOUCH_JITTER_STEP_S  11
+
+/* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W; bitpos: [10:9]; default: 0;
+ * touch jitter step
+ */
+
+#define RTC_CNTL_TOUCH_SMOOTH_LVL    0x00000003
+#define RTC_CNTL_TOUCH_SMOOTH_LVL_M  (RTC_CNTL_TOUCH_SMOOTH_LVL_V << RTC_CNTL_TOUCH_SMOOTH_LVL_S)
+#define RTC_CNTL_TOUCH_SMOOTH_LVL_V  0x00000003
+#define RTC_CNTL_TOUCH_SMOOTH_LVL_S  9
+
 /* RTC_CNTL_USB_CONF_REG register
 * configure usb control register
 */
@ -4387,29 +4975,53 @@
 #define RTC_CNTL_USB_VREFH_V  0x00000003
 #define RTC_CNTL_USB_VREFH_S  0

+/* RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG register
+ * Description
+ */
+
+#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x120)
+
+/* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W; bitpos: [22]; default: 1;
+ * N/A
+ */
+
+#define RTC_CNTL_TOUCH_TIMEOUT_EN    (BIT(22))
+#define RTC_CNTL_TOUCH_TIMEOUT_EN_M  (RTC_CNTL_TOUCH_TIMEOUT_EN_V << RTC_CNTL_TOUCH_TIMEOUT_EN_S)
+#define RTC_CNTL_TOUCH_TIMEOUT_EN_V  0x00000001
+#define RTC_CNTL_TOUCH_TIMEOUT_EN_S  22
+
+/* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W; bitpos: [21:0]; default: 4194303;
+ * N/A
+ */
+
+#define RTC_CNTL_TOUCH_TIMEOUT_NUM    0x003fffff
+#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M  (RTC_CNTL_TOUCH_TIMEOUT_NUM_V << RTC_CNTL_TOUCH_TIMEOUT_NUM_S)
+#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V  0x003fffff
+#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S  0
+
 /* RTC_CNTL_SLP_REJECT_CAUSE_REG register
- * sleep reject casue register
+ * Stores the reject-to-sleep cause.
 */

 #define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x124)

 /* RTC_CNTL_REJECT_CAUSE : RO; bitpos: [16:0]; default: 0;
- * sleep reject cause
+ * Stores the reject-to-sleep cause.
 */

-#define RTC_CNTL_REJECT_CAUSE    0x0001FFFF
+#define RTC_CNTL_REJECT_CAUSE    0x0001ffff
 #define RTC_CNTL_REJECT_CAUSE_M  (RTC_CNTL_REJECT_CAUSE_V << RTC_CNTL_REJECT_CAUSE_S)
-#define RTC_CNTL_REJECT_CAUSE_V  0x0001FFFF
+#define RTC_CNTL_REJECT_CAUSE_V  0x0001ffff
 #define RTC_CNTL_REJECT_CAUSE_S  0

 /* RTC_CNTL_OPTION1_REG register
- * configure rtc option
+ * RTC option register
 */

 #define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x128)

 /* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [0]; default: 0;
- * force chip boot from download mode
+ * Set this bit to force the chip to boot from the download mode.
 */

 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT    (BIT(0))
@ -4418,29 +5030,44 @@
 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S  0

 /* RTC_CNTL_SLP_WAKEUP_CAUSE_REG register
- * sleep wakeup cause state register
+ * Stores the sleep-to-wakeup cause.
 */

 #define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x12c)

 /* RTC_CNTL_WAKEUP_CAUSE : RO; bitpos: [16:0]; default: 0;
- * sleep wakeup cause
+ * Stores the wakeup cause.
 */

-#define RTC_CNTL_WAKEUP_CAUSE    0x0001FFFF
+#define RTC_CNTL_WAKEUP_CAUSE    0x0001ffff
 #define RTC_CNTL_WAKEUP_CAUSE_M  (RTC_CNTL_WAKEUP_CAUSE_V << RTC_CNTL_WAKEUP_CAUSE_S)
-#define RTC_CNTL_WAKEUP_CAUSE_V  0x0001FFFF
+#define RTC_CNTL_WAKEUP_CAUSE_V  0x0001ffff
 #define RTC_CNTL_WAKEUP_CAUSE_S  0

+/* RTC_CNTL_ULP_CP_TIMER_1_REG register
+ * Description
+ */
+
+#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x130)
+
+/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W; bitpos: [31:8]; default: 200;
+ * sleep cycles for ULP-coprocessor timer
+ */
+
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE    0x00ffffff
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M  (RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V << RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V  0x00ffffff
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S  8
+
 /* RTC_CNTL_DATE_REG register */

 #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x138)

 /* RTC_CNTL_CNTL_DATE : R/W; bitpos: [27:0]; default: 26239377; */

-#define RTC_CNTL_CNTL_DATE    0x0FFFFFFF
+#define RTC_CNTL_CNTL_DATE    0x0fffffff
 #define RTC_CNTL_CNTL_DATE_M  (RTC_CNTL_CNTL_DATE_V << RTC_CNTL_CNTL_DATE_S)
-#define RTC_CNTL_CNTL_DATE_V  0x0FFFFFFF
+#define RTC_CNTL_CNTL_DATE_V  0x0fffffff
 #define RTC_CNTL_CNTL_DATE_S  0

 #endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTCCNTL_H */
--- a/arch/xtensa/src/esp32s2/hardware/esp32s2_sens.h
+++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_sens.h