S32K - Expand FlexTimer header file and add PWM support
This commit is contained in:
Jari van Ewijk
Abdelatif Guettouche
parent
651eefc8f7
commit
3db090a210
@ -43,6 +43,8 @@ config ARCH_CHIP_S32K144
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config ARCH_CHIP_S32K146
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bool "S32K146"
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select ARCH_CHIP_S32K14X
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select S32K1XX_HAVE_FTM4
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select S32K1XX_HAVE_FTM5
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select S32K1XX_HAVE_LPSPI2
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select S32K1XX_HAVE_FLEXCAN1
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select S32K1XX_HAVE_FLEXCAN2
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@ -53,6 +55,10 @@ config ARCH_CHIP_S32K148
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bool "S32K148"
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select ARCH_CHIP_S32K14X
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select S32K1XX_HAVE_ENET
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select S32K1XX_HAVE_FTM4
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select S32K1XX_HAVE_FTM5
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select S32K1XX_HAVE_FTM6
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select S32K1XX_HAVE_FTM7
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select S32K1XX_HAVE_LPI2C1
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select S32K1XX_HAVE_LPSPI2
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select S32K1XX_HAVE_SAI
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@ -76,6 +82,8 @@ config ARCH_CHIP_S32K14X
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select ARCH_HAVE_FPU
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select ARCH_HAVE_FETCHADD
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select S32K1XX_HAVE_EWM
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select S32K1XX_HAVE_FTM2
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select S32K1XX_HAVE_FTM3
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select S32K1XX_HAVE_SPLL
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select S32K1XX_HAVE_HSRUN
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select S32K1XX_HAVE_LMEM
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@ -98,6 +106,30 @@ config S32K1XX_HAVE_FIRC_CMU
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bool
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default n
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config S32K1XX_HAVE_FTM2
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bool
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default n
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config S32K1XX_HAVE_FTM3
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bool
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default n
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config S32K1XX_HAVE_FTM4
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bool
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default n
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config S32K1XX_HAVE_FTM5
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bool
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default n
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config S32K1XX_HAVE_FTM6
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bool
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default n
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config S32K1XX_HAVE_FTM7
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bool
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default n
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config S32K1XX_HAVE_HSRUN
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bool
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default n
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@ -140,6 +172,10 @@ config S32K1XX_HAVE_SPLL
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# Peripheral Group Selections
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config S32K1XX_FTM
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bool
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default n
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config S32K1XX_LPUART
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bool
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default n
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@ -190,6 +226,52 @@ config S32K1XX_FLEXCAN2
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default n
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depends on S32K1XX_HAVE_FLEXCAN2
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config S32K1XX_FTM0
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bool "FTM0"
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default n
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select S32K1XX_FTM
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config S32K1XX_FTM1
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bool "FTM1"
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default n
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select S32K1XX_FTM
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config S32K1XX_FTM2
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bool "FTM2"
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default n
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select S32K1XX_FTM
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depends on S32K1XX_HAVE_FTM2
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config S32K1XX_FTM3
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bool "FTM3"
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default n
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select S32K1XX_FTM
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depends on S32K1XX_HAVE_FTM3
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config S32K1XX_FTM4
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bool "FTM4"
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default n
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select S32K1XX_FTM
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depends on S32K1XX_HAVE_FTM4
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config S32K1XX_FTM5
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bool "FTM5"
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default n
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select S32K1XX_FTM
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depends on S32K1XX_HAVE_FTM5
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config S32K1XX_FTM6
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bool "FTM6"
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default n
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select S32K1XX_FTM
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depends on S32K1XX_HAVE_FTM6
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config S32K1XX_FTM7
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bool "FTM7"
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default n
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select S32K1XX_FTM
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depends on S32K1XX_HAVE_FTM7
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menuconfig S32K1XX_LPI2C0
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bool "LPI2C0"
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default n
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@ -265,6 +347,99 @@ config S32K1XX_EEEPROM
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endmenu # S32K1XX Peripheral Selection
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menu "S32K1XX FTM PWM Configuration"
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depends on S32K1XX_FTM
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config S32K1XX_FTM0_PWM
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bool "FTM0 PWM"
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default n
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depends on S32K1XX_FTM0
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config S32K1XX_FTM0_CHANNEL
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int "FTM0 PWM Output Channel"
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default 0
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range 0 7
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depends on S32K1XX_FTM0_PWM
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config S32K1XX_FTM1_PWM
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bool "FTM1 PWM"
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default n
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depends on S32K1XX_FTM1
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config S32K1XX_FTM1_CHANNEL
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int "FTM1 PWM Output Channel"
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default 0
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range 0 7
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depends on S32K1XX_FTM1_PWM
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config S32K1XX_FTM2_PWM
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bool "FTM2 PWM"
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default n
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depends on S32K1XX_FTM2
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config S32K1XX_FTM2_CHANNEL
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int "FTM2 PWM Output Channel"
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default 0
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range 0 7
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depends on S32K1XX_FTM2_PWM
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config S32K1XX_FTM3_PWM
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bool "FTM3 PWM"
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default n
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depends on S32K1XX_FTM3
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config S32K1XX_FTM3_CHANNEL
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int "FTM3 PWM Output Channel"
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default 0
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range 0 7
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depends on S32K1XX_FTM3_PWM
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config S32K1XX_FTM4_PWM
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bool "FTM4 PWM"
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default n
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depends on S32K1XX_FTM4
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config S32K1XX_FTM4_CHANNEL
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int "FTM4 PWM Output Channel"
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default 0
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range 0 7
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depends on S32K1XX_FTM4_PWM
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config S32K1XX_FTM5_PWM
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bool "FTM5 PWM"
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default n
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depends on S32K1XX_FTM5
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config S32K1XX_FTM5_CHANNEL
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int "FTM5 PWM Output Channel"
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default 0
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range 0 7
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depends on S32K1XX_FTM5_PWM
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config S32K1XX_FTM6_PWM
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bool "FTM6 PWM"
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default n
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depends on S32K1XX_FTM6
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config S32K1XX_FTM6_CHANNEL
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int "FTM6 PWM Output Channel"
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default 0
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range 0 7
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depends on S32K1XX_FTM6_PWM
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config S32K1XX_FTM7_PWM
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bool "FTM7 PWM"
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default n
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depends on S32K1XX_FTM7
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config S32K1XX_FTM7_CHANNEL
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int "FTM7 PWM Output Channel"
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default 0
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range 0 7
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depends on S32K1XX_FTM7_PWM
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endmenu # S32K1XX FTM PWM Configuration
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config S32K1XX_WDT_DISABLE
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bool "Disable watchdog on reset"
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default y
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@ -58,6 +58,10 @@ ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y)
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CHIP_CSRCS += s32k1xx_flashcfg.c
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endif
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ifeq ($(CONFIG_PWM),y)
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CHIP_CSRCS += s32k1xx_pwm.c
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endif
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ifeq ($(CONFIG_S32K1XX_LPUART),y)
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CHIP_CSRCS += s32k1xx_serial.c
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endif
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File diff suppressed because it is too large
Load Diff
836
arch/arm/src/s32k1xx/s32k1xx_pwm.c
Normal file
836
arch/arm/src/s32k1xx/s32k1xx_pwm.c
Normal file
@ -0,0 +1,836 @@
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/*****************************************************************************
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* arch/arm/src/s32k1xx/s32k1xx_pwm.c
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*
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* Copyright (C) 2013, 2016, 2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Alan Carvalho de Assis <acassis@gmail.com>
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* Ken Fazzone <kfazz01@gmail.com>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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/*****************************************************************************
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* Included Files
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*****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/timers/pwm.h>
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#include <arch/board/board.h>
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#include "arm_internal.h"
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#include "arm_arch.h"
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#include "chip.h"
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#include "s32k1xx_clockconfig.h"
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#include "s32k1xx_pin.h"
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#include "s32k1xx_pwm.h"
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#include "hardware/s32k1xx_gpio.h"
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#include "hardware/s32k1xx_ftm.h"
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#include "hardware/s32k1xx_sim.h"
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/* This module then only compiles if there is at least one enabled timer
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* intended for use with the PWM upper half driver.
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*/
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#if defined(CONFIG_S32K1XX_FTM0_PWM) || defined(CONFIG_S32K1XX_FTM1_PWM) || \
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defined(CONFIG_S32K1XX_FTM2_PWM) || defined(CONFIG_S32K1XX_FTM3_PWM) || \
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defined(CONFIG_S32K1XX_FTM4_PWM) || defined(CONFIG_S32K1XX_FTM5_PWM) || \
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defined(CONFIG_S32K1XX_FTM6_PWM) || defined(CONFIG_S32K1XX_FTM7_PWM)
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/*****************************************************************************
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* Pre-processor Definitions
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*****************************************************************************/
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/* PWM/Timer Definitions *****************************************************/
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/* Debug *********************************************************************/
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#ifdef CONFIG_DEBUG_PWM_INFO
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# define pwm_dumpgpio(p,m) s32k1xx_pindump(p,m)
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#else
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# define pwm_dumpgpio(p,m)
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure represents the state of one PWM timer */
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struct s32k1xx_pwmtimer_s
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{
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FAR const struct pwm_ops_s *ops; /* PWM operations */
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uint8_t tpmid; /* Timer/PWM Module ID {0,..,7} */
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uint8_t channel; /* Timer/PWM Module channel: {0,...,7} */
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uint32_t base; /* The base address of the timer */
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uint32_t pincfg; /* Output pin configuration */
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uint32_t pclk; /* The frequency of the peripheral clock */
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};
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/*****************************************************************************
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* Static Function Prototypes
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*****************************************************************************/
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/* Register access */
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static uint32_t pwm_getreg(struct s32k1xx_pwmtimer_s *priv, int offset);
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static void pwm_putreg(struct s32k1xx_pwmtimer_s *priv, int offset,
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uint32_t value);
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#ifdef CONFIG_DEBUG_PWM_INFO
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static void pwm_dumpregs(struct s32k1xx_pwmtimer_s *priv,
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FAR const char *msg);
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#else
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# define pwm_dumpregs(priv,msg)
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#endif
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/* Timer management */
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static int pwm_timer(FAR struct s32k1xx_pwmtimer_s *priv,
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FAR const struct pwm_info_s *info);
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/* PWM driver methods */
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static int pwm_setup(FAR struct pwm_lowerhalf_s *dev);
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static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev);
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static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
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FAR const struct pwm_info_s *info);
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static int pwm_stop(FAR struct pwm_lowerhalf_s *dev);
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static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd,
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unsigned long arg);
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/*****************************************************************************
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* Private Data
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*****************************************************************************/
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/* This is the list of lower half PWM driver methods used by the upper half
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* driver.
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*/
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static const struct pwm_ops_s g_pwmops =
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{
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.setup = pwm_setup,
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.shutdown = pwm_shutdown,
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.start = pwm_start,
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.stop = pwm_stop,
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.ioctl = pwm_ioctl,
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};
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#ifdef CONFIG_S32K1XX_FTM0_PWM
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static struct s32k1xx_pwmtimer_s g_pwm0dev =
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{
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.ops = &g_pwmops,
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.tpmid = 0,
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.channel = CONFIG_S32K1XX_FTM0_CHANNEL,
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.base = S32K1XX_FTM0_BASE,
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.pincfg = PWM_FTM0_PINCFG,
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};
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#endif
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#ifdef CONFIG_S32K1XX_FTM1_PWM
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static struct s32k1xx_pwmtimer_s g_pwm1dev =
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{
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.ops = &g_pwmops,
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.tpmid = 1,
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.channel = CONFIG_S32K1XX_FTM1_CHANNEL,
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.base = S32K1XX_FTM1_BASE,
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.pincfg = PWM_FTM1_PINCFG,
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};
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#endif
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#ifdef CONFIG_S32K1XX_FTM2_PWM
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static struct s32k1xx_pwmtimer_s g_pwm2dev =
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{
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.ops = &g_pwmops,
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.tpmid = 2,
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.channel = CONFIG_S32K1XX_FTM2_CHANNEL,
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.base = S32K1XX_FTM2_BASE,
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.pincfg = PWM_FTM2_PINCFG,
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};
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#endif
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#ifdef CONFIG_S32K1XX_FTM3_PWM
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static struct s32k1xx_pwmtimer_s g_pwm3dev =
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{
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.ops = &g_pwmops,
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.tpmid = 3,
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.channel = CONFIG_S32K1XX_FTM3_CHANNEL,
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.base = S32K1XX_FTM3_BASE,
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.pincfg = PWM_FTM3_PINCFG,
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};
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#endif
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#ifdef CONFIG_S32K1XX_FTM4_PWM
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static struct s32k1xx_pwmtimer_s g_pwm4dev =
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{
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.ops = &g_pwmops,
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.tpmid = 4,
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.channel = CONFIG_S32K1XX_FTM4_CHANNEL,
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.base = S32K1XX_FTM4_BASE,
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.pincfg = PWM_FTM4_PINCFG,
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};
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#endif
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#ifdef CONFIG_S32K1XX_FTM5_PWM
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static struct s32k1xx_pwmtimer_s g_pwm5dev =
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{
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.ops = &g_pwmops,
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.tpmid = 5,
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.channel = CONFIG_S32K1XX_FTM5_CHANNEL,
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.base = S32K1XX_FTM5_BASE,
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.pincfg = PWM_FTM5_PINCFG,
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};
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#endif
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#ifdef CONFIG_S32K1XX_FTM6_PWM
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static struct s32k1xx_pwmtimer_s g_pwm6dev =
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{
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.ops = &g_pwmops,
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.tpmid = 6,
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.channel = CONFIG_S32K1XX_FTM6_CHANNEL,
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.base = S32K1XX_FTM6_BASE,
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.pincfg = PWM_FTM6_PINCFG,
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};
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#endif
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#ifdef CONFIG_S32K1XX_FTM7_PWM
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static struct s32k1xx_pwmtimer_s g_pwm7dev =
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{
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.ops = &g_pwmops,
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.tpmid = 7,
|
||||
.channel = CONFIG_S32K1XX_FTM7_CHANNEL,
|
||||
.base = S32K1XX_FTM7_BASE,
|
||||
.pincfg = PWM_FTM7_PINCFG,
|
||||
};
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Private Functions
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pwm_getreg
|
||||
*
|
||||
* Description:
|
||||
* Read the value of an PWM timer register.
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - A reference to the PWM block status
|
||||
* offset - The offset to the register to read
|
||||
*
|
||||
* Returned Value:
|
||||
* The current contents of the specified register
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
static uint32_t pwm_getreg(struct s32k1xx_pwmtimer_s *priv, int offset)
|
||||
{
|
||||
return getreg32(priv->base + offset);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pwm_putreg
|
||||
*
|
||||
* Description:
|
||||
* Read the value of an PWM timer register.
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - A reference to the PWM block status
|
||||
* offset - The offset to the register to read
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
static void pwm_putreg(struct s32k1xx_pwmtimer_s *priv, int offset,
|
||||
uint32_t value)
|
||||
{
|
||||
putreg32(value, priv->base + offset);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pwm_dumpregs
|
||||
*
|
||||
* Description:
|
||||
* Dump all timer registers.
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - A reference to the PWM block status
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_PWM_INFO
|
||||
static void pwm_dumpregs(struct s32k1xx_pwmtimer_s *priv, FAR const char *msg)
|
||||
{
|
||||
pwminfo("%s:\n", msg);
|
||||
pwminfo(" FTM%d_SC: %04x FTM%d_CNT: %04x FTM%d_MOD: %04x\n",
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_SC_OFFSET),
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_CNT_OFFSET),
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_MOD_OFFSET));
|
||||
pwminfo(" FTM%d_STATUS: %04x FTM%d_CONF: %04x\n",
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_STATUS_OFFSET),
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_CONF_OFFSET));
|
||||
pwminfo(" FTM%d_C0SC: %04x FTM%d_C0V: %04x\n",
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C0SC_OFFSET),
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C0V_OFFSET));
|
||||
pwminfo(" FTM%d_C1SC: %04x FTM%d_C1V: %04x\n",
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C1SC_OFFSET),
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C1V_OFFSET));
|
||||
pwminfo(" FTM%d_C2SC: %04x FTM%d_C2V: %04x\n",
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C2SC_OFFSET),
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C2V_OFFSET));
|
||||
pwminfo(" FTM%d_C3SC: %04x FTM%d_C3V: %04x\n",
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C3SC_OFFSET),
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C3V_OFFSET));
|
||||
pwminfo(" FTM%d_C4SC: %04x FTM%d_C4V: %04x\n",
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C4SC_OFFSET),
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C4V_OFFSET));
|
||||
pwminfo(" FTM%d_C5SC: %04x FTM%d_C5V: %04x\n",
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C5SC_OFFSET),
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C5V_OFFSET));
|
||||
pwminfo(" FTM%d_C6SC: %04x FTM%d_C6V: %04x\n",
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C6SC_OFFSET),
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C6V_OFFSET));
|
||||
pwminfo(" FTM%d_C7SC: %04x FTM%d_C7V: %04x\n",
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C7SC_OFFSET),
|
||||
priv->tpmid, pwm_getreg(priv, S32K1XX_FTM_C7V_OFFSET));
|
||||
}
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pwm_timer
|
||||
*
|
||||
* Description:
|
||||
* (Re-)initialize the timer resources and start the pulsed output
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - A reference to the lower half PWM driver state structure
|
||||
* info - A reference to the characteristics of the pulsed output
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
static int pwm_timer(FAR struct s32k1xx_pwmtimer_s *priv,
|
||||
FAR const struct pwm_info_s *info)
|
||||
{
|
||||
/* Calculated values */
|
||||
|
||||
uint32_t prescaler;
|
||||
uint32_t tpmclk;
|
||||
uint32_t modulo;
|
||||
uint32_t regval;
|
||||
uint32_t cv;
|
||||
uint8_t i;
|
||||
|
||||
static const uint8_t presc_values[8] = {1, 2, 4, 8, 16, 32, 64, 128};
|
||||
|
||||
/* Register contents */
|
||||
|
||||
DEBUGASSERT(priv != NULL && info != NULL);
|
||||
|
||||
pwminfo("FTM%d channel: %d frequency: %d duty: %08x\n",
|
||||
priv->tpmid, priv->channel, info->frequency, info->duty);
|
||||
|
||||
DEBUGASSERT(info->frequency > 0 && info->duty > 0 &&
|
||||
info->duty < uitoub16(100));
|
||||
|
||||
/* Calculate optimal values for the timer prescaler and for the timer modulo
|
||||
* register. If' frequency' is the desired frequency, then
|
||||
*
|
||||
* modulo = tpmclk / frequency
|
||||
* tpmclk = pclk / presc
|
||||
*
|
||||
* Or,
|
||||
*
|
||||
* modulo = pclk / presc / frequency
|
||||
*
|
||||
* There are many solutions to do this, but the best solution will be the
|
||||
* one that has the largest modulo value and the smallest prescaler value.
|
||||
* That is the solution that should give us the most accuracy in the timer
|
||||
* control. Subject to:
|
||||
*
|
||||
* 1 <= presc <= 128 (need to be 1, 2, 4, 8, 16, 32, 64, 128)
|
||||
* 1 <= modulo <= 65535
|
||||
*
|
||||
* So presc = pclk / 65535 / frequency would be optimal.
|
||||
*
|
||||
* Example:
|
||||
*
|
||||
* pclk = 24 MHz
|
||||
* frequency = 100 Hz
|
||||
*
|
||||
* prescaler = 24,000,000 / 65,535 / 100
|
||||
* = 3.6 (or 4 -- taking the ceiling always)
|
||||
* timclk = 24,000,000 / 4
|
||||
* = 6,000,000
|
||||
* modulo = 6,000,000 / 100
|
||||
* = 60,000
|
||||
*/
|
||||
|
||||
prescaler = (priv->pclk / info->frequency + 65534) / 65535;
|
||||
|
||||
for (i = 0; i < 7; i++)
|
||||
{
|
||||
if (prescaler <= presc_values[i])
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
prescaler = i;
|
||||
|
||||
tpmclk = priv->pclk / presc_values[prescaler];
|
||||
|
||||
modulo = tpmclk / info->frequency;
|
||||
if (modulo < 1)
|
||||
{
|
||||
modulo = 1;
|
||||
}
|
||||
else if (modulo > 65535)
|
||||
{
|
||||
modulo = 65535;
|
||||
}
|
||||
|
||||
/* Duty cycle:
|
||||
*
|
||||
* duty cycle = cv / modulo (fractional value)
|
||||
*/
|
||||
|
||||
cv = b16toi(info->duty * modulo + b16HALF);
|
||||
|
||||
pwminfo("FTM%d PCLK: %d frequency: %d FTMCLK: %d prescaler: %d modulo: %d c0v: %d\n",
|
||||
priv->tpmid, priv->pclk, info->frequency, tpmclk,
|
||||
presc_values[prescaler], modulo, cv);
|
||||
|
||||
/* Disable FTM and reset CNT before writing MOD and PS */
|
||||
|
||||
pwm_putreg(priv, S32K1XX_FTM_SC_OFFSET, FTM_SC_CLKS_DIS);
|
||||
pwm_putreg(priv, S32K1XX_FTM_CNT_OFFSET, 0);
|
||||
|
||||
/* Set the modulo value */
|
||||
|
||||
pwm_putreg(priv, S32K1XX_FTM_MOD_OFFSET, (uint16_t)modulo);
|
||||
|
||||
/* Set the duty cycle for channel specific */
|
||||
|
||||
switch (priv->channel)
|
||||
{
|
||||
case 0: /* PWM Mode configuration: Channel 0 */
|
||||
{
|
||||
pwm_putreg(priv, S32K1XX_FTM_C0SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB);
|
||||
pwm_putreg(priv, S32K1XX_FTM_C0V_OFFSET, (uint16_t) cv);
|
||||
}
|
||||
break;
|
||||
|
||||
case 1: /* PWM Mode configuration: Channel 1 */
|
||||
{
|
||||
pwm_putreg(priv, S32K1XX_FTM_C1SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB);
|
||||
pwm_putreg(priv, S32K1XX_FTM_C1V_OFFSET, (uint16_t) cv);
|
||||
}
|
||||
break;
|
||||
|
||||
case 2: /* PWM Mode configuration: Channel 2 */
|
||||
{
|
||||
pwm_putreg(priv, S32K1XX_FTM_C2SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB);
|
||||
pwm_putreg(priv, S32K1XX_FTM_C2V_OFFSET, (uint16_t) cv);
|
||||
}
|
||||
break;
|
||||
|
||||
case 3: /* PWM Mode configuration: Channel 3 */
|
||||
{
|
||||
pwm_putreg(priv, S32K1XX_FTM_C3SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB);
|
||||
pwm_putreg(priv, S32K1XX_FTM_C3V_OFFSET, (uint16_t) cv);
|
||||
}
|
||||
break;
|
||||
|
||||
case 4: /* PWM Mode configuration: Channel 4 */
|
||||
{
|
||||
pwm_putreg(priv, S32K1XX_FTM_C4SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB);
|
||||
pwm_putreg(priv, S32K1XX_FTM_C4V_OFFSET, (uint16_t) cv);
|
||||
}
|
||||
break;
|
||||
|
||||
case 5: /* PWM Mode configuration: Channel 5 */
|
||||
{
|
||||
pwm_putreg(priv, S32K1XX_FTM_C5SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB);
|
||||
pwm_putreg(priv, S32K1XX_FTM_C5V_OFFSET, (uint16_t) cv);
|
||||
}
|
||||
break;
|
||||
|
||||
case 6: /* PWM Mode configuration: Channel 6 */
|
||||
{
|
||||
pwm_putreg(priv, S32K1XX_FTM_C6SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB);
|
||||
pwm_putreg(priv, S32K1XX_FTM_C6V_OFFSET, (uint16_t) cv);
|
||||
}
|
||||
break;
|
||||
case 7: /* PWM Mode configuration: Channel 7 */
|
||||
{
|
||||
pwm_putreg(priv, S32K1XX_FTM_C7SC_OFFSET, FTM_CNSC_MSB | FTM_CNSC_ELSB);
|
||||
pwm_putreg(priv, S32K1XX_FTM_C7V_OFFSET, (uint16_t) cv);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
pwmerr("ERROR: No such channel: %d\n", priv->channel);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Set prescaler and enable clock */
|
||||
|
||||
regval = pwm_getreg(priv, S32K1XX_FTM_SC_OFFSET);
|
||||
regval &= ~(FTM_SC_PS_MASK);
|
||||
regval &= ~(FTM_SC_CLKS_MASK);
|
||||
regval |= prescaler | FTM_SC_CLKS_FTM;
|
||||
regval |= FTM_SC_PWMEN(priv->channel);
|
||||
pwm_putreg(priv, S32K1XX_FTM_SC_OFFSET, regval);
|
||||
|
||||
pwm_dumpregs(priv, "After starting");
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pwm_setup
|
||||
*
|
||||
* Description:
|
||||
* This method is called when the driver is opened. The lower half driver
|
||||
* should configure and initialize the device so that it is ready for use.
|
||||
* It should not, however, output pulses until the start method is called.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - A reference to the lower half PWM driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure
|
||||
*
|
||||
* Assumptions:
|
||||
* AHB1 or 2 clocking for the GPIOs and timer has already been configured
|
||||
* by the RCC logic at power up.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
|
||||
{
|
||||
FAR struct s32k1xx_pwmtimer_s *priv = (FAR struct s32k1xx_pwmtimer_s *)dev;
|
||||
|
||||
/* Note: The appropriate clock should for the right FTM device should
|
||||
* already be enabled in the board-specific s32k1xx_periphclocks.c file. */
|
||||
|
||||
pwminfo("FTM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
|
||||
pwm_dumpregs(priv, "Initially");
|
||||
|
||||
/* Configure the PWM output pin, but do not start the timer yet */
|
||||
|
||||
s32k1xx_pinconfig(priv->pincfg);
|
||||
pwm_dumpgpio(priv->pincfg, "PWM setup");
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pwm_shutdown
|
||||
*
|
||||
* Description:
|
||||
* This method is called when the driver is closed. The lower half driver
|
||||
* stop pulsed output, free any resources, disable the timer hardware, and
|
||||
* put the system into the lowest possible power usage state
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - A reference to the lower half PWM driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
|
||||
{
|
||||
FAR struct s32k1xx_pwmtimer_s *priv = (FAR struct s32k1xx_pwmtimer_s *)dev;
|
||||
uint32_t pincfg;
|
||||
|
||||
pwminfo("FTM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
|
||||
|
||||
/* Make sure that the output has been stopped */
|
||||
|
||||
pwm_stop(dev);
|
||||
|
||||
/* Then put the GPIO pin back to the default state */
|
||||
|
||||
pincfg = (priv->pincfg & ~(_PIN_MODE_MASK));
|
||||
pincfg |= GPIO_INPUT;
|
||||
s32k1xx_pinconfig(pincfg);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pwm_start
|
||||
*
|
||||
* Description:
|
||||
* (Re-)initialize the timer resources and start the pulsed output
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - A reference to the lower half PWM driver state structure
|
||||
* info - A reference to the characteristics of the pulsed output
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
|
||||
FAR const struct pwm_info_s *info)
|
||||
{
|
||||
FAR struct s32k1xx_pwmtimer_s *priv = (FAR struct s32k1xx_pwmtimer_s *)dev;
|
||||
return pwm_timer(priv, info);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pwm_stop
|
||||
*
|
||||
* Description:
|
||||
* Stop the pulsed output and reset the timer resources
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - A reference to the lower half PWM driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure
|
||||
*
|
||||
* Assumptions:
|
||||
* This function is called to stop the pulsed output at anytime. This
|
||||
* method is also called from the timer interrupt handler when a repetition
|
||||
* count expires... automatically stopping the timer.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
|
||||
{
|
||||
FAR struct s32k1xx_pwmtimer_s *priv = (FAR struct s32k1xx_pwmtimer_s *)dev;
|
||||
irqstate_t flags;
|
||||
|
||||
pwminfo("FTM%d\n", priv->tpmid);
|
||||
|
||||
/* Disable interrupts momentary to stop any ongoing timer processing and
|
||||
* to prevent any concurrent access to the reset register.
|
||||
*/
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
/* Disable further interrupts and stop the timer */
|
||||
|
||||
pwm_putreg(priv, S32K1XX_FTM_SC_OFFSET, FTM_SC_CLKS_DIS);
|
||||
pwm_putreg(priv, S32K1XX_FTM_CNT_OFFSET, 0);
|
||||
|
||||
/* Determine which timer channel to clear */
|
||||
|
||||
switch (priv->channel)
|
||||
{
|
||||
case 0:
|
||||
pwm_putreg(priv, S32K1XX_FTM_C0V_OFFSET, 0);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
pwm_putreg(priv, S32K1XX_FTM_C1V_OFFSET, 0);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
pwm_putreg(priv, S32K1XX_FTM_C2V_OFFSET, 0);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
pwm_putreg(priv, S32K1XX_FTM_C3V_OFFSET, 0);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
pwm_putreg(priv, S32K1XX_FTM_C4V_OFFSET, 0);
|
||||
break;
|
||||
|
||||
case 5:
|
||||
pwm_putreg(priv, S32K1XX_FTM_C5V_OFFSET, 0);
|
||||
break;
|
||||
|
||||
case 6:
|
||||
pwm_putreg(priv, S32K1XX_FTM_C6V_OFFSET, 0);
|
||||
break;
|
||||
|
||||
case 7:
|
||||
pwm_putreg(priv, S32K1XX_FTM_C7V_OFFSET, 0);
|
||||
break;
|
||||
|
||||
default:
|
||||
pwmerr("ERROR: No such channel: %d\n", priv->channel);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
pwm_dumpregs(priv, "After stop");
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pwm_ioctl
|
||||
*
|
||||
* Description:
|
||||
* Lower-half logic may support platform-specific ioctl commands
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - A reference to the lower half PWM driver state structure
|
||||
* cmd - The ioctl command
|
||||
* arg - The argument accompanying the ioctl command
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG_PWM_INFO
|
||||
FAR struct s32k1xx_pwmtimer_s *priv = (FAR struct s32k1xx_pwmtimer_s *)dev;
|
||||
|
||||
/* There are no platform-specific ioctl commands */
|
||||
|
||||
pwminfo("FTM%d\n", priv->tpmid);
|
||||
#endif
|
||||
return -ENOTTY;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: s32k1xx_pwminitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize one timer for use with the upper_level PWM driver.
|
||||
*
|
||||
* Input Parameters:
|
||||
* timer - A number identifying the timer use.
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, a pointer to the S32K1XX lower half PWM driver is returned.
|
||||
* NULL is returned on any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct pwm_lowerhalf_s *s32k1xx_pwminitialize(int timer)
|
||||
{
|
||||
FAR struct s32k1xx_pwmtimer_s *lower;
|
||||
int ret;
|
||||
uint32_t sysclk;
|
||||
|
||||
sysclk = s32k1xx_get_coreclk();
|
||||
ret = (sysclk == 0) ? -ENODEV : OK;
|
||||
|
||||
pwminfo("FTM%d\n", timer);
|
||||
|
||||
switch (timer)
|
||||
{
|
||||
#ifdef CONFIG_S32K1XX_FTM0_PWM
|
||||
case 0:
|
||||
g_pwm0dev.pclk = sysclk;
|
||||
lower = &g_pwm0dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S32K1XX_FTM1_PWM
|
||||
case 1:
|
||||
g_pwm1dev.pclk = sysclk;
|
||||
lower = &g_pwm1dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S32K1XX_FTM2_PWM
|
||||
case 2:
|
||||
g_pwm2dev.pclk = sysclk;
|
||||
lower = &g_pwm2dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S32K1XX_FTM3_PWM
|
||||
case 3:
|
||||
g_pwm3dev.pclk = sysclk;
|
||||
lower = &g_pwm3dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S32K1XX_FTM4_PWM
|
||||
case 4:
|
||||
g_pwm4dev.pclk = sysclk;
|
||||
lower = &g_pwm4dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S32K1XX_FTM5_PWM
|
||||
case 5:
|
||||
g_pwm5dev.pclk = sysclk;
|
||||
lower = &g_pwm5dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S32K1XX_FTM6_PWM
|
||||
case 6:
|
||||
g_pwm6dev.pclk = sysclk;
|
||||
lower = &g_pwm6dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S32K1XX_FTM7_PWM
|
||||
case 7:
|
||||
g_pwm7dev.pclk = sysclk;
|
||||
lower = &g_pwm7dev;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
pwmerr("ERROR: No such timer configured\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (ret != OK)
|
||||
{
|
||||
pwmerr("ERROR: FTM%d peripheral clock not available\n", timer);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return (FAR struct pwm_lowerhalf_s *)lower;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_S32K1XX_FTMn_PWM, n = 0,...,7 */
|
||||
346
arch/arm/src/s32k1xx/s32k1xx_pwm.h
Normal file
346
arch/arm/src/s32k1xx/s32k1xx_pwm.h
Normal file
@ -0,0 +1,346 @@
|
||||
/*****************************************************************************
|
||||
* arch/arm/src/s32k1xx/s32k1xx_pwm.h
|
||||
*
|
||||
* Copyright (C) 2013, 2016, 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
* Ken Fazzone <kfazz01@gmail.com>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_PWM_H
|
||||
#define __ARCH_ARM_SRC_S32K1XX_S32K1XX_PWM_H
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
*****************************************************************************/
|
||||
|
||||
/* Configuration *************************************************************/
|
||||
|
||||
/* Timer devices may be used for different purposes. One special purpose is
|
||||
* to generate modulated outputs for such things as motor control. If
|
||||
* CONFIG_S32K1XX_FTMn is defined then the CONFIG_S32K1XX_FTMn_PWM must also
|
||||
* be defined to indicate that timer "n" is intended to be used for pulsed
|
||||
* output signal generation.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_S32K1XX_FTM0
|
||||
# undef CONFIG_S32K1XX_FTM0_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_S32K1XX_FTM1
|
||||
# undef CONFIG_S32K1XX_FTM1_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_S32K1XX_FTM2
|
||||
# undef CONFIG_S32K1XX_FTM2_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_S32K1XX_FTM3
|
||||
# undef CONFIG_S32K1XX_FTM3_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_S32K1XX_FTM4
|
||||
# undef CONFIG_S32K1XX_FTM4_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_S32K1XX_FTM5
|
||||
# undef CONFIG_S32K1XX_FTM5_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_S32K1XX_FTM6
|
||||
# undef CONFIG_S32K1XX_FTM6_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_S32K1XX_FTM7
|
||||
# undef CONFIG_S32K1XX_FTM7_PWM
|
||||
#endif
|
||||
|
||||
/* Check if PWM support for any channel is enabled. */
|
||||
|
||||
#if defined(CONFIG_S32K1XX_FTM0_PWM) || defined(CONFIG_S32K1XX_FTM1_PWM) || \
|
||||
defined(CONFIG_S32K1XX_FTM2_PWM) || defined(CONFIG_S32K1XX_FTM3_PWM) || \
|
||||
defined(CONFIG_S32K1XX_FTM4_PWM) || defined(CONFIG_S32K1XX_FTM5_PWM) || \
|
||||
defined(CONFIG_S32K1XX_FTM6_PWM) || defined(CONFIG_S32K1XX_FTM7_PWM)
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include "hardware/s32k1xx_pinmux.h"
|
||||
|
||||
/* For each timer that is enabled for PWM usage, we need the following additional
|
||||
* configuration settings:
|
||||
*
|
||||
* CONFIG_S32K1XX_FTMx_CHANNEL - Specifies the timer output channel {0,..,7}
|
||||
* PWM_FTMx_PINCFG - One of the values defined in s32k1*_pinmux.h. In the case
|
||||
* where there are multiple pin selections, the correct setting must be provided
|
||||
* in the arch/board/board.h file.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_S32K1XX_FTM0_PWM
|
||||
# if !defined(CONFIG_S32K1XX_FTM0_CHANNEL)
|
||||
# error "CONFIG_S32K1XX_FTM0_CHANNEL must be provided"
|
||||
# elif CONFIG_S32K1XX_FTM0_CHANNEL == 0
|
||||
# define PWM_FTM0_PINCFG GPIO_FTM0_CH0OUT
|
||||
# elif CONFIG_S32K1XX_FTM0_CHANNEL == 1
|
||||
# define PWM_FTM0_PINCFG GPIO_FTM0_CH1OUT
|
||||
# elif CONFIG_S32K1XX_FTM0_CHANNEL == 2
|
||||
# define PWM_FTM0_PINCFG GPIO_FTM0_CH2OUT
|
||||
# elif CONFIG_S32K1XX_FTM0_CHANNEL == 3
|
||||
# define PWM_FTM0_PINCFG GPIO_FTM0_CH3OUT
|
||||
# elif CONFIG_S32K1XX_FTM0_CHANNEL == 4
|
||||
# define PWM_FTM0_PINCFG GPIO_FTM0_CH4OUT
|
||||
# elif CONFIG_S32K1XX_FTM0_CHANNEL == 5
|
||||
# define PWM_FTM0_PINCFG GPIO_FTM0_CH5OUT
|
||||
# elif CONFIG_S32K1XX_FTM0_CHANNEL == 6
|
||||
# define PWM_FTM0_PINCFG GPIO_FTM0_CH6OUT
|
||||
# elif CONFIG_S32K1XX_FTM0_CHANNEL == 7
|
||||
# define PWM_FTM0_PINCFG GPIO_FTM0_CH7OUT
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_S32K1XX_FTM0_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S32K1XX_FTM1_PWM
|
||||
# if !defined(CONFIG_S32K1XX_FTM1_CHANNEL)
|
||||
# error "CONFIG_S32K1XX_FTM1_CHANNEL must be provided"
|
||||
# elif CONFIG_S32K1XX_FTM1_CHANNEL == 0
|
||||
# define PWM_FTM1_PINCFG GPIO_FTM1_CH0OUT
|
||||
# elif CONFIG_S32K1XX_FTM1_CHANNEL == 1
|
||||
# define PWM_FTM1_PINCFG GPIO_FTM1_CH1OUT
|
||||
# elif CONFIG_S32K1XX_FTM1_CHANNEL == 2
|
||||
# define PWM_FTM1_PINCFG GPIO_FTM1_CH2OUT
|
||||
# elif CONFIG_S32K1XX_FTM1_CHANNEL == 3
|
||||
# define PWM_FTM1_PINCFG GPIO_FTM1_CH3OUT
|
||||
# elif CONFIG_S32K1XX_FTM1_CHANNEL == 4
|
||||
# define PWM_FTM1_PINCFG GPIO_FTM1_CH4OUT
|
||||
# elif CONFIG_S32K1XX_FTM1_CHANNEL == 5
|
||||
# define PWM_FTM1_PINCFG GPIO_FTM1_CH5OUT
|
||||
# elif CONFIG_S32K1XX_FTM1_CHANNEL == 6
|
||||
# define PWM_FTM1_PINCFG GPIO_FTM1_CH6OUT
|
||||
# elif CONFIG_S32K1XX_FTM1_CHANNEL == 7
|
||||
# define PWM_FTM1_PINCFG GPIO_FTM1_CH7OUT
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_S32K1XX_FTM1_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S32K1XX_FTM2_PWM
|
||||
# if !defined(CONFIG_S32K1XX_FTM2_CHANNEL)
|
||||
# error "CONFIG_S32K1XX_FTM2_CHANNEL must be provided"
|
||||
# elif CONFIG_S32K1XX_FTM2_CHANNEL == 0
|
||||
# define PWM_FTM2_PINCFG GPIO_FTM2_CH0OUT
|
||||
# elif CONFIG_S32K1XX_FTM2_CHANNEL == 1
|
||||
# define PWM_FTM2_PINCFG GPIO_FTM2_CH1OUT
|
||||
# elif CONFIG_S32K1XX_FTM2_CHANNEL == 2
|
||||
# define PWM_FTM2_PINCFG GPIO_FTM2_CH2OUT
|
||||
# elif CONFIG_S32K1XX_FTM2_CHANNEL == 3
|
||||
# define PWM_FTM2_PINCFG GPIO_FTM2_CH3OUT
|
||||
# elif CONFIG_S32K1XX_FTM2_CHANNEL == 4
|
||||
# define PWM_FTM2_PINCFG GPIO_FTM2_CH4OUT
|
||||
# elif CONFIG_S32K1XX_FTM2_CHANNEL == 5
|
||||
# define PWM_FTM2_PINCFG GPIO_FTM2_CH5OUT
|
||||
# elif CONFIG_S32K1XX_FTM2_CHANNEL == 6
|
||||
# define PWM_FTM2_PINCFG GPIO_FTM2_CH6OUT
|
||||
# elif CONFIG_S32K1XX_FTM2_CHANNEL == 7
|
||||
# define PWM_FTM2_PINCFG GPIO_FTM2_CH7OUT
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_S32K1XX_FTM2_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S32K1XX_FTM3_PWM
|
||||
# if !defined(CONFIG_S32K1XX_FTM3_CHANNEL)
|
||||
# error "CONFIG_S32K1XX_FTM3_CHANNEL must be provided"
|
||||
# elif CONFIG_S32K1XX_FTM3_CHANNEL == 0
|
||||
# define PWM_FTM3_PINCFG GPIO_FTM3_CH0OUT
|
||||
# elif CONFIG_S32K1XX_FTM3_CHANNEL == 1
|
||||
# define PWM_FTM3_PINCFG GPIO_FTM3_CH1OUT
|
||||
# elif CONFIG_S32K1XX_FTM3_CHANNEL == 2
|
||||
# define PWM_FTM3_PINCFG GPIO_FTM3_CH2OUT
|
||||
# elif CONFIG_S32K1XX_FTM3_CHANNEL == 3
|
||||
# define PWM_FTM3_PINCFG GPIO_FTM3_CH3OUT
|
||||
# elif CONFIG_S32K1XX_FTM3_CHANNEL == 4
|
||||
# define PWM_FTM3_PINCFG GPIO_FTM3_CH4OUT
|
||||
# elif CONFIG_S32K1XX_FTM3_CHANNEL == 5
|
||||
# define PWM_FTM3_PINCFG GPIO_FTM3_CH5OUT
|
||||
# elif CONFIG_S32K1XX_FTM3_CHANNEL == 6
|
||||
# define PWM_FTM3_PINCFG GPIO_FTM3_CH6OUT
|
||||
# elif CONFIG_S32K1XX_FTM3_CHANNEL == 7
|
||||
# define PWM_FTM3_PINCFG GPIO_FTM3_CH7OUT
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_S32K1XX_FTM3_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S32K1XX_FTM4_PWM
|
||||
# if !defined(CONFIG_S32K1XX_FTM4_CHANNEL)
|
||||
# error "CONFIG_S32K1XX_FTM4_CHANNEL must be provided"
|
||||
# elif CONFIG_S32K1XX_FTM4_CHANNEL == 0
|
||||
# define PWM_FTM4_PINCFG GPIO_FTM4_CH0OUT
|
||||
# elif CONFIG_S32K1XX_FTM4_CHANNEL == 1
|
||||
# define PWM_FTM4_PINCFG GPIO_FTM4_CH1OUT
|
||||
# elif CONFIG_S32K1XX_FTM4_CHANNEL == 2
|
||||
# define PWM_FTM4_PINCFG GPIO_FTM4_CH2OUT
|
||||
# elif CONFIG_S32K1XX_FTM4_CHANNEL == 3
|
||||
# define PWM_FTM4_PINCFG GPIO_FTM4_CH3OUT
|
||||
# elif CONFIG_S32K1XX_FTM4_CHANNEL == 4
|
||||
# define PWM_FTM4_PINCFG GPIO_FTM4_CH4OUT
|
||||
# elif CONFIG_S32K1XX_FTM4_CHANNEL == 5
|
||||
# define PWM_FTM4_PINCFG GPIO_FTM4_CH5OUT
|
||||
# elif CONFIG_S32K1XX_FTM4_CHANNEL == 6
|
||||
# define PWM_FTM4_PINCFG GPIO_FTM4_CH6OUT
|
||||
# elif CONFIG_S32K1XX_FTM4_CHANNEL == 7
|
||||
# define PWM_FTM4_PINCFG GPIO_FTM4_CH7OUT
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_S32K1XX_FTM4_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S32K1XX_FTM5_PWM
|
||||
# if !defined(CONFIG_S32K1XX_FTM5_CHANNEL)
|
||||
# error "CONFIG_S32K1XX_FTM5_CHANNEL must be provided"
|
||||
# elif CONFIG_S32K1XX_FTM5_CHANNEL == 0
|
||||
# define PWM_FTM5_PINCFG GPIO_FTM5_CH0OUT
|
||||
# elif CONFIG_S32K1XX_FTM5_CHANNEL == 1
|
||||
# define PWM_FTM5_PINCFG GPIO_FTM5_CH1OUT
|
||||
# elif CONFIG_S32K1XX_FTM5_CHANNEL == 2
|
||||
# define PWM_FTM5_PINCFG GPIO_FTM5_CH2OUT
|
||||
# elif CONFIG_S32K1XX_FTM5_CHANNEL == 3
|
||||
# define PWM_FTM5_PINCFG GPIO_FTM5_CH3OUT
|
||||
# elif CONFIG_S32K1XX_FTM5_CHANNEL == 4
|
||||
# define PWM_FTM5_PINCFG GPIO_FTM5_CH4OUT
|
||||
# elif CONFIG_S32K1XX_FTM5_CHANNEL == 5
|
||||
# define PWM_FTM5_PINCFG GPIO_FTM5_CH5OUT
|
||||
# elif CONFIG_S32K1XX_FTM5_CHANNEL == 6
|
||||
# define PWM_FTM5_PINCFG GPIO_FTM5_CH6OUT
|
||||
# elif CONFIG_S32K1XX_FTM5_CHANNEL == 7
|
||||
# define PWM_FTM5_PINCFG GPIO_FTM5_CH7OUT
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_S32K1XX_FTM5_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S32K1XX_FTM6_PWM
|
||||
# if !defined(CONFIG_S32K1XX_FTM6_CHANNEL)
|
||||
# error "CONFIG_S32K1XX_FTM6_CHANNEL must be provided"
|
||||
# elif CONFIG_S32K1XX_FTM6_CHANNEL == 0
|
||||
# define PWM_FTM6_PINCFG GPIO_FTM6_CH0OUT
|
||||
# elif CONFIG_S32K1XX_FTM6_CHANNEL == 1
|
||||
# define PWM_FTM6_PINCFG GPIO_FTM6_CH1OUT
|
||||
# elif CONFIG_S32K1XX_FTM6_CHANNEL == 2
|
||||
# define PWM_FTM6_PINCFG GPIO_FTM6_CH2OUT
|
||||
# elif CONFIG_S32K1XX_FTM6_CHANNEL == 3
|
||||
# define PWM_FTM6_PINCFG GPIO_FTM6_CH3OUT
|
||||
# elif CONFIG_S32K1XX_FTM6_CHANNEL == 4
|
||||
# define PWM_FTM6_PINCFG GPIO_FTM6_CH4OUT
|
||||
# elif CONFIG_S32K1XX_FTM6_CHANNEL == 5
|
||||
# define PWM_FTM6_PINCFG GPIO_FTM6_CH5OUT
|
||||
# elif CONFIG_S32K1XX_FTM6_CHANNEL == 6
|
||||
# define PWM_FTM6_PINCFG GPIO_FTM6_CH6OUT
|
||||
# elif CONFIG_S32K1XX_FTM6_CHANNEL == 7
|
||||
# define PWM_FTM6_PINCFG GPIO_FTM6_CH7OUT
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_S32K1XX_FTM6_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S32K1XX_FTM7_PWM
|
||||
# if !defined(CONFIG_S32K1XX_FTM7_CHANNEL)
|
||||
# error "CONFIG_S32K1XX_FTM7_CHANNEL must be provided"
|
||||
# elif CONFIG_S32K1XX_FTM7_CHANNEL == 0
|
||||
# define PWM_FTM7_PINCFG GPIO_FTM7_CH0OUT
|
||||
# elif CONFIG_S32K1XX_FTM7_CHANNEL == 1
|
||||
# define PWM_FTM7_PINCFG GPIO_FTM7_CH1OUT
|
||||
# elif CONFIG_S32K1XX_FTM7_CHANNEL == 2
|
||||
# define PWM_FTM7_PINCFG GPIO_FTM7_CH2OUT
|
||||
# elif CONFIG_S32K1XX_FTM7_CHANNEL == 3
|
||||
# define PWM_FTM7_PINCFG GPIO_FTM7_CH3OUT
|
||||
# elif CONFIG_S32K1XX_FTM7_CHANNEL == 4
|
||||
# define PWM_FTM7_PINCFG GPIO_FTM7_CH4OUT
|
||||
# elif CONFIG_S32K1XX_FTM7_CHANNEL == 5
|
||||
# define PWM_FTM7_PINCFG GPIO_FTM7_CH5OUT
|
||||
# elif CONFIG_S32K1XX_FTM7_CHANNEL == 6
|
||||
# define PWM_FTM7_PINCFG GPIO_FTM7_CH6OUT
|
||||
# elif CONFIG_S32K1XX_FTM7_CHANNEL == 7
|
||||
# define PWM_FTM7_PINCFG GPIO_FTM7_CH7OUT
|
||||
# else
|
||||
# error "Unsupported value of CONFIG_S32K1XX_FTM7_CHANNEL"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Types
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Data
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Function Prototypes
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: s32k1xx_pwminitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize one timer for use with the upper_level PWM driver.
|
||||
*
|
||||
* Input Parameters:
|
||||
* timer - A number identifying the timer use.
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, a pointer to the S32K1XX lower half PWM driver is returned.
|
||||
* NULL is returned on any failure.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
FAR struct pwm_lowerhalf_s *s32k1xx_pwminitialize(int timer);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_S32K1XX_FTMx_PWM */
|
||||
#endif /* __ARCH_ARM_SRC_S32K1XX_S32K1XX_PWM_H */
|
||||
Loading…
Reference in New Issue
Block a user