More paging changed
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2870 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
5170466f46
commit
3db7ecd49b
@ -252,7 +252,7 @@
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#define PTE_TINY_NPAGES 1024 /* 1024 Tiny PTE's per section */
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/* Default MMU flags for memory and IO */
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/* Default MMU flags for RAM memory, IO, vector region */
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#define MMU_MEMFLAGS \
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(PMD_TYPE_SECT|PMD_SECT_WB|PMD_BIT4|PMD_SECT_AP_WRITE|PMD_SECT_AP_READ)
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@ -64,9 +64,21 @@
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*/
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# if CONFIG_PAGING_PAGESIZE == 1024
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# define PTE_NPAGES PTE_TINY_NPAGES
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# define PTE_NPAGES PTE_TINY_NPAGES
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# define PG_L2_BASE_PADDR PGTABLE_FINE_BASE_PADDR
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# define PG_L2_BASE_VADDR PGTABLE_FINE_BASE_VADDR
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_FINE|PMD_BIT4|PTE_CACHEABLE)
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# define MMU_L2_TEXTFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_FINE|PMD_BIT4|PTE_CACHEABLE)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW|PTE_CACHEABLE)
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# elif CONFIG_PAGING_PAGESIZE == 4096
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# define PTE_NPAGES PTE_SMALL_NPAGES
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# define PG_L2_BASE_PADDR PGTABLE_COARSE_BASE_PADDR
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# define PG_L2_BASE_vADDR PGTABLE_COARSE_BASE_VADDR
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_COARSE|PMD_BIT4|PTE_CACHEABLE)
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# define MMU_L2_TEXTFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_COARSE|PMD_BIT4|PTE_CACHEABLE|PTE_BUFFERABLE)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
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# else
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# error "Need extended definitions for CONFIG_PAGING_PAGESIZE"
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# endif
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@ -81,177 +93,163 @@
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#ifdef __ASSEMBLY
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/****************************************************************************
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* Name: wrpte_coarse
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* Name: pg_map
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*
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* Description:
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* Write one L2 entry for a coarse PTE.
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* Write several, contiguous L2 page table entries. npages entries will be
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* written. This macro is used when CONFIG_PAGING is enable. This case,
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* it is used asfollows:
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*
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* Inputs (unmodified):
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* ctab - Register containing the address of the coarse page table
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* paddr - Physical address of the page to be mapped
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* vaddr - Virtual address of the page to be mapped
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* mmuflags - the MMU flags to use in the mapping
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*
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* Scratch registers (modified): tmp1, tmp2
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*
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****************************************************************************/
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#ifdef CONFIG_PAGING
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.macro wrpte_coarse, ctab, paddr, vaddr, mmuflags, tmp1, tmp2
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/* Get tmp1 = (paddr | mmuflags), the value to write into the table */
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orr \tmp1, \mmuflags, \paddr
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/* index = (vaddr & 0x000ff000) >> 12
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* offset = (vaddr & 0x000ff000) >> 10
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*/
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and \tmp2, \vaddr, #0x0000ff000
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/* Write value into table at ofset */
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str \tmp1, [\ctab, \tmp2, lsr #10]
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.endm
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#endif /* CONFIG_PAGING */
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/****************************************************************************
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* Name: wrpmd_coarse
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*
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* Description:
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* Write one L1 entry for a coarse page table.
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*
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* Inputs (unmodified unless noted):
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* paddr - Physical address of the section (modified)
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* vaddr - Virtual address of the section
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* mmuflags - MMU flags to use in the section mapping
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*
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* Scratch registers (modified): tmp1, tmp2, tmp3
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*
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****************************************************************************/
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#ifdef CONFIG_PAGING
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.macro wrpmd_coarse, paddr, vaddr, mmuflags, tmp1, tmp2
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/* tmp1 = the base of the L1 page table */
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ldr \tmp1, =PGTABLE_BASE_VADDR
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/* tmp2 = (paddr | mmuflags), the value to write into the page table */
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orr \paddr, \paddr, \mmuflags
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/* Write the value into the table at the correc offset.
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* table index = vaddr >> 20, offset = index << 2
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*/
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lsr \tmp2, \vaddr, #20
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str \paddr, [\tmp1, \tmp2, lsl #2]
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.endm
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#endif /* CONFIG_PAGING */
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/****************************************************************************
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* Name: wr_coarse
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*
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* Description:
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* Write one coarse L1 entry and all assocated L2 entries for a coarse
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* page table.
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* ldr r0, =PG_LOCKED_PBASE
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* ldr r1, =CONFIG_PAGING_NLOCKED
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* ldr r2, =MMUFLAGS
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* pg_map r0, r1, r2, r3, r4
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*
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* Inputs:
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* offset - coarse page table offset (unmodified)
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* paddr - Physical address of the section (modified)
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* vaddr - Virtual address of the section (modified)
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* paddr - The physical address of the start of the region to span. Must
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* be aligned to 1Mb section boundaries (modified)
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* npages - Number of pages to write in the section (modified)
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* mmuflags - L2 MMU FLAGS
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*
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* Scratch registers (modified): tmp1, tmp2, tmp3, tmp4, tmp5
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* Scratch registers (modified): tmp1, tmp2
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* tmp1 - Physical address in the L2 page table.
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* tmp2 - scratch
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*
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* On return, paddr and vaddr refer to the beginning of the
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* next section.
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* Assumptions:
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* - The MMU is not yet enabled
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* - The L2 page tables have been zeroed prior to calling this function
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* - pg_span has been called to initialize the L1 table.
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*
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****************************************************************************/
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#ifdef CONFIG_PAGING
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.macro wr_coarse, offset, paddr, vaddr, npages, tmp1, tmp2, tmp3, tmp4
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.macro pg_map, paddr, npages, mmuflags, tmp1, tmp2
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/* tmp1 = address of L2 table; tmp2 = MMU flags */
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/* tmp1 = Physical address of the start of the L2 page table
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* tmp2 = MMU flags
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*/
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ldr \tmp1, =PGTABLE_COARSE_BASE_VADDR
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add \tmp1, \offset, \paddr
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ldr \tmp2, =MMU_L2_VECTORFLAGS
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ldr \tmp1, =PG_L2_BASE_PADDR
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b 2f
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1:
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/* Write that L2 entry into the coarse page table */
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/* Write the one L2 entries. First, get tmp2 = (paddr | mmuflags),
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* the value to write into the L2 PTE
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*/
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wrpte_coarse \tmp1, \paddr, \vaddr, \tmp2, \tmp3, \tmp4
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orr \tmp2, \paddr, \mmuflags
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/* Update the physical and virtual addresses that will
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* correspond to the next table entry.
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/* Write value into table at the current table address */
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str \tmp2, [\tmp1], #4
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/* Update the physical addresses that will correspond to the next
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* table entry.
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*/
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add \paddr, \paddr, #CONFIG_PAGING_PAGESIZE
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add \vaddr, \vaddr, #CONFIG_PAGING_PAGESIZE
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2:
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/* Check if all of the pages have been written. If not, then
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* loop and write the next entry.
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*/
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add \tmp1, \tmp1, #4
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/* Decrement the number of pages written */
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sub \npages, \npages, #1
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cmn \npages #1
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bne 1b
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/* Write the section entry that refers to this coarse page
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* table.
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2:
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/* Check if all of the pages have been written. If not, then
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* loop and write the next PTE.
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*/
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ldr \tmp1, =PGTABLE_COARSE_BASE_PADDR
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ldr \tmp2, =MMU_L1_VECTORFLAGS
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add \tmp1, \offset, \tmp1
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wrpmd_coarse \tmp1, \vaddr, \tmp2, \tmp3, \tmp4
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cmp \npages, #0
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bgt 1b
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.endm
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#endif /* CONFIG_PAGING */
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/****************************************************************************
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* Name: wr_sections
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* Name: pg_span
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*
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* Description:
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* Write several, contiguous coarse L1 page table entries (and all
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* associated L2 page table entries). As many entries will be written as
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* many as needed to span npages.
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* Write several, contiguous unmapped coarse L1 page table entries. As
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* many entries will be written as many as needed to span npages. This
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* macro is used when CONFIG_PAGING is enable. This case, it is used as
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* follows:
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*
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* Inputs:
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* offset - coarse page table offset (modified)
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* paddr - Physical address of the section (modified)
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* vaddr - Virtual address of the section
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* npages - Number of pages to write in the section
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* ldr r0, =PG_LOCKED_PBASE
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* ldr r1, =(CONFIG_PAGING_NLOCKED+CONFIG_PAGING_NPAGES)
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* ldr r2, =MMU_FLAGS
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* pg_span r0, r1, r2, r3, r4
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*
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* Scratch registers (modified): tmp1, tmp2, tmp3, tmp4, tmp5
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* Inputs (unmodified unless noted):
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* addr - The virtual address of the start of the region to span. Must
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* be aligned to 1Mb section boundaries (modified)
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* npages - Number of pages to required to span that memory region (modified)
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* mmuflags - L1 MMU flags to use
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*
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* Scratch registers (modified):
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* addr, npages, tmp1, tmp2
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* addr - Physical address in the L1 page table.
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* npages - The number of pages remaining to be accounted for
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* tmp1 - L2 page table physical address
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* tmp2 - scratch
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*
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* Return:
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* Nothing of interest.
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*
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* Assumptions:
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* - The MMU is not yet enabled
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* - The L2 page tables have been zeroed prior to calling this function
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*
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****************************************************************************/
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#ifdef CONFIG_PAGING
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.macro wr_sections, offset, paddr, vaddr, npages, tmp1, tmp2, tmp3, tmp4
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b 2f
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1:
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/* Select the number of pages to write in this section. This number
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* will be 256 for coarse page tables or 1024 for fine/tiny page
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* tables (unless the npages argument indicates that there are fewer
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* than pages remaining to be mapped).
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.macro pg_span, addr, npages, mmuflags, tmp1, tmp2
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/* tmp1 = Physical address of the start of the L2 page table */
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ldr \tmp1, =PG_L2_BASE_PADDR
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/* Get addr = the L1 page table address coresponding to the virtual
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* address of the start of memory region to be mapped.
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*/
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cmp \npages, #(PTE_NPAGES-1) /* Check if npages < PTE_NPAGES */
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movls \tmp1, \npages /* YES.. tmp1 = npages */
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movls \npages, #0 /* npages = 0 */
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movhi \tmp1, #PTE_NPAGES /* NO.. tmp1 = PTE_NPAGES */
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subhi \npages, \npages, #PTE_NPAGES /* npages -= PTE_NPAGES */
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ldr \tmp2, =PGTABLE_BASE_PADDR
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lsr \addr, \addr, #20
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add \addr, \tmp2, \addr, lsl #2
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b 2f
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1:
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/* Write the L1 table entry that refers to this (unmapped) coarse page
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* table.
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*
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* tmp2 = (paddr | mmuflags), the value to write into the page table
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*/
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/* Write the L2 entries for this section */
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orr \tmp2, \tmp1, \mmuflags
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wr_coarse \offset, \paddr, \vaddr, \tmp1, \tmp1, \tmp2, \tmp3, \tmp4
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add \offset, \offset, #PT_SIZE
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/* Write the value into the L1 table at the correct offset. */
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str \tmp2, [\addr], #4
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/* Update the L2 page table address for the next L1 table entry. */
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add \tmp1, \tmp1, #PT_SIZE /* Next L2 page table start paddr */
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/* Update the number of pages that we have account for (with
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* non-mappings
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*/
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sub \npages, \npages, PTE_NPAGES
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2:
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/* Check if all of the pages have been written. If not, then
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* loop and write the next L1 entry.
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*/
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cmp \npages, #0
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bne 1b
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bgt 1b
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.endm
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#endif /* CONFIG_PAGING */
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#endif /* __ASSEMBLY */
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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#ifndef __ASSEMBLY
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#endif /* __ASSEMBLY */
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#endif /* __ARCH_ARM_SRC_ARM_PG_MACROS_H */
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@ -44,6 +44,11 @@
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#include "up_internal.h"
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#include "up_arch.h"
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#ifdef CONFIG_PAGING
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# include <nuttx/page.h>
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# include "pg_macros.h"
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#endif
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/**********************************************************************************
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* Configuration
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**********************************************************************************/
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@ -103,17 +108,6 @@
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#define RX_NSECTIONS ((CONFIG_DRAM_SIZE+0x000fffff) >> 20)
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/* If CONFIG_PAGING is defined, then
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* - RX_NPAGES determines the number of pages of size PAGESIZE that
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* are required to span the locked, Read/eXecute .text region.
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* - RW_NPAGES determines the number of pages of size PAGESIZE this
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* are required to span the Read/Write data region.
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*/
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#ifdef CONFIG_PAGING
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# define RX_NPAGES CONFIG_PAGING_LOCKEDPAGES
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#endif
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/****************************************************************************
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* Assembly Macros
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****************************************************************************/
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@ -185,6 +179,21 @@ __start:
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add r3, r1, r0 /* r3=flags + base */
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str r3, [r4, r0, lsr #18] /* identity mapping */
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#ifdef CONFIG_PAGING
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/* Populate the L1 table for the locked and paged text regions */
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ldr r0, =PG_LOCKED_PBASE
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ldr r1, =PG_TEXT_NPAGES
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ldr r2, =MMU_L1_TEXTFLAGS
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pg_span r0, r1, r2, r3, r4
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/* Populate the L2 table for the locked text region only */
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ldr r0, =PG_LOCKED_PBASE
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ldr r1, =CONFIG_PAGING_NLOCKED
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ldr r2, =MMU_L2_TEXTFLAGS
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pg_map r0, r1, r2, r3, r4
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#else
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/* Create a virtual single section mapping for the first MB of the .text
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* address space. Now, we have the first 1MB mapping to both phyical and
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* virtual addresses. The rest of the .text mapping will be completed in
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@ -198,7 +207,7 @@ __start:
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/* NOTE: No .data/.bss access should be attempted. This temporary mapping
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* can only be assumed to cover the initial .text region.
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*/
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#endif
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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/* The following logic will set up the ARM920/ARM926 for normal operation */
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@ -343,6 +352,24 @@ __start:
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mov r0, #0 /* flags + base = 0 */
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str r0, [r4, r3, lsr #18] /* Undo identity mapping */
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#if defined(CONFIG_PAGING)
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/* Populate the L1 table for the data regions */
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ldr r0, =PG_PAGED_PBASE
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ldr r1, =PG_DATA_NPAGED
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ldr r2, =MMU_L1_DATAFLAGS
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pg_span r0, r1, r2, r3, r4
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/* Populate the L2 table for the data region */
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ldr r0, =PG_PAGED_PBASE
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ldr r1, =PG_DATA_NPAGED
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ldr r2, =MMU_L2_DATAFLAGS
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pg_map r0, r1, r2, r3, r4
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#elif defined(CONFIG_BOOT_RUNFROMFLASH)
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# error "Logic not implemented"
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#else
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/* Now setup the pagetables for our normal SDRAM mappings mapped region.
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* We round NUTTX_START_VADDR down to the nearest megabyte boundary.
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*/
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@ -374,9 +401,6 @@ __start:
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* paging of the .text region, then the RAM-based .data/.bss/heap section
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* will still probably be located in a separate (virtual) address region.
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*/
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#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_PAGING)
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# error "Logic not implemented"
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#endif
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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@ -77,37 +77,73 @@
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#define PG_ALIGNUP(addr) (((addr) + PAGEMASK) & ~PAGEMASK)
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/* CONFIG_PAGING_NLOCKED - This is the number of locked pages in the memory
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* map. The size of locked address region will then be:
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* map. The size of locked address region will then be:
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*/
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#define PG_LOCKEDSIZE (CONFIG_PAGING_NLOCKED << PAGESHIFT)
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#define PG_LOCKED_SIZE (CONFIG_PAGING_NLOCKED << PAGESHIFT)
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/* PG_LOCKEDBASE - May be defined to determine the base address
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* of the locked page regions (lowest in memory). If PG_LOCKEDBASE
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* is not defined, it will be set to CONFIG_DRAM_VSTART (i.e., assuming that
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* the base address of the locked region is at the virtual address of the
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* beginning of RAM).
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/* CONFIG_PAGING_LOCKED_P/VBASE - May be defined to determine the base
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* address of the locked page regions (lowest in memory). If both are not
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* not defined, then this logic will be set to then to CONFIG_DRAM_START
|
||||
* and CONFIG_DRAM_VSTART (i.e., assuming that the base address of the
|
||||
* locked region is at the virtual address of the beginning of RAM).
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_PAGING_LOCKEDBASE
|
||||
# define PG_LOCKEDBASE CONFIG_PAGING_LOCKEDBASE
|
||||
#if defined(CONFIG_PAGING_LOCKED_PBASE) && defined(CONFIG_PAGING_LOCKED_VBASE)
|
||||
# define PG_LOCKED_PBASE CONFIG_PAGING_LOCKED_PBASE
|
||||
# define PG_LOCKED_VBASE CONFIG_PAGING_LOCKED_VBASE
|
||||
#else
|
||||
# define PG_LOCKEDBASE CONFIG_DRAM_VSTART
|
||||
# define PG_LOCKED_PBASE CONFIG_DRAM_START
|
||||
# define PG_LOCKED_VBASE CONFIG_DRAM_VSTART
|
||||
#endif
|
||||
|
||||
#define PG_LOCKEDEND (PG_LOCKEDBASE + PG_LOCKEDSIZE)
|
||||
#define PG_LOCKED_PEND (PG_LOCKED_PBASE + PG_LOCKED_SIZE)
|
||||
#define PG_LOCKED_VEND (PG_LOCKED_VBASE + PG_LOCKED_SIZE)
|
||||
|
||||
#if (PG_LOCKEDBASE & PAGEMASK) != 0
|
||||
#if (PG_LOCKED_PBASE & PAGEMASK) != 0 || (PG_LOCKED_VBASE & PAGEMASK) != 0
|
||||
# error "Base address of the locked region is not page aligned"
|
||||
#endif
|
||||
|
||||
/* CONFIG_PAGING_NPAGES - The number of pages in the paged region of the
|
||||
* memory map. This paged region then begins and ends at:
|
||||
/* CONFIG_PAGING_NPAGED - This is the number of paged pages in the memory
|
||||
* map. The size of paged address region will then be:
|
||||
*/
|
||||
|
||||
#define PG_PAGEDSIZE (CONFIG_PAGING_NPAGES << PAGESHIFT)
|
||||
#define PG_PAGEDBASE PG_LOCKEDEND
|
||||
#define PG_PAGEDEND (PG_PAGEDBASE + PG_PAGEDSIZE)
|
||||
#define PG_PAGED_SIZE (CONFIG_PAGING_NPAGED << PAGESHIFT)
|
||||
|
||||
/* This positions the paging Read-Only text section */
|
||||
|
||||
#define PG_PAGED_PBASE PG_LOCKED_PEND
|
||||
#define PG_PAGED_VBASE PG_LOCKED_VEND
|
||||
#define PG_PAGED_PEND (PG_PAGED_PBASE + PG_PAGED_SIZE)
|
||||
#define PG_PAGED_VEND (PG_PAGED_VBASE + PG_PAGED_SIZE)
|
||||
|
||||
/* CONFIG_PAGING_NDATA - This is the number of data pages in the memory
|
||||
* map. The size of data address region will then be:
|
||||
*/
|
||||
|
||||
#define PG_TEXT_NPAGES (CONFIG_PAGING_NLOCKED + CONFIG_PAGING_NPAGED)
|
||||
#define PG_RAM_PAGES (CONFIG_DRAM_SIZE >> PAGESHIFT)
|
||||
#if PG_RAM_PAGES <= PG_TEXT_NPAGES
|
||||
# error "Not enough memory for this page layout"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PAGING_NDATA
|
||||
# PG_DATA_NPAGED CONFIG_PAGING_NDATA
|
||||
#else
|
||||
# PG_DATA_NPAGED (PG_RAM_PAGES - PG_TEXT_NPAGES)
|
||||
#endif
|
||||
|
||||
#define PG_DATA_SIZE (CONFIG_PAGING_NPAGED << PAGESHIFT)
|
||||
|
||||
/* This positions the Read/Write data region */
|
||||
|
||||
#if defined(CONFIG_PAGING_DATA_PBASE) && defined(CONFIG_PAGING_DATA_VBASE)
|
||||
# define PG_DATA_PBASE CONFIG_PAGING_DATA_PBASE
|
||||
# define PG_DATA_VBASE CONFIG_PAGING_DATA_VBASE
|
||||
#else
|
||||
# define PG_DATA_PBASE PG_LOCKED_PEND
|
||||
# define PG_DATA_VBASE PG_LOCKED_VEND
|
||||
#endif
|
||||
|
||||
/* CONFIG_PAGING_DEFPRIO - The default, minimum priority of the page fill
|
||||
* worker thread. The priority of the page fill work thread will be boosted
|
||||
|
||||
Loading…
Reference in New Issue
Block a user