Add system registers
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1686 42af7a65-404d-4744-a932-0658087f49c3
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@ -41,6 +41,7 @@
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************************************************************************************/
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#include "imx_memorymap.h"
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#include "imx_system.h"
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#include "imx_wdog.h"
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#include "imx_timer.h"
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#include "imx_rtc.h"
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@ -49,6 +49,7 @@
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/* -0x000fffff Double Map Image 1Mb */
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/* -0x001fffff Bootstrap ROM 1Mb */
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#define IMX_PERIPHERALS_PSECTION 0x00200000 /* -0x002fffff Peripherals 1Mb */
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#define IMX_ESRAM_PSECTION 0x00300000 /* -0x003fffff Embedded SRAM 128Kb */
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#define IMX_SDRAM0_PSECTION 0x08000000 /* -0x0bffffff SDRAM0 (CSD0) 64Mb */
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#define IMX_SDRAM1_PSECTION 0x0c000000 /* -0x0fffffff SDRAM1 (CSD1) 64Mb */
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#define IMX_FLASH_PSECTION 0x10000000 /* -0x11ffffff FLASH (CS0) 32Mb */
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117
arch/arm/src/imx/imx_system.h
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117
arch/arm/src/imx/imx_system.h
Executable file
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/************************************************************************************
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* arch/arm/src/imx/imx_system.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_IMX_SYSTEM_H
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#define __ARCH_ARM_IMX_SYSTEM_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* AIPI Register Offsets ************************************************************/
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#define AIPI_PSR0_OFFSET 0x0000 /* Peripheral Size Register 0 */
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#define AIPI_PSR1_OFFSET 0x0004 /* Peripheral Size Register 1 */
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#define AIPI_PAR_OFFSET 0x0008 /* Peripheral Access Register */
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/* AIPI Register Addresses **********************************************************/
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#define IMX_AIPI1_PSR0 (IMX_AIPI1_VBASE + AIPI_PSR0_OFFSET)
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#define IMX_AIPI1_PSR1 (IMX_AIPI1_VBASE + AIPI_PSR1_OFFSET)
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#define IMX_AIPI1_PAR (IMX_AIPI1_VBASE + AIPI_PAR_OFFSET)
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#define IMX_AIPI2_PSR0 (IMX_AIP2_VBASE + AIPI_PSR0_OFFSET)
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#define IMX_AIPI2_PSR1 (IMX_AIP2_VBASE + AIPI_PSR1_OFFSET)
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#define IMX_AIPI2_PAR (IMX_AIP2_VBASE + 0xAIPI_PAR_OFFSET)
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/* AIPI Register Bit Definitions ****************************************************/
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/* PLL Register Offsets *************************************************************/
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#define PLL_CSCR_OFFSET 0x0000 /* Clock Source Control Register */
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#define PLL_MCTL0_OFFSET 0x0004 /* MCU PLL Control Register 0 */
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#define PLL_MCTL1_OFFSET 0x0008 /* MCU PLL Control Register 1 */
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#define PLL_SPCTL0_OFFSET 0x000c /* System PLL Control Register 0 */
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#define PLL_SPCTL1_OFFSET 0x0010 /* System PLL Control Register 1 */
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#define PLL_PCDR_OFFSET 0x0020 /* Peripherial Clock Divider Register */
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/* PLL Register Addresses ***********************************************************/
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#define IMX_PLL_CSCR (IMX_PLL_VBASE + PLL_CSCR_OFFSET)
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#define IMX_PLL_MCTL0 (IMX_PLL_VBASE + PLL_MCTL0_OFFSET)
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#define IMX_PLL_MCTL1 (IMX_PLL_VBASE + PLL_MCTL1_OFFSET)
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#define IMX_PLL_SPCTL0 (IMX_PLL_VBASE + PLL_SPCTL0_OFFSET)
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#define IMX_PLL_SPCTL1 (IMX_PLL_VBASE + PLL_SPCTL1_OFFSET)
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#define IMX_PLL_PCDR (IMX_PLL_VBASE + PLL_PCDR_OFFSET)
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/* PLL Register Bit Definitions *****************************************************/
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/* SC Register Offsets **************************************************************/
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#define SC_RSR_OFFSET 0x0000 /* Reset Source Register */
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#define SC_SIDR_OFFSET 0x0004 /* Silicon ID Register */
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#define SC_FMCR_OFFSET 0x0008 /* Function Muxing Control Register */
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#define SC_GPCR_OFFSET 0x000c /* Global Peripherial Control Regiser */
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/* SC Register Addresses ************************************************************/
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#define IMX_SC_RSR (IMX_SC_VBASE + SC_RSR_OFFSET)
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#define IMX_SC_SIDR (IMX_SC_VBASE + SC_SIDR_OFFSET)
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#define IMX_SC_FMCR (IMX_SC_VBASE + SC_FMCR_OFFSET)
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#define IMX_SC_GPCR (IMX_SC_VBASE + SC_GPCR_OFFSET)
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/* SC Register Bit Definitions ******************************************************/
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/* SDRAMC Register Offsets **********************************************************/
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#define SDRAMC_SDCTL0_OFFSET 0x0000
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#define SDRAMC_SDCTL1_OFFSET 0x0004
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/* SDRAMC Register Addresses ********************************************************/
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#define IMX_SDRAMC_SDCTL0 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL0_OFFSET)
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#define IMX_SDRAMC_SDCTL1 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL1_OFFSET))
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/* SDRAMC Register Bit Definitions **************************************************/
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_IMX_SYSTEM_H */
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