boards/stm32wl5jc: add support for board ipcc

Allows to easily enable and configure ipcc for board.

Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>

boards/arm/stm32wl5/nucleo-wl55jc/Kconfig

@@ -24,6 +24,127 @@ config ARCH_BOARD_ENABLE_CPU2
 		When enabled, CPU2 (cortex-m0) will be started up. CPU2
 		will be booted after all initialization on CPU1 is done.
 
+menuconfig ARCH_BOARD_IPCC
+	bool "Enabled IPCC"
+	select IPCC
+	select STM32WL5_IPCC
+	default n
+	---help---
+		Enables IPCC (inter processor communication controller)
+		to exchange data between CPU1 and CPU2. Channels are
+		indexed from 0. IPCC will be accessible as character
+		device under "/dev/ipccN" path, where N is an ipcc channel.
+
+if ARCH_BOARD_IPCC
+
+comment "IPCC buffering is off, enable IPCC_BUFFERED to configure buffers"
+	depends on !IPCC_BUFFERED
+
+comment "IPCC channel 1 enabled by default"
+
+config ARCH_BOARD_IPCC_CHAN1_RXBUF
+	int "Channel 1 RX buffer size"
+	default 256
+	depends on IPCC_BUFFERED
+
+config ARCH_BOARD_IPCC_CHAN1_TXBUF
+	int "Channel 1 TX buffer size"
+	default 256
+	depends on IPCC_BUFFERED
+
+config ARCH_BOARD_IPCC_CHAN2
+	bool "Enable channel 2"
+	default n
+	select STM32WL5_IPCC_CHAN2
+
+if ARCH_BOARD_IPCC_CHAN2
+
+config ARCH_BOARD_IPCC_CHAN2_RXBUF
+	int "Channel 2 RX buffer size"
+	default 256
+	depends on IPCC_BUFFERED
+
+config ARCH_BOARD_IPCC_CHAN2_TXBUF
+	int "Channel 2 TX buffer size"
+	default 256
+	depends on IPCC_BUFFERED
+
+config ARCH_BOARD_IPCC_CHAN3
+	bool "Enable channel 3"
+	default n
+	select STM32WL5_IPCC_CHAN3
+
+if ARCH_BOARD_IPCC_CHAN3
+
+config ARCH_BOARD_IPCC_CHAN3_RXBUF
+	int "Channel 3 RX buffer size"
+	default 256
+	depends on IPCC_BUFFERED
+
+config ARCH_BOARD_IPCC_CHAN3_TXBUF
+	int "Channel 3 TX buffer size"
+	default 256
+	depends on IPCC_BUFFERED
+
+config ARCH_BOARD_IPCC_CHAN4
+	bool "Enable channel 4"
+	default n
+	select STM32WL5_IPCC_CHAN4
+
+if ARCH_BOARD_IPCC_CHAN4
+
+config ARCH_BOARD_IPCC_CHAN4_RXBUF
+	int "Channel 4 RX buffer size"
+	default 256
+	depends on IPCC_BUFFERED
+
+config ARCH_BOARD_IPCC_CHAN4_TXBUF
+	int "Channel 4 TX buffer size"
+	default 256
+	depends on IPCC_BUFFERED
+
+config ARCH_BOARD_IPCC_CHAN5
+	bool "Enable channel 5"
+	default n
+	select STM32WL5_IPCC_CHAN5
+
+if ARCH_BOARD_IPCC_CHAN5
+
+config ARCH_BOARD_IPCC_CHAN5_RXBUF
+	int "Channel 5 RX buffer size"
+	default 256
+	depends on IPCC_BUFFERED
+
+config ARCH_BOARD_IPCC_CHAN5_TXBUF
+	int "Channel 5 TX buffer size"
+	default 256
+	depends on IPCC_BUFFERED
+
+config ARCH_BOARD_IPCC_CHAN6
+	bool "Enable channel 6"
+	default n
+	select STM32WL5_IPCC_CHAN6
+
+if ARCH_BOARD_IPCC_CHAN6
+
+config ARCH_BOARD_IPCC_CHAN2_RXBUF
+	int "Channel 6 RX buffer size"
+	default 256
+	depends on IPCC_BUFFERED
+
+config ARCH_BOARD_IPCC_CHAN6_TXBUF
+	int "Channel 6 TX buffer size"
+	default 256
+	depends on IPCC_BUFFERED
+
+endif # ARCH_BOARD_IPCC_CHAN6
+endif # ARCH_BOARD_IPCC_CHAN5
+endif # ARCH_BOARD_IPCC_CHAN4
+endif # ARCH_BOARD_IPCC_CHAN3
+endif # ARCH_BOARD_IPCC_CHAN2
+
+endif # ARCH_BOARD_IPCC
+
 menuconfig ARCH_BOARD_FLASH_MOUNT
 	bool "Enable FLASH partitioning and mounting"
 	depends on !DISABLE_MOUNTPOINT

boards/arm/stm32wl5/nucleo-wl55jc/src/Makefile

@@ -38,10 +38,14 @@ ifeq ($(CONFIG_SPI_DRIVER),y)
   CSRCS += stm32_spi.c
 endif
 
+CSRCS-$(CONFIG_ARCH_BOARD_IPCC) = stm32_ipcc.c
+
 ifeq ($(CONFIG_VIDEO_FB),y)
 ifeq ($(CONFIG_LCD_SSD1680),y)
   CSRCS += stm32_ssd1680.c
 endif
 endif
 
+CSRCS += $(CSRCS-y)
+
 include $(TOPDIR)/boards/Board.mk

boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h

@@ -155,7 +155,8 @@ void board_leds_initialize(void);
 
 int stm32wl5_flash_init(void);
 
-/* Name: stm32wl5_spidev_initialize
+/****************************************************************************
+ * Name: stm32wl5_spidev_initialize
  *
  * Description:
  *   Initialize SPIs
@@ -164,4 +165,14 @@ int stm32wl5_flash_init(void);
 
 void stm32wl5_spidev_initialize(void);
 
+/****************************************************************************
+ * Name: ipcc_init
+ *
+ * Description:
+ *   Initializes configured IPCC channels.
+ *
+ ****************************************************************************/
+
+int ipcc_init(void);
+
 #endif /* __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H */

boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_appinit.c

@@ -133,6 +133,16 @@ int board_app_initialize(uintptr_t arg)
     }
 #endif
 
+#if defined(CONFIG_ARCH_BOARD_IPCC)
+  /* Register IPCC driver */
+
+  ret = ipcc_init();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: ipcc_init() failed\n");
+    }
+#endif
+
 #if defined(CONFIG_ARCH_BOARD_ENABLE_CPU2)
   /* Start second CPU */
 

boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c

@@ -0,0 +1,180 @@
+/****************************************************************************
+ * boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/ipcc.h>
+#include <debug.h>
+
+#include <stm32wl5_ipcc.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Define default values for macros if they are not define in config */
+
+#ifndef CONFIG_ARCH_BOARD_IPCC_CHAN1_RXBUF
+#  define CONFIG_ARCH_BOARD_IPCC_CHAN1_RXBUF 0
+#endif
+
+#ifndef CONFIG_ARCH_BOARD_IPCC_CHAN1_TXBUF
+#  define CONFIG_ARCH_BOARD_IPCC_CHAN1_TXBUF 0
+#endif
+
+#ifndef CONFIG_ARCH_BOARD_IPCC_CHAN2_RXBUF
+#  define CONFIG_ARCH_BOARD_IPCC_CHAN2_RXBUF 0
+#endif
+
+#ifndef CONFIG_ARCH_BOARD_IPCC_CHAN2_TXBUF
+#  define CONFIG_ARCH_BOARD_IPCC_CHAN2_TXBUF 0
+#endif
+
+#ifndef CONFIG_ARCH_BOARD_IPCC_CHAN3_RXBUF
+#  define CONFIG_ARCH_BOARD_IPCC_CHAN3_RXBUF 0
+#endif
+
+#ifndef CONFIG_ARCH_BOARD_IPCC_CHAN3_TXBUF
+#  define CONFIG_ARCH_BOARD_IPCC_CHAN3_TXBUF 0
+#endif
+
+#ifndef CONFIG_ARCH_BOARD_IPCC_CHAN4_RXBUF
+#  define CONFIG_ARCH_BOARD_IPCC_CHAN4_RXBUF 0
+#endif
+
+#ifndef CONFIG_ARCH_BOARD_IPCC_CHAN4_TXBUF
+#  define CONFIG_ARCH_BOARD_IPCC_CHAN4_TXBUF 0
+#endif
+
+#ifndef CONFIG_ARCH_BOARD_IPCC_CHAN5_RXBUF
+#  define CONFIG_ARCH_BOARD_IPCC_CHAN5_RXBUF 0
+#endif
+
+#ifndef CONFIG_ARCH_BOARD_IPCC_CHAN5_TXBUF
+#  define CONFIG_ARCH_BOARD_IPCC_CHAN5_TXBUF 0
+#endif
+
+#ifndef CONFIG_ARCH_BOARD_IPCC_CHAN6_RXBUF
+#  define CONFIG_ARCH_BOARD_IPCC_CHAN6_RXBUF 0
+#endif
+
+#ifndef CONFIG_ARCH_BOARD_IPCC_CHAN6_TXBUF
+#  define CONFIG_ARCH_BOARD_IPCC_CHAN6_TXBUF 0
+#endif
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int init_ipcc(int chan, size_t rxbuflen, size_t txbuflen);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: init_ipcc
+ *
+ * Description:
+ *   Initializes IPCC channel with tx and rx buffer sizes. If ipcc is
+ *   unbuffered, rxbuflen and txbuflen are ignored.
+ *
+ * Input Parameters:
+ *   chan - channel number, indexed from 0
+ *   rxbuflen - size of rxbuffer for buffered transactions
+ *   txbuflen - size of txbuffer for buffered transactions
+ *
+ * Returned Value:
+ *   0 on success or -1 on errors.
+ *
+ ****************************************************************************/
+
+static int init_ipcc(int chan, size_t rxbuflen, size_t txbuflen)
+{
+  struct ipcc_lower_s *ipcc;
+  int ret;
+
+  if ((ipcc = stm32wl5_ipcc_init(chan)) == NULL)
+    {
+      syslog(LOG_ERR, "ERROR: stm32wl5_ipcc_init(%d) failed\n", chan);
+      return -1;
+    }
+
+#ifdef CONFIG_IPCC_BUFFERED
+  ret = ipcc_register(ipcc, rxbuflen, txbuflen);
+#else
+  UNUSED(rxbuflen);
+  UNUSED(txbuflen);
+  ret = ipcc_register(ipcc);
+#endif
+
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: ipcc_register() failed: %d, channel: %d\n",
+             ret, chan);
+      return -1;
+    }
+
+  return 0;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+int ipcc_init(void)
+{
+  int ret = 0;
+
+  /* First channel is always enabled in IPCC is enabled */
+
+  ret |= init_ipcc(0, CONFIG_ARCH_BOARD_IPCC_CHAN1_RXBUF,
+                   CONFIG_ARCH_BOARD_IPCC_CHAN1_TXBUF);
+
+#ifdef CONFIG_ARCH_BOARD_IPCC_CHAN2
+  ret |= init_ipcc(1, CONFIG_ARCH_BOARD_IPCC_CHAN2_RXBUF,
+                   CONFIG_ARCH_BOARD_IPCC_CHAN2_TXBUF);
+#endif
+
+#ifdef CONFIG_ARCH_BOARD_IPCC_CHAN3
+  ret |= init_ipcc(2, CONFIG_ARCH_BOARD_IPCC_CHAN3_RXBUF,
+                   CONFIG_ARCH_BOARD_IPCC_CHAN3_TXBUF);
+#endif
+
+#ifdef CONFIG_ARCH_BOARD_IPCC_CHAN4
+  ret |= init_ipcc(3, CONFIG_ARCH_BOARD_IPCC_CHAN4_RXBUF,
+                   CONFIG_ARCH_BOARD_IPCC_CHAN4_TXBUF);
+#endif
+
+#ifdef CONFIG_ARCH_BOARD_IPCC_CHAN5
+  ret |= init_ipcc(4, CONFIG_ARCH_BOARD_IPCC_CHAN5_RXBUF,
+                   CONFIG_ARCH_BOARD_IPCC_CHAN5_TXBUF);
+#endif
+
+#ifdef CONFIG_ARCH_BOARD_IPCC_CHAN6
+  ret |= init_ipcc(5, CONFIG_ARCH_BOARD_IPCC_CHAN6_RXBUF,
+                   CONFIG_ARCH_BOARD_IPCC_CHAN6_TXBUF);
+#endif
+
+  return ret;
+}