Merged in paulpatience/nuttx-arch/stm32_adc (pull request #42)
STM32 ADC: Add DMA support for STM32F30xxx
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commit
3e4fb7a60d
@ -182,6 +182,19 @@
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# define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_NODMA
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#endif
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#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define ADC_DMA_CONTROL_WORD (DMA_SCR_MSIZE_16BITS | \
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DMA_SCR_PSIZE_16BITS | \
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DMA_SCR_MINC | \
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DMA_SCR_CIRC | \
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DMA_SCR_DIR_P2M)
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#else
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# define ADC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \
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DMA_CCR_PSIZE_16BITS | \
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DMA_CCR_MINC | \
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DMA_CCR_CIRC)
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#endif
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/* DMA channels and interface values differ for the F1 and F4 families */
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#if defined(CONFIG_STM32_STM32F10XX)
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@ -1923,8 +1936,6 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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if (priv->hasdma)
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{
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uint32_t ccr;
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/* Stop and free DMA if it was started before */
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if (priv->dma != NULL)
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@ -1934,17 +1945,12 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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}
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priv->dma = stm32_dmachannel(priv->dmachan);
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ccr = DMA_SCR_MSIZE_16BITS | /* Memory size */
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DMA_SCR_PSIZE_16BITS | /* Peripheral size */
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DMA_SCR_MINC | /* Memory increment mode */
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DMA_SCR_CIRC | /* Circular buffer */
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DMA_SCR_DIR_P2M; /* Read from peripheral */
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stm32_dmasetup(priv->dma,
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priv->base + STM32_ADC_DR_OFFSET,
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(uint32_t)priv->dmabuffer,
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priv->nchannels,
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ccr);
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ADC_DMA_CONTROL_WORD);
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stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false);
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}
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@ -280,15 +280,7 @@
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#undef ADC_HAVE_DMA
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#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \
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defined(CONFIG_STM32_ADC3_DMA) || defined(CONFIG_STM32_ADC4_DMA)
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# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define ADC_HAVE_DMA 1
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# else
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# warning "DMA is only supported for the STM32 F2/F3/F4 families"
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# undef CONFIG_STM32_ADC1_DMA
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# undef CONFIG_STM32_ADC2_DMA
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# undef CONFIG_STM32_ADC3_DMA
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# undef CONFIG_STM32_ADC4_DMA
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# endif
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# define ADC_HAVE_DMA 1
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#endif
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#ifdef CONFIG_STM32_ADC1_DMA
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