Add support for R61505U LCD controller on HY-mini STM32v board
This commit is contained in:
parent
cf3ba4b7cc
commit
3e8e275b53
@ -4,4 +4,13 @@
|
|||||||
#
|
#
|
||||||
|
|
||||||
if ARCH_BOARD_HYMINI_STM32V
|
if ARCH_BOARD_HYMINI_STM32V
|
||||||
|
|
||||||
|
config LCD_R61505U
|
||||||
|
bool "LCD Based on R61505U LCD Controller"
|
||||||
|
default n
|
||||||
|
depends on NX_LCDDRIVER && !LCD_SSD1289
|
||||||
|
---help---
|
||||||
|
Enables HY-Mini STM32v support for any LCD based on the R61505U,
|
||||||
|
LCD Controller.
|
||||||
|
|
||||||
endif
|
endif
|
||||||
|
@ -43,8 +43,12 @@ AOBJS = $(ASRCS:.S=$(OBJEXT))
|
|||||||
|
|
||||||
CSRCS = up_boot.c up_leds.c up_buttons.c up_spi.c up_usbdev.c
|
CSRCS = up_boot.c up_leds.c up_buttons.c up_spi.c up_usbdev.c
|
||||||
|
|
||||||
ifeq ($(CONFIG_NX_LCDDRIVER),y)
|
ifeq ($(CONFIG_LCD_SSD1289),y)
|
||||||
CSRCS += up_ssd1289.c
|
CSRCS += up_ssd1289.c
|
||||||
|
else
|
||||||
|
ifeq ($(CONFIG_LCD_R61505U),y)
|
||||||
|
CSRCS += up_r61505u.c
|
||||||
|
endif
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CONFIG_NSH_ARCHINIT),y)
|
ifeq ($(CONFIG_NSH_ARCHINIT),y)
|
||||||
|
1006
configs/hymini-stm32v/src/up_r61505u.c
Executable file
1006
configs/hymini-stm32v/src/up_r61505u.c
Executable file
File diff suppressed because it is too large
Load Diff
@ -156,20 +156,22 @@ Memory Map
|
|||||||
|
|
||||||
Code can be loaded by the CalypsoBootloader only into HRAM beginning at
|
Code can be loaded by the CalypsoBootloader only into HRAM beginning at
|
||||||
address 0x00820000 and, hence, is restricted to 128KB (including then
|
address 0x00820000 and, hence, is restricted to 128KB (including then
|
||||||
non-loaded sections: uninitialized data and for the NuttX heap).
|
non-loaded sections: Uninitialized data and the NuttX heap).
|
||||||
|
|
||||||
|
SDRAM and NOR FLASH
|
||||||
|
-------------------
|
||||||
|
SDRAM is provided by a Flash/SRAM: Spansion S71PL129NC0 part that provices
|
||||||
|
128MBit (16MB) of FLASH and 64MBit (8MB) of SDRAM.
|
||||||
|
|
||||||
SDRAM
|
* SDRAM
|
||||||
-----
|
|
||||||
The Pirelli DP-L10 has 8MB of SDRAM beginning at address 0x01000000.
|
|
||||||
This DRAM appears to be initialized by the Pirelli ROM loader and is
|
|
||||||
ready for use with no further initialization required.
|
|
||||||
|
|
||||||
NOR FLASH
|
The Pirelli DP-L10 has 8MB of SDRAM beginning at address 0x01000000.
|
||||||
---------
|
This DRAM appears to be initialized by the Pirelli ROM loader and is
|
||||||
There is non-volatile memory at address 0x00000000. The other Calypso
|
ready for use with no further initialization required.
|
||||||
phones have NOR FLASH at this location. This needs more investigation
|
|
||||||
for the Pirelli phones.
|
* NOR FLASH
|
||||||
|
|
||||||
|
The 16MB FLASH is at address 0x00000000.
|
||||||
|
|
||||||
USB Serial Console
|
USB Serial Console
|
||||||
==================
|
==================
|
||||||
|
Loading…
x
Reference in New Issue
Block a user