sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add interrupt management logic

Browse Source 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2494 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-01-03 13:01:35 +00:00
parent 778b814926
commit 3e902483c0
3 changed files with 451 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/src/sam3u/Make.defs
View File

@ -45,5 +45,5 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
up_usestack.c up_doirq.c up_hardfault.c up_svcall.c
CHIP_ASRCS =
CHIP_CSRCS = sam3u_start.c
CHIP_CSRCS = sam3u_irq.c sam3u_start.c

10
arch/arm/src/sam3u/chip.h
View File

@ -54,6 +54,16 @@
#include "sam3u_memorymap.h"
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-15. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
/************************************************************************************
* Public Types
************************************************************************************/

440
arch/arm/src/sam3u/sam3u_irq.c Executable file
View File

@ -0,0 +1,440 @@
/****************************************************************************
* arch/arm/src/sam3u/sam3u_irq.c
* arch/arm/src/chip/sam3u_irq.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include "nvic.h"
#include "up_arch.h"
#include "os_internal.h"
#include "up_internal.h"
#include "sam3u_internal.h"
/****************************************************************************
* Definitions
****************************************************************************/
/* Enable NVIC debug features that are probably only desireable during
* bringup
*/
#undef SAM3U_IRQ_DEBUG
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 |\
NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
NVIC_SYSH_PRIORITY_DEFAULT << 8 |\
NVIC_SYSH_PRIORITY_DEFAULT)
/****************************************************************************
* Public Data
****************************************************************************/
uint32_t *current_regs;
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam3u_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#if defined(SAM3U_IRQ_DEBUG) && defined (CONFIG_DEBUG)
static void sam3u_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = irqsave();
slldbg("NVIC (%s, irq=%d):\n", msg, irq);
slldbg(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
slldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
slldbg(" IRQ ENABLE: %08x\n", getreg32(NVIC_IRQ0_31_ENABLE));
slldbg(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
slldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
slldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqrestore(flags);
}
#else
# define sam3u_dumpnvic(msg, irq)
#endif
/****************************************************************************
* Name: sam3u_nmi, sam3u_mpu, sam3u_busfault, sam3u_usagefault, sam3u_pendsv,
* sam3u_dbgmonitor, sam3u_pendsv, sam3u_reserved
*
* Description:
* Handlers for various execptions. None are handled and all are fatal
* error conditions. The only advantage these provided over the default
* unexpected interrupt handler is that they provide a diagnostic output.
*
****************************************************************************/
#ifdef CONFIG_DEBUG
static int sam3u_nmi(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! NMI received\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int sam3u_mpu(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! MPU interrupt received\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int sam3u_busfault(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! Bus fault recived\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int sam3u_usagefault(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! Usage fault received\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int sam3u_pendsv(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! PendSV received\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int sam3u_dbgmonitor(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! Debug Monitor receieved\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int sam3u_reserved(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! Reserved interrupt\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
#endif
/****************************************************************************
* Name: sam3u_irqinfo
*
* Description:
* Given an IRQ number, provide the register and bit setting to enable or
* disable the irq.
*
****************************************************************************/
static int sam3u_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
{
DEBUGASSERT(irq >= SAM3U_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= SAM3U_IRQ_EXTINT)
{
if (irq < NR_IRQS)
{
*regaddr = NVIC_IRQ0_31_ENABLE;
*bit = 1 << (irq - SAM3U_IRQ_EXTINT);
}
else
{
return ERROR; /* Invalid interrupt */
}
}
/* Handle processor exceptions. Only a few can be disabled */
else
{
*regaddr = NVIC_SYSHCON;
if (irq == SAM3U_IRQ_MPU)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == SAM3U_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == SAM3U_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == SAM3U_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
}
else
{
return ERROR; /* Invalid or unsupported exception */
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
/* Disable all interrupts */
putreg32(0, NVIC_IRQ0_31_ENABLE);
/* Set up the vector table address */
#ifdef CONFIG_SAM3U_DFU
putreg32((uint32_t)sam3u_vectors, NVIC_VECTAB);
#endif
/* Set all interrrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
/* currents_regs is non-NULL only while processing an interrupt */
current_regs = NULL;
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(SAM3U_IRQ_SVCALL, up_svcall);
irq_attach(SAM3U_IRQ_HARDFAULT, up_hardfault);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(SAM3U_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG
irq_attach(SAM3U_IRQ_NMI, sam3u_nmi);
irq_attach(SAM3U_IRQ_MPU, sam3u_mpu);
irq_attach(SAM3U_IRQ_BUSFAULT, sam3u_busfault);
irq_attach(SAM3U_IRQ_USAGEFAULT, sam3u_usagefault);
irq_attach(SAM3U_IRQ_PENDSV, sam3u_pendsv);
irq_attach(SAM3U_IRQ_DBGMONITOR, sam3u_dbgmonitor);
irq_attach(SAM3U_IRQ_RESERVED, sam3u_reserved);
#endif
sam3u_dumpnvic("initial", NR_IRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Initialize FIQs */
#ifdef CONFIG_ARCH_FIQ
up_fiqinitialize();
#endif
/* And finally, enable interrupts */
setbasepri(NVIC_SYSH_PRIORITY_MAX);
irqrestore(0);
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
uint32_t regaddr;
uint32_t regval;
uint32_t bit;
if (sam3u_irqinfo(irq, &regaddr, &bit) == 0)
{
/* Clear the appropriate bit in the register to enable the interrupt */
regval = getreg32(regaddr);
regval &= ~bit;
putreg32(regval, regaddr);
}
sam3u_dumpnvic("disable", irq);
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
uint32_t regaddr;
uint32_t regval;
uint32_t bit;
if (sam3u_irqinfo(irq, &regaddr, &bit) == 0)
{
/* Set the appropriate bit in the register to enable the interrupt */
regval = getreg32(regaddr);
regval |= bit;
putreg32(regval, regaddr);
}
sam3u_dumpnvic("enable", irq);
}
/****************************************************************************
* Name: up_maskack_irq
*
* Description:
* Mask the IRQ and acknowledge it
*
****************************************************************************/
void up_maskack_irq(int irq)
{
up_disable_irq(irq);
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
DEBUGASSERT(irq >= SAM3U_IRQ_MPU && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < SAM3U_IRQ_EXTINT)
{
irq -= 4;
regaddr = NVIC_SYSH_PRIORITY(irq);
}
else
{
irq -= SAM3U_IRQ_EXTINT;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
sam3u_dumpnvic("prioritize", irq);
return OK;
}
#endif