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Begnning of support for the STM32L15X family

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This commit is contained in:
Gregory Nutt 2013-05-18 11:15:37 -06:00
parent 6a7e1ba3ef
commit 3eae56467b
4 changed files with 1031 additions and 6 deletions
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363
arch/arm/include/stm32/chip.h
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@ -56,10 +56,248 @@
* the chip datasheet.
*/
/* STM32L EnergyLite Line ************************************************************/
/* STM32L151XX -- No LCD
* STM32L152XX -- With LCD
*
* STM32L15XCX -- 48-pins
* STM32L15XRX -- 64-pins
* STM32L15XVX -- 100-pins
*
* STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM
* STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM
* STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM
*/
#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \
defined(CONFIG_ARCH_CHIP_STM32L151CB)
# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 6 /* (3) 16-bit general up/down timers TIM2,3,4 with DMA */
/* (3) 16-bit general up timers TIM9, 10, 11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 1 /* DMA1, 7-channels */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 37 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 16-channels */
# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
/* (2) Comparators */
# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L151R6) || defined(CONFIG_ARCH_CHIP_STM32L151R8) || \
defined(CONFIG_ARCH_CHIP_STM32L151RB)
# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 6 /* (3) 16-bit general up/down timers TIM2,3,4 with DMA */
/* (3) 16-bit general up timers TIM9, 10, 11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 1 /* DMA1, 7-channels */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 51 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 20-channels */
# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
/* (2) Comparators */
# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L151V6) || defined(CONFIG_ARCH_CHIP_STM32L151V8) || \
defined(CONFIG_ARCH_CHIP_STM32L151VB)
# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 6 /* (3) 16-bit general up/down timers TIM2,3,4 with DMA */
/* (3) 16-bit general up timers TIM9, 10, 11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 1 /* DMA1, 7-channels */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 83 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 24-channels */
# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
/* (2) Comparators */
# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L152C6) || defined(CONFIG_ARCH_CHIP_STM32L152C8) || \
defined(CONFIG_ARCH_CHIP_STM32L152CB)
# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 6 /* (3) 16-bit general up/down timers TIM2,3,4 with DMA */
/* (3) 16-bit general up timers TIM9, 10, 11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 1 /* DMA1, 7-channels */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x16 */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 37 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 16-channels */
# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
/* (2) Comparators */
# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L152R6) || defined(CONFIG_ARCH_CHIP_STM32L152R8) || \
defined(CONFIG_ARCH_CHIP_STM32L152RB)
# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 6 /* (3) 16-bit general up/down timers TIM2,3,4 with DMA */
/* (3) 16-bit general up timers TIM9, 10, 11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 1 /* DMA1, 7-channels */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x32, 8x28 */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 51 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 20-channels */
# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
/* (2) Comparators */
# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32L152V6) || defined(CONFIG_ARCH_CHIP_STM32L152V8) || \
defined(CONFIG_ARCH_CHIP_STM32L152VB)
# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 6 /* (3) 16-bit general up/down timers TIM2,3,4 with DMA */
/* (3) 16-bit general up timers TIM9, 10, 11 without DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
# define STM32_NDMA 1 /* DMA1, 7-channels */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 1 /* LCD 4x44, 8x40*/
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
# define STM32_NGPIO 83 /* GPIOA-E,H */
# define STM32_NADC 1 /* ADC1, 24-channels */
# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
/* (2) Comparators */
# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
/* STM32 F100 Value Line ************************************************************/
#if defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \
#elif defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \
|| defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -69,7 +307,7 @@
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 3 /* 16-bit general timers TIM2,3,4 with DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
@ -81,16 +319,20 @@
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 64 /* GPIOA-D */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 2 /* DAC 1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC1 */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -112,10 +354,12 @@
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 80 /* GPIOA-E */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 2 /* DAC 1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC1 */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
@ -125,6 +369,8 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F100RC) || defined(CONFIG_ARCH_CHIP_STM32F100RD) \
|| defined(CONFIG_ARCH_CHIP_STM32F100RE)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -146,10 +392,12 @@
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 64 /* GPIOA-D */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 2 /* DAC 1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC1 */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
@ -157,6 +405,8 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F100VC) || defined(CONFIG_ARCH_CHIP_STM32F100VD) \
|| defined(CONFIG_ARCH_CHIP_STM32F100VE)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -178,10 +428,12 @@
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 80 /* GPIOA-E */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 2 /* DAC 1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC1 */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
@ -193,6 +445,8 @@
*/
#elif defined(CONFIG_ARCH_CHIP_STM32F103RBT6)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -213,10 +467,12 @@
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 1 /* bxCAN1 */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 51 /* GPIOA-E */
# define STM32_NADC 2 /* ADC1-2 */
# define STM32_NDAC 0 /* No DAC */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NTHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
@ -228,6 +484,8 @@
*/
#elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -248,10 +506,12 @@
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 1 /* CAN1 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 51 /* GPIOA-D */
# define STM32_NADC 2 /* ADC1-2 */
# define STM32_NDAC 2 /* DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
@ -262,6 +522,8 @@
*/
#elif defined(CONFIG_ARCH_CHIP_STM32F103VCT6) || defined(CONFIG_ARCH_CHIP_STM32F103VET6)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -282,10 +544,12 @@
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 1 /* bxCAN1 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 80 /* GPIOA-E */
# define STM32_NADC 3 /* ADC1-3 */
# define STM32_NDAC 2 /* DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NTHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
@ -295,7 +559,9 @@
* only in the available FLASH and SRAM.
*/
#elif defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
#elif defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -316,17 +582,22 @@
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 1 /* CAN1 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 112 /* GPIOA-G */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 0 /* No DAC */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
/* STM32 F105/F107 Connectivity Line *******************************************************/
#elif defined(CONFIG_ARCH_CHIP_STM32F105VBT7)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -347,16 +618,20 @@
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 80 /* GPIOA-E */
# define STM32_NADC 2 /* ADC1-2*/
# define STM32_NADC 2 /* ADC1-2 */
# define STM32_NDAC 2 /* DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -377,17 +652,22 @@
# define STM32_NI2C 1 /* I2C1 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 80 /* GPIOA-E */
# define STM32_NADC 2 /* ADC1-2*/
# define STM32_NDAC 2 /* DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
/* STM32 F2 Family ******************************************************************/
#elif defined(CONFIG_ARCH_CHIP_STM32F207IG) /* UFBGA-176 1024Kb FLASH 128Kb SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -410,10 +690,12 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 140 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
@ -430,6 +712,8 @@
*/
#elif defined(CONFIG_ARCH_CHIP_STM32F302CB) || defined(CONFIG_ARCH_CHIP_STM32F302CC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -454,16 +738,20 @@
# define STM32_NI2C 2 /* (2) I2C1-2 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 37 /* GPIOA-F */
# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */
# define STM32_NDAC 1 /* (1) 12-bit DAC1 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F302RB) || defined(CONFIG_ARCH_CHIP_STM32F302RC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -488,16 +776,20 @@
# define STM32_NI2C 2 /* (2) I2C1-2 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 52 /* GPIOA-F */
# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */
# define STM32_NDAC 1 /* (1) 12-bit DAC1 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F302VB) || defined(CONFIG_ARCH_CHIP_STM32F302VC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -522,16 +814,20 @@
# define STM32_NI2C 2 /* (2) I2C1-2 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 87 /* GPIOA-F */
# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */
# define STM32_NDAC 1 /* (1) 12-bit DAC1 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -556,16 +852,20 @@
# define STM32_NI2C 2 /* (2) I2C1-2 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 37 /* GPIOA-F */
# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303RB) || defined(CONFIG_ARCH_CHIP_STM32F303RC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -590,16 +890,20 @@
# define STM32_NI2C 2 /* (2) I2C1-2 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 52 /* GPIOA-F */
# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -624,17 +928,22 @@
# define STM32_NI2C 2 /* (2) I2C1-2 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 87 /* GPIOA-F */
# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
/* STM23 F4 Family ******************************************************************/
#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -657,16 +966,20 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -689,16 +1002,20 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -721,16 +1038,20 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* No Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -753,16 +1074,20 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -785,16 +1110,20 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -817,16 +1146,20 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -849,16 +1182,20 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -881,16 +1218,20 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -913,16 +1254,20 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F427I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -945,16 +1290,20 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F427Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -977,16 +1326,20 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F427V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@ -1009,10 +1362,12 @@
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */

168
arch/arm/src/stm32/Kconfig
View File

@ -10,6 +10,159 @@ choice
default ARCH_CHIP_STM32F103ZET6
depends on ARCH_CHIP_STM32
config ARCH_CHIP_STM32L151C6
bool "STM32L151C6"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151C8
bool "STM32L151C8"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151CB
bool "STM32L151CB"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151R6
bool "STM32L151R6"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151R8
bool "STM32L151R8"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151RB
bool "STM32L151RB"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151V6
bool "STM32L151V6"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151V8
bool "STM32L151V8"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151VB
bool "STM32L151VB"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L152C6
bool "STM32L152C6"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPRROM with
4x16 LCD interface
config ARCH_CHIP_STM32L152C8
bool "STM32L152C8"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPRROM with
4x16 LCD interface
config ARCH_CHIP_STM32L152CB
bool "STM32L152CB"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM with
4x16 LCD interface
config ARCH_CHIP_STM32L152R6
bool "STM32L152R6"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPRROM with
4x32/8x28 LCD interface
config ARCH_CHIP_STM32L152R8
bool "STM32L152R8"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPRROM with
4x32/8x28 LCD interface
config ARCH_CHIP_STM32L152RB
bool "STM32L152RB"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM with
4x32/8x28 LCD interface
config ARCH_CHIP_STM32L152V6
bool "STM32L152V6"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPRROM with
4x44/8x40 LCD interface
config ARCH_CHIP_STM32L152V8
bool "STM32L152V8"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPRROM with
4x44/8x40 LCD interface
config ARCH_CHIP_STM32L152VB
bool "STM32L152VB"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM with
4x44/8x40 LCD interface
config ARCH_CHIP_STM32F100C8
bool "STM32F100C8"
select ARCH_CORTEXM3
@ -254,26 +407,41 @@ config ARCH_CHIP_STM32F427I
endchoice
config STM32_STM32L15XX
bool
default n
config STM32_ENERGYLITE
bool
default n
config STM32_STM32F10XX
bool
default n
config STM32_VALUELINE
bool
default n
config STM32_HIGHDENSITY
bool
default n
config STM32_CONNECTIVITYLINE
bool
default n
config STM32_STM32F20XX
bool
default n
config STM32_STM32F30XX
bool
default n
config STM32_STM32F40XX
bool
default n
# This is really 427/437, but we treat the two the same.
config STM32_STM32F427

18
arch/arm/src/stm32/chip.h
View File

@ -48,9 +48,21 @@
/* Include the chip pin configuration file */
/* STM32L EnergyLite Line ***********************************************************/
#if defined(CONFIG_STM32_ENERGYLITE)
/* STM32L15xx family */
# if defined(CONFIG_STM32_STM32L15XX)
# include "chip/stm32l15xxx_pinmap.h"
# else
# error "Unsupported EnergyLite chip"
# endif
/* STM32 F1 Family ******************************************************************/
#if defined(CONFIG_STM32_STM32F10XX)
#elif defined(CONFIG_STM32_STM32F10XX)
/* STM32F100 Value Line */
@ -112,7 +124,9 @@
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
# if defined(CONFIG_STM32_STM32F10XX)
# if defined(CONFIG_STM32_STM32L15XX)
# include "chip/stm32l15xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_vectors.h"

488
arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h Normal file
View File

@ -0,0 +1,488 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_PINMAP_H
#define __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_PINMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if
* CAN1_RX connects vis PA11 on some board, then the following definitions should
* appear inthe board.h header file for that board:
*
* #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
*
* The driver will then automatically configre PB6 as the I2C1 SCL pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
*/
#define GPIO_BOOT1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN2)
/* ADC
*
* ADC_IN16 is internal temperature sensor
* ADC_IN17 is internal Vrefint
*/
#define GPIO_ADC1_IN0 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN0)
#define GPIO_ADC1_IN1 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN1)
#define GPIO_ADC1_IN2 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN2)
#define GPIO_ADC1_IN3 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN3)
#define GPIO_ADC1_IN4 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN4)
#define GPIO_ADC1_IN5 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN5)
#define GPIO_ADC1_IN6 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN6)
#define GPIO_ADC1_IN7 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN7)
#define GPIO_ADC1_IN8 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN0)
#define GPIO_ADC1_IN9 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN1)
#define GPIO_ADC1_IN10 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN0)
#define GPIO_ADC1_IN11 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN1)
#define GPIO_ADC1_IN12 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN2)
#define GPIO_ADC1_IN13 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN3)
#define GPIO_ADC1_IN14 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN4)
#define GPIO_ADC1_IN15 (GPIO_INPUT | GPIO_CNF_ANALOGI N| GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN5)
#define GPIO_ADC1_IN18 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN12)
#define GPIO_ADC1_IN19 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN13)
#define GPIO_ADC1_IN20 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN14)
#define GPIO_ADC1_IN21 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN15)
#define GPIO_ADC1_IN22 (GPIO_INPUT | GPIO_CNF_ANALOGI N| GPIO_MODE_INPUT | GPIO_PORTE | GPIO_PIN7)
#define GPIO_ADC1_IN24 (GPIO_INPUT | GPIO_CNF_ANALOGI N| GPIO_MODE_INPUT | GPIO_PORTE | GPIO_PIN8)
#define GPIO_ADC1_IN24 (GPIO_INPUT | GPIO_CNF_ANALOGI N| GPIO_MODE_INPUT | GPIO_PORTE | GPIO_PIN9)
#define GPIO_ADC1_IN25 (GPIO_INPUT | GPIO_CNF_ANALOGI N| GPIO_MODE_INPUT | GPIO_PORTE | GPIO_PIN10)
/* DAC */
#define GPIO_DAC_OUT1 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN4)
#define GPIO_DAC_OUT2 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN5)
/* I2C */
#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF3 | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF4 | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN8)
#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN9)
#define GPIO_I2C1_SMBA (GPIO_ALT | GPIO_AF4 | GPIO_CNF_INFLOAT | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN5)
#define GPIO_I2C2_SCL (GPIO_ALT | GPIO_AF4 | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN10)
#define GPIO_I2C2_SDA (GPIO_ALT | GPIO_AF4 | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN11)
#define GPIO_I2C2_SMBA (GPIO_ALT | GPIO_AF4 | GPIO_CNF_INFLOAT | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN12)
/* JTAG/Trace */
#define GPIO_JTCK_SWCLK (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14)
#define GPIO_JTDI (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_JTDO (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_JTMS_SWDAT (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN13)
#define GPIO_JTRST (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_TRACECK (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN2)
#define GPIO_TRACED0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN3)
#define GPIO_TRACED1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN4)
#define GPIO_TRACED2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN5)
#define GPIO_TRACED3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN6)
/* LCD */
#define GPIO_LCD_COM0 (GPIO_ALT | GPIO_AF11 | GPIO_PORTA | GPIO_PIN8)
#define GPIO_LCD_COM1 (GPIO_ALT | GPIO_AF11 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_LCD_COM2 (GPIO_ALT | GPIO_AF11 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_LCD_COM3 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_LCD_COM4 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN10)
#define GPIO_LCD_COM5 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN11)
#define GPIO_LCD_COM6 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN12)
#define GPIO_LCD_COM7 (GPIO_ALT | GPIO_AF11 | GPIO_PORTD | GPIO_PIN2)
#define GPIO_LCD_SEG0 (GPIO_ALT | GPIO_AF11 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_LCD_SEG1 (GPIO_ALT | GPIO_AF11 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_LCD_SEG2 (GPIO_ALT | GPIO_AF11 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_LCD_SEG3 (GPIO_ALT | GPIO_AF11 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_LCD_SEG4 (GPIO_ALT | GPIO_AF11 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_LCD_SEG5 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_LCD_SEG6 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_LCD_SEG7 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_LCD_SEG8 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_LCD_SEG9 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_LCD_SEG10 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_LCD_SEG11 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_LCD_SEG12 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_LCD_SEG13 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_LCD_SEG14 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_LCD_SEG15 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_LCD_SEG16 (GPIO_ALT | GPIO_AF11 | GPIO_PORTB | GPIO_PIN8)
#define GPIO_LCD_SEG17 (GPIO_ALT | GPIO_AF11 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_LCD_SEG18 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN0)
#define GPIO_LCD_SEG19 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN1)
#define GPIO_LCD_SEG20 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN2)
#define GPIO_LCD_SEG21 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN3)
#define GPIO_LCD_SEG22 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN4)
#define GPIO_LCD_SEG23 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN5)
#define GPIO_LCD_SEG24 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN6)
#define GPIO_LCD_SEG25 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN7)
#define GPIO_LCD_SEG26 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN8)
#define GPIO_LCD_SEG27 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN9)
#define GPIO_LCD_SEG28_1 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN10)
#define GPIO_LCD_SEG28_2 (GPIO_ALT | GPIO_AF11 | GPIO_PORTD | GPIO_PIN8)
#define GPIO_LCD_SEG29_1 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN11)
#define GPIO_LCD_SEG29_2 (GPIO_ALT | GPIO_AF11 | GPIO_PORTD | GPIO_PIN9)
#define GPIO_LCD_SEG30_1 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN12)
#define GPIO_LCD_SEG30_2 (GPIO_ALT | GPIO_AF11 | GPIO_PORTD | GPIO_PIN10)
#define GPIO_LCD_SEG31_1 (GPIO_ALT | GPIO_AF11 | GPIO_PORTD | GPIO_PIN11)
#define GPIO_LCD_SEG31_2 (GPIO_ALT | GPIO_AF11 | GPIO_PORTD | GPIO_PIN2)
#define GPIO_LCD_SEG32 (GPIO_ALT | GPIO_AF11 | GPIO_PORTD | GPIO_PIN12)
#define GPIO_LCD_SEG33 (GPIO_ALT | GPIO_AF11 | GPIO_PORTD | GPIO_PIN13)
#define GPIO_LCD_SEG34 (GPIO_ALT | GPIO_AF11 | GPIO_PORTD | GPIO_PIN14)
#define GPIO_LCD_SEG35 (GPIO_ALT | GPIO_AF11 | GPIO_PORTD | GPIO_PIN15)
#define GPIO_LCD_SEG36 (GPIO_ALT | GPIO_AF11 | GPIO_PORTE | GPIO_PIN0)
#define GPIO_LCD_SEG37 (GPIO_ALT | GPIO_AF11 | GPIO_PORTE | GPIO_PIN1)
#define GPIO_LCD_SEG38 (GPIO_ALT | GPIO_AF11 | GPIO_PORTE | GPIO_PIN2)
#define GPIO_LCD_SEG39 (GPIO_ALT | GPIO_AF11 | GPIO_PORTE | GPIO_PIN3)
#define GPIO_LCD_SEG40 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN10)
#define GPIO_LCD_SEG41 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN11)
#define GPIO_LCD_SEG42 (GPIO_ALT | GPIO_AF11 | GPIO_PORTC | GPIO_PIN12)
#define GPIO_LCD_SEG43 (GPIO_ALT | GPIO_AF11 | GPIO_PORTD | GPIO_PIN2)
/* Clocking */
#define GPIO_MCO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN8)
#define GPIO_OSC32_IN (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN14)
#define GPIO_OSC32_OUT (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN15)
#define GPIO_OSC_IN (GPIO_ALT | GPIO_AF0 | GPIO_PORTH | GPIO_PIN0)
#define GPIO_OSC_OUT (GPIO_ALT | GPIO_AF0 | GPIO_PORTH | GPIO_PIN1)
/* Event outputs */
#define GPIO_PA0_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_PA10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_PA10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_PA11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_PA13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN13)
#define GPIO_PA14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN14)
#define GPIO_PA15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_PA1_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_PA2_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_PA3_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_PA4_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_PA5_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_PA6_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_PA7_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_PA8_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN8)
#define GPIO_PA9_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_PB0_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_PB10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_PB11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_PB12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_PB13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_PB14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_PB15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_PB1_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_PB2_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN2)
#define GPIO_PB3_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_PB4_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_PB5_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_PB6_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN6)
#define GPIO_PB7_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN7)
#define GPIO_PB8_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN8)
#define GPIO_PB9_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_PC0_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN0)
#define GPIO_PC10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN10)
#define GPIO_PC11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN11)
#define GPIO_PC12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN12)
#define GPIO_PC13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN13)
#define GPIO_PC14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN14)
#define GPIO_PC15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN15)
#define GPIO_PC1_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN1)
#define GPIO_PC2_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN2)
#define GPIO_PC3_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN3)
#define GPIO_PC4_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN4)
#define GPIO_PC5_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN5)
#define GPIO_PC6_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN6)
#define GPIO_PC7_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN7)
#define GPIO_PC8_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN8)
#define GPIO_PC9_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTC | GPIO_PIN9)
#define GPIO_PD0_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN0)
#define GPIO_PD10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN10)
#define GPIO_PD11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN11)
#define GPIO_PD12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN12)
#define GPIO_PD13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN13)
#define GPIO_PD14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN14)
#define GPIO_PD15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN15)
#define GPIO_PD1_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN1)
#define GPIO_PD2_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN2)
#define GPIO_PD3_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN3)
#define GPIO_PD4_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN4)
#define GPIO_PD5_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN5)
#define GPIO_PD6_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN6)
#define GPIO_PD7_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN7)
#define GPIO_PD8_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN8)
#define GPIO_PD9_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTD | GPIO_PIN9)
#define GPIO_PE0_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN0)
#define GPIO_PE10_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN10)
#define GPIO_PE11_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN11)
#define GPIO_PE12_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN12)
#define GPIO_PE13_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN13)
#define GPIO_PE14_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN14)
#define GPIO_PE15_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN15)
#define GPIO_PE1_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN1)
#define GPIO_PE2_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN2)
#define GPIO_PE3_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN3)
#define GPIO_PE4_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN4)
#define GPIO_PE5_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN5)
#define GPIO_PE6_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN6)
#define GPIO_PE7_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN7)
#define GPIO_PE8_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN8)
#define GPIO_PE9_EVENT_OUT (GPIO_ALT | GPIO_AF15 | GPIO_PORTE | GPIO_PIN9)
/* RTC */
#define GPIO_RTC_OUT (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN13)
#define GPIO_RTC_REFIN (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_RTC_TAMP1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN13)
#define GPIO_RTC_TS (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN13)
/* SPI */
#define GPIO_SPI1_MISO_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_SPI1_MISO_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_SPI1_MISO_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_SPI1_MISO_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTE | GPIO_PIN14)
#define GPIO_SPI1_MOSI_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_SPI1_MOSI_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_SPI1_MOSI_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_SPI1_MOSI_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTE | GPIO_PIN15)
#define GPIO_SPI1_NSS_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_SPI1_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_SPI1_NSS_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTE | GPIO_PIN12)
#define GPIO_SPI1_SCK_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_SPI1_SCK_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_SPI1_SCK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTE | GPIO_PIN13)
#define GPIO_SPI2_MISO_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_SPI2_MISO_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN3)
#define GPIO_SPI2_MOSI_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_SPI2_MOSI_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN4)
#define GPIO_SPI2_NSS_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_SPI2_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN0)
#define GPIO_SPI2_SCK_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_SPI2_SCK_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN1)
/* Timers */
#define GPIO_TIM2_CH1_ETR_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_TIM2_CH1_ETR_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_TIM2_CH1_ETR_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN9)
#define GPIO_TIM2_CH1_ETR_4 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_TIM2_CH2_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_TIM2_CH2_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_TIM2_CH2_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN10)
#define GPIO_TIM2_CH3_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TIM2_CH3_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_TIM2_CH3_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN11)
#define GPIO_TIM2_CH4_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_TIM2_CH4_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_TIM2_CH4_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN12)
#define GPIO_TIM3_CH1_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_TIM3_CH1_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_TIM3_CH1_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN6)
#define GPIO_TIM3_CH1_4 (GPIO_ALT | GPIO_AF2 | GPIO_PORTE | GPIO_PIN3)
#define GPIO_TIM3_CH2_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TIM3_CH2_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_TIM3_CH2_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN7)
#define GPIO_TIM3_CH2_4 (GPIO_ALT | GPIO_AF2 | GPIO_PORTE | GPIO_PIN4)
#define GPIO_TIM3_CH3_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_TIM3_CH3_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN8)
#define GPIO_TIM3_CH4_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_TIM3_CH4_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN9)
#define GPIO_TIM3_ETR_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN2)
#define GPIO_TIM3_ETR_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTE | GPIO_PIN2)
#define GPIO_TIM4_CH1_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN6)
#define GPIO_TIM4_CH1_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN12)
#define GPIO_TIM4_CH2_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN7)
#define GPIO_TIM4_CH2_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN13)
#define GPIO_TIM4_CH3_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN8)
#define GPIO_TIM4_CH3_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN14)
#define GPIO_TIM4_CH4_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_TIM4_CH4_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN15)
#define GPIO_TIM4_ETR (GPIO_ALT | GPIO_AF2 | GPIO_PORTE | GPIO_PIN0)
#define GPIO_TIM9_CH1_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TIM9_CH1_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_TIM9_CH1_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTD | GPIO_PIN0)
#define GPIO_TIM9_CH1_4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTE | GPIO_PIN5)
#define GPIO_TIM9_CH2_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_TIM9_CH2_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_TIM9_CH2_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTD | GPIO_PIN7)
#define GPIO_TIM9_CH2_4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTE | GPIO_PIN6)
#define GPIO_TIM10_CH1_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_TIM10_CH1_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_TIM10_CH1_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN8)
#define GPIO_TIM10_CH1_4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTE | GPIO_PIN0)
#define GPIO_TIM11_CH1_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TIM11_CH1_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_TIM11_CH1_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_TIM11_CH1_4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTE | GPIO_PIN1)
#define GPIO_TIMX_IC1_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_TIMX_IC1_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_TIMX_IC1_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_TIMX_IC1_4 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN8)
#define GPIO_TIMX_IC1_5 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN0)
#define GPIO_TIMX_IC1_6 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN12)
#define GPIO_TIMX_IC1_7 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN4)
#define GPIO_TIMX_IC1_8 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN8)
#define GPIO_TIMX_IC1_9 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN0)
#define GPIO_TIMX_IC1_10 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN12)
#define GPIO_TIMX_IC1_11 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN4)
#define GPIO_TIMX_IC1_12 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN8)
#define GPIO_TIMX_IC1_13 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN0)
#define GPIO_TIMX_IC1_14 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN12)
#define GPIO_TIMX_IC1_15 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN4)
#define GPIO_TIMX_IC1_16 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN8)
#define GPIO_TIMX_IC2_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_TIMX_IC2_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN13)
#define GPIO_TIMX_IC2_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_TIMX_IC2_4 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_TIMX_IC2_5 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN1)
#define GPIO_TIMX_IC2_6 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN13)
#define GPIO_TIMX_IC2_7 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN5)
#define GPIO_TIMX_IC2_8 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN9)
#define GPIO_TIMX_IC2_9 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN1)
#define GPIO_TIMX_IC2_10 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN13)
#define GPIO_TIMX_IC2_11 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN5)
#define GPIO_TIMX_IC2_12 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN9)
#define GPIO_TIMX_IC2_13 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN1)
#define GPIO_TIMX_IC2_14 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN13)
#define GPIO_TIMX_IC2_15 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN5)
#define GPIO_TIMX_IC2_16 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN9)
#define GPIO_TIMX_IC3_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_TIMX_IC3_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN14)
#define GPIO_TIMX_IC3_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TIMX_IC3_4 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_TIMX_IC3_5 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN10)
#define GPIO_TIMX_IC3_6 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN14)
#define GPIO_TIMX_IC3_7 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN2)
#define GPIO_TIMX_IC3_8 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN6)
#define GPIO_TIMX_IC3_9 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN10)
#define GPIO_TIMX_IC3_10 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN14)
#define GPIO_TIMX_IC3_11 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN2)
#define GPIO_TIMX_IC3_12 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN6)
#define GPIO_TIMX_IC3_13 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN10)
#define GPIO_TIMX_IC3_14 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN14)
#define GPIO_TIMX_IC3_15 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN2)
#define GPIO_TIMX_IC3_16 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN6)
#define GPIO_TIMX_IC4_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_TIMX_IC4_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_TIMX_IC4_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_TIMX_IC4_4 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TIMX_IC4_5 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN11)
#define GPIO_TIMX_IC4_6 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN15)
#define GPIO_TIMX_IC4_7 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN3)
#define GPIO_TIMX_IC4_8 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN7)
#define GPIO_TIMX_IC4_9 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN11)
#define GPIO_TIMX_IC4_10 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN15)
#define GPIO_TIMX_IC4_11 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN3)
#define GPIO_TIMX_IC4_12 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN7)
#define GPIO_TIMX_IC4_13 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN11)
#define GPIO_TIMX_IC4_14 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN15)
#define GPIO_TIMX_IC4_15 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN3)
#define GPIO_TIMX_IC4_16 (GPIO_ALT | GPIO_AF14 | GPIO_PORTE | GPIO_PIN7)
/* USART */
#define GPIO_USART1_CK (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN8)
#define GPIO_USART1_CTS (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_USART1_RTS (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_USART1_RX_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_USART1_RX_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN7)
#define GPIO_USART1_TX_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_USART1_TX_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN6)
#define GPIO_USART2_CK_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_USART2_CK_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN7)
#define GPIO_USART2_CTS_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_USART2_CTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN3)
#define GPIO_USART2_RTS_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_USART2_RTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN4)
#define GPIO_USART2_RX_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_USART2_RX_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN6)
#define GPIO_USART2_TX_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_USART2_TX_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN5)
#define GPIO_USART3_CK_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_USART3_CK_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTC | GPIO_PIN12)
#define GPIO_USART3_CK_3 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN10)
#define GPIO_USART3_CTS_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_USART3_CTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN11)
#define GPIO_USART3_RTS_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_USART3_RTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN12)
#define GPIO_USART3_RX_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_USART3_RX_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTC | GPIO_PIN11)
#define GPIO_USART3_RX_3 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN9)
#define GPIO_USART3_TX_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_USART3_TX_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTC | GPIO_PIN10)
#define GPIO_USART3_TX_3 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN8)
/* USB */
#define GPIO_USB_DM (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_USG_DP (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN12)
/* Wakeup inputs */
#define GPIO_WKUP1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_WKUP2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN13)
#define GPIO_WKUP3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN6)
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_PINMAP_H */