Flesh out memory map
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2474 42af7a65-404d-4744-a932-0658087f49c3
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@ -1,4 +1,4 @@
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/************************************************************************************
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/************************************************************************************************
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* arch/arm/src/sam3u/sam3u_memorymap.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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@ -31,37 +31,103 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H
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#define __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H
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/************************************************************************************
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/************************************************************************************************
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* Included Files
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************************************************************************************/
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************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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/************************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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************************************************************************************************/
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/* FLASH and SRAM *******************************************************************/
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#define SAM3U_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */
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# define SAM3U_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x0007ffff: Boot Memory */
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# define SAM3U_INTFLASH0_BASE 0x00080000 /* 0x00080000-0x000fffff: Internal FLASH 0 */
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# define SAM3U_INTFLASH1_BASE 0x00100000 /* 0x00100000-0x0017ffff: Internal FLASH 1 */
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# define SAM3U_INTROM_BASE 0x00180000 /* 0x00180000-0x001fffff: Internal ROM */
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/* 0x00200000-0x1fffffff: Reserved */
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#define SAM3U_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */
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# define SAM3U_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: SRAM0 */
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# define SAM3U_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: SRAM1 */
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# define SAM3U_NFCSRAM_BASE 0x20100000 /* 0x20100000-0x207fffff: NFC (SRAM) */
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# define SAM3U_UDPHPSDMS_BASE 0x20180000 /* 0x20180000-0x201fffff: UDPHS (DMA) */
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/* 0x20200000-0x2fffffff: Undefined */
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# define SAM3U_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32Mb bit-band alias */
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/* 0x24000000-0x3fffffff: Undefined */
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#define SAM3U_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */
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# define SAM3U_MCI_BASE 0x40000000 /* 0x40000000-0x400003ff: MCI */
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# define SAM3U_SSC_BASE 0x40000400 /* 0x40000400-0x400007ff: SSC */
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# define SAM3U_SPI_BASE 0x40000800 /* 0x40000800-0x40000bff: SPI */
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/* 0x40000c00-0x4007ffff: Reserved */
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# define SAM3U_TC0_BASE 0x40080000 /* 0x40080000-0x4008003f: TC0 */
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# define SAM3U_TC1_BASE 0x40080040 /* 0x40080040-0x4008007f: TC1 */
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# define SAM3U_TC2_BASE 0x40080080 /* 0x40080080-0x400800bf: TC2 */
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# define SAM3U_TWI0_BASE 0x40084000 /* 0x40084000-0x40087fff: TWI0 */
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# define SAM3U_TWI1_BASE 0x40088000 /* 0x40088000-0x4008bfff: TWI1 */
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# define SAM3U_PWM_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: PWM */
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# define SAM3U_USART0_BASE 0x40090000 /* 0x40090000-0x40093fff: USART0 */
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# define SAM3U_USART1_BASE 0x40094000 /* 0x40094000-0x40097fff: USART1 */
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# define SAM3U_USART2_BASE 0x40098000 /* 0x40098000-0x4009bfff: USART2 */
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# define SAM3U_USART3_BASE 0x4009c000 /* 0x4009c000-0x4009ffff: USART3 */
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/* 0x400a0000-0x400a3fff: Reserved */
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# define SAM3U_UDPHPS_BASE 0x400a4000 /* 0x400a4000-0x400a7fff: UDPHS */
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# define SAM3U_ADC12B_BASE 0x400a8000 /* 0x400a8000-0x400abfff: ADC 12-bit */
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# define SAM3U_ADC_BASE 0x400ac000 /* 0x400ac000-0x400affff: ADC */
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# define SAM3U_DMAC_BASE 0x400b0000 /* 0x400b0000-0x400b3fff: DMA controller */
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/* 0x400b4000-0x400dffff: Reserved */
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# define SAM3U_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */
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/* 0x400e2600-0x400fffff: Reserved */
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/* 0x40100000-0x41ffffff: Reserved */
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# define SAM3U_BBPERIPH__BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */
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/* 0x44000000-0x5fffffff: Reserved */
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#define SAM3U_EXTSRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External SRAM */
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# define SAM3U_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: Chip select 0 */
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# define SAM3U_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: Chip select 1 */
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# define SAM3U_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */
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# define SAM3U_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */
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/* 0x64000000-0x67ffffff: Reserved */
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# define SAM3U_NFC_BASE 0x68000000 /* 0x68000000-0x68ffffff: NFC */
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/* 0x69000000-0x9fffffff: Reserved */
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/* 0xa0000000-0xdfffffff: Reserved */
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#define SAM3U_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */
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/* Register Base Addresses **********************************************************/
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/* System Controller Register Blocks: 0x400e0000-0x4007ffff */
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/************************************************************************************
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#define SAM3U_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: SMC */
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#define SAM3U_MATRIX_BASE 0x400e0000 /* 0x400e0200-0x400e03ff: MATRIX */
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#define SAM3U_PMC_BASE 0x400e0000 /* 0x400e0400-0x400e05ff: PMC */
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#define SAM3U_UART_BASE 0x400e0000 /* 0x400e0600-0x400e073f: UART */
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#define SAM3U_CHIPID_BASE 0x400e0000 /* 0x400e0740-0x400e07ff: CHIP ID */
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#define SAM3U_EFC0_BASE 0x400e0000 /* 0x400e0800-0x400e09ff: EFC0 */
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#define SAM3U_EFC1_BASE 0x400e0000 /* 0x400e0a00-0x400e0bff: EFC1 */
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#define SAM3U_PIOA_BASE 0x400e0000 /* 0x400e0c00-0x400e0dff: PIOA */
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#define SAM3U_PIOB_BASE 0x400e0000 /* 0x400e0e00-0x400e0fff: PIOB */
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#define SAM3U_PIOC_BASE 0x400e0000 /* 0x400e1000-0x400e11ff: PIOC */
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#define SAM3U_RSTC_BASE 0x400e0000 /* 0x400e1200-0x400e120f: RSTC */
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#define SAM3U_SUPC_BASE 0x400e0000 /* 0x400e1210-0x400e122f: SUPC */
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#define SAM3U_RTT_BASE 0x400e0000 /* 0x400e1230-0x400e124f: RTT */
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#define SAM3U_WDT_BASE 0x400e0000 /* 0x400e1250-0x400e125f: WDT */
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#define SAM3U_RTC_BASE 0x400e0000 /* 0x400e1260-0x400e128f: RTD */
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#define SAM3U_GPBR_BASE 0x400e0000 /* 0x400e1290-0x400e13ff: GPBR */
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/* 0x490e1400-0x4007ffff: Reserved */
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/************************************************************************************************
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* Public Types
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************************************************************************************/
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************************************************************************************************/
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/************************************************************************************
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/************************************************************************************************
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* Public Data
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************************************************************************************/
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************************************************************************************************/
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/************************************************************************************
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/************************************************************************************************
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* Public Functions
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************************************************************************************/
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************************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H */
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