diff --git a/arch/arm/src/armv7-a/cp15.h b/arch/arm/src/armv7-a/cp15.h
index c0f5c76f7b..8da017b419 100644
--- a/arch/arm/src/armv7-a/cp15.h
+++ b/arch/arm/src/armv7-a/cp15.h
@@ -74,7 +74,7 @@
 #define _CP15(op1,rd,crn,crm,op2) p15, op1, rd, crn, crm, op2
 
 #define CP15_MIDR(r)       _CP15(0, r, c0, c0, 0)   /* Main ID Register */
-#define CP15_TR(r)         _CP15(0, r, c0, c0, 1)   /* Cache Type Register */
+#define CP15_CTR(r)        _CP15(0, r, c0, c0, 1)   /* Cache Type Register */
 #define CP15_TCMTR(r)      _CP15(0, r, c0, c0, 2)   /* TCM Type Register */
 #define CP15_TLBTR(r)      _CP15(0, r, c0, c0, 3)   /* TLB Type Register */
 #define CP15_MPIDR(r)      _CP15(0, r, c0, c0, 5)   /* Multiprocessor Affinity Register */
@@ -158,10 +158,10 @@
 #define CP15_TLBIASID(r,c) _CP15(0, r, c8, c, 2)    /* Invalidate data TLB by ASID match. CRm = c5, c6, or c7 */
 #define CP15_TLBIMVAA(r,c) _CP15(0, r, c8, c, 3)    /* Invalidate unified TLB entry by MVA and ASID. CRm = c5, c6, or c7 */
 
-#define CP15_MCR(r)        _CP15(0, r, c9, c12, 0)  /* Performance Monitor Control Register */
+#define CP15_PMCR(r)       _CP15(0, r, c9, c12, 0)  /* Performance Monitor Control Register */
 #define CP15_PMCNTENSET(r) _CP15(0, r, c9, c12, 1)  /* Count Enable Set Register */
 #define CP15_PMCNTENCLR(r) _CP15(0, r, c9, c12, 2)  /* Count Enable Clear Register */
-#define CP15_MOVSR(r)      _CP15(0, r, c9, c12, 3)  /* Overflow Flag Status Register */
+#define CP15_PMOVSR(r)     _CP15(0, r, c9, c12, 3)  /* Overflow Flag Status Register */
 #define CP15_PMSWINC(r)    _CP15(0, r, c9, c12, 4)  /* Software Increment Register */
 #define CP15_PMSELR(r)     _CP15(0, r, c9, c12, 5)  /* Event Counter Selection Register */
 #define CP15_PMCEID0(r)    _CP15(0, r, c9, c12, 6)  /* Common Event Identification Registers (Cortex-A5) */
@@ -169,7 +169,7 @@
 #define CP15_PMCCNTR(r)    _CP15(0, r, c9, c13, 0)  /* Cycle Count Register */
 #define CP15_PMXEVTYPER(r) _CP15(0, r, c9, c13, 1)  /* Event Type Select Register */
 #define CP15_PMCCFILTR(r)  _CP15(0, r, c9, c13, 1)  /* Cycle Count Filter Control Register */
-#define CP15_MXEVCNTR(r)   _CP15(0, r, c9, c13, 2)  /* Event Count Registers (Cortex-A5) */
+#define CP15_PMXEVCNTR(r)  _CP15(0, r, c9, c13, 2)  /* Event Count Registers (Cortex-A5) */
 #define CP15_PMUSERENR(r)  _CP15(0, r, c9, c14, 0)  /* User Enable Register */
 #define CP15_PMINTENSET(r) _CP15(0, r, c9, c14, 1)  /* Interrupt Enable Set Register */
 #define CP15_PMINTENCLR(r) _CP15(0, r, c9, c14, 2)  /* Interrupt Enable Clear Register */
diff --git a/arch/arm/src/armv7-a/cp15_clean_dcache.S b/arch/arm/src/armv7-a/cp15_clean_dcache.S
index 4c2310b1ec..0f2f8e39eb 100644
--- a/arch/arm/src/armv7-a/cp15_clean_dcache.S
+++ b/arch/arm/src/armv7-a/cp15_clean_dcache.S
@@ -92,7 +92,7 @@
 
 cp15_clean_dcache:
 
-	mrc		CP15_TR(r3)				/* Read the Cache Type Register */
+	mrc		CP15_CTR(r3)				/* Read the Cache Type Register */
 	lsr		r3, r3, #16				/* Isolate the DMinLine field */
 	and		r3, r3, #0xf
 	mov		r2, #4
diff --git a/arch/arm/src/armv7-a/cp15_coherent_dcache.S b/arch/arm/src/armv7-a/cp15_coherent_dcache.S
index 2dc245e75b..8f3ee3196b 100644
--- a/arch/arm/src/armv7-a/cp15_coherent_dcache.S
+++ b/arch/arm/src/armv7-a/cp15_coherent_dcache.S
@@ -93,7 +93,7 @@
 	.type	cp15_coherent_dcache, function
 
 cp15_coherent_dcache:
-	mrc		CP15_TR(r3)				/* Read the Cache Type Register */
+	mrc		CP15_CTR(r3)				/* Read the Cache Type Register */
 	lsr		r3, r3, #16				/* Isolate the DMinLine field */
 	and		r3, r3, #0xf
 	mov		r2, #4
@@ -111,7 +111,7 @@ cp15_coherent_dcache:
 
 	dsb
 
-	mrc		CP15_TR(r3)				/* Read the Cache Type Register */
+	mrc		CP15_CTR(r3)				/* Read the Cache Type Register */
 	and		r3, r3, #0xf			/* Isolate the IminLine field */
 	mov		r2, #4
 	mov		r2, r2, lsl r3			/* Get the cache line size in bytes */
diff --git a/arch/arm/src/armv7-a/cp15_flush_dcache.S b/arch/arm/src/armv7-a/cp15_flush_dcache.S
index bac23761ae..ca43fa1adf 100644
--- a/arch/arm/src/armv7-a/cp15_flush_dcache.S
+++ b/arch/arm/src/armv7-a/cp15_flush_dcache.S
@@ -92,7 +92,7 @@
 
 cp15_flush_dcache:
 
-	mrc		CP15_TR(r3)				/* Read the Cache Type Register */
+	mrc		CP15_CTR(r3)				/* Read the Cache Type Register */
 	lsr		r3, r3, #16				/* Isolate the DMinLine field */
 	and		r3, r3, #0xf
 	mov		r2, #4
diff --git a/arch/arm/src/armv7-a/cp15_invalidate_dcache.S b/arch/arm/src/armv7-a/cp15_invalidate_dcache.S
index a51b4021be..56ff8837bf 100644
--- a/arch/arm/src/armv7-a/cp15_invalidate_dcache.S
+++ b/arch/arm/src/armv7-a/cp15_invalidate_dcache.S
@@ -93,7 +93,7 @@
 
 cp15_invalidate_dcache:
 
-	mrc		CP15_TR(r3)				/* Read the Cache Type Register */
+	mrc		CP15_CTR(r3)				/* Read the Cache Type Register */
 	lsr		r3, r3, #16				/* Isolate the DMinLine field */
 	and		r3, r3, #0xf
 	mov		r2, #4