From 3f6157001a172e74ea5e6b4afd686bccd63867d4 Mon Sep 17 00:00:00 2001 From: "Daniel P. Carvalho" Date: Wed, 4 Nov 2020 17:41:40 -0300 Subject: [PATCH] Change SPWM example to enable timer after configure timer clock. --- arch/arm/src/stm32l4/stm32l4_tim.c | 49 +++++++++++-------- arch/arm/src/stm32l4/stm32l4_tim.h | 43 +++++++++------- .../stm32l4/nucleo-l432kc/src/stm32_spwm.c | 1 + 3 files changed, 53 insertions(+), 40 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index 40e10ca657..2e2d1a6de5 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -254,7 +254,8 @@ static inline void stm32l4_putreg32(FAR struct stm32l4_tim_dev_s *dev, /* Timer helpers */ static void stm32l4_tim_reload_counter(FAR struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_enable(FAR struct stm32l4_tim_dev_s *dev, bool state); +static void stm32l4_tim_enable(FAR struct stm32l4_tim_dev_s *dev); +static void stm32l4_tim_disable(FAR struct stm32l4_tim_dev_s *dev); static void stm32l4_tim_reset(FAR struct stm32l4_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ @@ -312,6 +313,7 @@ static const struct stm32l4_tim_ops_s stm32l4_tim_ops = .ackint = stm32l4_tim_ackint, .checkint = stm32l4_tim_checkint, .enable = stm32l4_tim_enable, + .disable = stm32l4_tim_disable, .dump_regs = stm32l4_tim_dumpregs, }; @@ -506,19 +508,23 @@ static void stm32l4_tim_reload_counter(FAR struct stm32l4_tim_dev_s *dev) * Name: stm32l4_tim_enable ************************************************************************************/ -static void stm32l4_tim_enable(FAR struct stm32l4_tim_dev_s *dev, bool state) +static void stm32l4_tim_enable(FAR struct stm32l4_tim_dev_s *dev) { uint16_t val = stm32l4_getreg16(dev, STM32L4_BTIM_CR1_OFFSET); - if(state) - { - val |= ATIM_CR1_CEN; - stm32l4_tim_reload_counter(dev); - } - else - { - val &= ~ATIM_CR1_CEN; - } + val |= ATIM_CR1_CEN; + stm32l4_tim_reload_counter(dev); + stm32l4_putreg16(dev, STM32L4_BTIM_CR1_OFFSET, val); +} + +/************************************************************************************ + * Name: stm32l4_tim_disable + ************************************************************************************/ + +static void stm32l4_tim_disable(FAR struct stm32l4_tim_dev_s *dev) +{ + uint16_t val = stm32l4_getreg16(dev, STM32L4_BTIM_CR1_OFFSET); + val &= ~ATIM_CR1_CEN; stm32l4_putreg16(dev, STM32L4_BTIM_CR1_OFFSET, val); } @@ -533,7 +539,7 @@ static void stm32l4_tim_enable(FAR struct stm32l4_tim_dev_s *dev, bool state) static void stm32l4_tim_reset(FAR struct stm32l4_tim_dev_s *dev) { ((struct stm32l4_tim_priv_s *)dev)->mode = STM32L4_TIM_MODE_DISABLED; - stm32l4_tim_enable(dev, false); + stm32l4_tim_disable(dev); } /************************************************************************************ @@ -567,29 +573,30 @@ static void stm32l4_tim_gpioconfig(uint32_t cfg, enum stm32l4_tim_channel_e mode static void stm32l4_tim_dumpregs(FAR struct stm32l4_tim_dev_s *dev) { struct stm32l4_tim_priv_s *priv = (struct stm32l4_tim_priv_s *)dev; - { - /* data */ - }; - + ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET), stm32l4_getreg16(dev, STM32L4_GTIM_CR2_OFFSET), stm32l4_getreg16(dev, STM32L4_GTIM_SMCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_DIER_OFFSET)); + stm32l4_getreg16(dev, STM32L4_GTIM_DIER_OFFSET) + ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", stm32l4_getreg16(dev, STM32L4_GTIM_SR_OFFSET), stm32l4_getreg16(dev, STM32L4_GTIM_CCMR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCMR2_OFFSET)); + stm32l4_getreg16(dev, STM32L4_GTIM_CCMR2_OFFSET) + ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET), stm32l4_getreg16(dev, STM32L4_GTIM_CNT_OFFSET), stm32l4_getreg16(dev, STM32L4_GTIM_PSC_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_ARR_OFFSET)); + stm32l4_getreg16(dev, STM32L4_GTIM_ARR_OFFSET) + ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", stm32l4_getreg16(dev, STM32L4_GTIM_CCR1_OFFSET), stm32l4_getreg16(dev, STM32L4_GTIM_CCR2_OFFSET), stm32l4_getreg16(dev, STM32L4_GTIM_CCR3_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR4_OFFSET)); + stm32l4_getreg16(dev, STM32L4_GTIM_CCR4_OFFSET) + ); if (priv->base == STM32L4_TIM1_BASE || priv->base == STM32L4_TIM8_BASE) { @@ -698,7 +705,7 @@ static int stm32l4_tim_setclock(FAR struct stm32l4_tim_dev_s *dev, if (freq == 0) { - stm32l4_tim_enable(dev, false); + stm32l4_tim_disable(dev); return 0; } diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h index 51f1a37503..d69b9a7511 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/stm32l4_tim.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/***************************************************************************** * arch/arm/src/stm32l4/stm32l4_tim.h * * Copyright (C) 2011 Uros Platise. All rights reserved. @@ -37,25 +37,25 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + *****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H #define __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H -/************************************************************************************ +/***************************************************************************** * Included Files - ************************************************************************************/ + *****************************************************************************/ #include #include "chip.h" #include "hardware/stm32l4_tim.h" -/************************************************************************************ +/***************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + *****************************************************************************/ -/* Helpers **************************************************************************/ +/* Helpers *******************************************************************/ #define STM32L4_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) #define STM32L4_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) @@ -71,12 +71,13 @@ #define STM32L4_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) #define STM32L4_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) #define STM32L4_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32L4_TIM_ENABLE(d,s) ((d)->ops->enable(d,s)) +#define STM32L4_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32L4_TIM_DISABLE(d) ((d)->ops->disable(d)) #define STM32L4_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) -/************************************************************************************ +/***************************************************************************** * Public Types - ************************************************************************************/ + *****************************************************************************/ #ifndef __ASSEMBLY__ @@ -117,7 +118,7 @@ enum stm32l4_tim_mode_e #if 0 STM32L4_TIM_MODE_CK_INT_TRIG = 0x0400, STM32L4_TIM_MODE_CK_EXT = 0x0800, - STM32L4_TIM_MODE_CK_EXT_TRIG = 0x0C00, + STM32L4_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ @@ -150,7 +151,9 @@ enum stm32l4_tim_channel_e /* Output Compare Modes */ - STM32L4_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32L4_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active + * high when counter < compare + */ #if 0 STM32L4_TIM_CH_OUTCOMPARE = 0x06, #endif @@ -194,13 +197,14 @@ struct stm32l4_tim_ops_s void (*disableint)(FAR struct stm32l4_tim_dev_s *dev, int source); void (*ackint)(FAR struct stm32l4_tim_dev_s *dev, int source); int (*checkint)(FAR struct stm32l4_tim_dev_s *dev, int source); - void (*enable)(FAR struct stm32l4_tim_dev_s *dev, bool state); + void (*enable)(FAR struct stm32l4_tim_dev_s *dev); + void (*disable)(FAR struct stm32l4_tim_dev_s *dev); void (*dump_regs)(FAR struct stm32l4_tim_dev_s *dev); }; -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/***************************************************************************** + * Public functions + *****************************************************************************/ /* Power-up timer and get its structure */ @@ -210,7 +214,7 @@ FAR struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer); int stm32l4_tim_deinit(FAR struct stm32l4_tim_dev_s *dev); -/**************************************************************************** +/***************************************************************************** * Name: stm32l4_timer_initialize * * Description: @@ -218,14 +222,15 @@ int stm32l4_tim_deinit(FAR struct stm32l4_tim_dev_s *dev); * register the timer drivers at 'devpath' * * Input Parameters: - * devpath - The full path to the timer device. This should be of the form /dev/timer0 + * devpath - The full path to the timer device. This should be of the form + * /dev/timer0 * timer - the timer number. * * Returned Value: * Zero (OK) is returned on success; A negated errno value is returned * to indicate the nature of any failure. * - ****************************************************************************/ + *****************************************************************************/ #ifdef CONFIG_TIMER int stm32l4_timer_initialize(FAR const char *devpath, int timer); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c index a48e823a3b..5ec2d25139 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c @@ -392,6 +392,7 @@ static int spwm_tim6_setup(FAR struct spwm_s *spwm) STM32L4_TIM_SETCLOCK(tim, BOARD_TIM6_FREQUENCY); STM32L4_TIM_SETPERIOD(tim, per); + STM32L4_TIM_ENABLE(tim); /* Attach TIM6 ram vector */