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Costmetic fixes to C coding style

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This commit is contained in:
Gregory Nutt 2015-10-05 17:13:53 -06:00
parent 7a63e976ad
commit 3fdd914203
160 changed files with 930 additions and 875 deletions
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2
arch/arm/src/a1x/a1x_pio.c
View File

@ -67,7 +67,7 @@
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: a1x_pio_pin

16
arch/arm/src/armv6-m/up_vectors.c
View File

@ -85,16 +85,16 @@ extern char _ebss;
*/
unsigned _vectors[] __attribute__((section(".vectors"))) =
{
/* Initial stack */
{
/* Initial stack */
IDLE_STACK,
IDLE_STACK,
/* Reset exception handler */
/* Reset exception handler */
(unsigned)&__start,
(unsigned)&__start,
/* Vectors 2 - n point directly at the generic handler */
/* Vectors 2 - n point directly at the generic handler */
[2 ... (15 + ARMV6M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common
};
[2 ... (15 + ARMV6M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common
};

2
arch/arm/src/armv7-a/arm_syscall.c
View File

@ -128,7 +128,7 @@ static void dispatch_syscall(void)
" str lr, [sp, #12]\n" /* Save lr in the stack frame */
" ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */
" ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this SYSCALL */
" blx ip\n" /* Call the stub (modifies lr)*/
" blx ip\n" /* Call the stub (modifies lr) */
" ldr lr, [sp, #12]\n" /* Restore lr */
" add sp, sp, #16\n" /* Destroy the stack frame */
" mov r2, r0\n" /* R2=Save return value in R2 */

2
arch/arm/src/armv7-a/arm_virtpgaddr.c
View File

@ -85,4 +85,4 @@ uintptr_t arm_virtpgaddr(uintptr_t paddr)
return 0;
}
#endif /* CONFIG_MM_PGALLOC && CONFIG_ARCH_PGPOOL_MAPPING*/
#endif /* CONFIG_MM_PGALLOC && CONFIG_ARCH_PGPOOL_MAPPING */

2
arch/arm/src/armv7-m/arch_enable_dcache.c
View File

@ -114,7 +114,7 @@ void arch_enable_dcache(void)
}
while (tmpways--);
}
while(sets--);
while (sets--);
ARM_DSB();

2
arch/arm/src/armv7-m/up_svcall.c
View File

@ -130,7 +130,7 @@ static void dispatch_syscall(void)
" str lr, [sp, #12]\n" /* Save lr in the stack frame */
" ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */
" ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this syscall */
" blx ip\n" /* Call the stub (modifies lr)*/
" blx ip\n" /* Call the stub (modifies lr) */
" ldr lr, [sp, #12]\n" /* Restore lr */
" add sp, sp, #16\n" /* Destroy the stack frame */
" mov r2, r0\n" /* R2=Save return value in R2 */

16
arch/arm/src/armv7-m/up_vectors.c
View File

@ -80,16 +80,16 @@ extern char _ebss;
*/
unsigned _vectors[] __attribute__((section(".vectors"))) =
{
/* Initial stack */
{
/* Initial stack */
IDLE_STACK,
IDLE_STACK,
/* Reset exception handler */
/* Reset exception handler */
(unsigned)&__start,
(unsigned)&__start,
/* Vectors 2 - n point directly at the generic handler */
/* Vectors 2 - n point directly at the generic handler */
[2 ... (15 + ARMV7M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common
};
[2 ... (15 + ARMV7M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common
};

19
arch/arm/src/c5471/c5471_ethernet.c
View File

@ -871,11 +871,11 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
/* Words #0 and #1 of descriptor */
while (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc))
{
/* Loop until the SWITCH lets go of the descriptor giving us access
* rights to submit our new ether frame to it.
*/
}
{
/* Loop until the SWITCH lets go of the descriptor giving us access
* rights to submit our new ether frame to it.
*/
}
if (bfirstframe)
{
@ -1683,7 +1683,7 @@ static int c5471_ifup(struct net_driver_s *dev)
ndbg("Bringing up: %d.%d.%d.%d\n",
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Initilize Ethernet interface */
@ -2244,12 +2244,12 @@ void up_netinitialize(void)
g_c5471[0].c_dev.d_addmac = c5471_addmac; /* Add multicast MAC address */
g_c5471[0].c_dev.d_rmmac = c5471_rmmac; /* Remove multicast MAC address */
#endif
g_c5471[0].c_dev.d_private = (void*)g_c5471; /* Used to recover private state from dev */
g_c5471[0].c_dev.d_private = (void*)g_c5471; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmisstions */
g_c5471[0].c_txpoll = wd_create(); /* Create periodic poll timer */
g_c5471[0].c_txtimeout = wd_create(); /* Create TX timeout timer */
g_c5471[0].c_txpoll = wd_create(); /* Create periodic poll timer */
g_c5471[0].c_txtimeout = wd_create(); /* Create TX timeout timer */
/* Register the device with the OS so that socket IOCTLs can be performed */
@ -2257,4 +2257,3 @@ void up_netinitialize(void)
}
#endif /* CONFIG_NET */

18
arch/arm/src/c5471/c5471_serial.c
View File

@ -562,18 +562,18 @@ static int up_interrupt(int irq, void *context)
/* Is this an interrupt from the IrDA UART? */
if (irq == C5471_IRQ_UART_IRDA)
{
/* Save the currently enabled IrDA UART interrupts
* so that we can restore the IrDA interrupt state
* below.
*/
{
/* Save the currently enabled IrDA UART interrupts
* so that we can restore the IrDA interrupt state
* below.
*/
ier_val = up_inserial(priv, UART_IER_OFFS);
ier_val = up_inserial(priv, UART_IER_OFFS);
/* Then disable all IrDA UART interrupts */
/* Then disable all IrDA UART interrupts */
up_serialout(priv, UART_IER_OFFS, 0);
}
up_serialout(priv, UART_IER_OFFS, 0);
}
/* Receive characters from the RX fifo */

7
arch/arm/src/c5471/c5471_timerisr.c
View File

@ -92,10 +92,10 @@
int up_timerisr(int irq, uint32_t *regs)
{
/* Process timer interrupt */
/* Process timer interrupt */
sched_process_timer();
return 0;
sched_process_timer();
return 0;
}
/****************************************************************************
@ -125,4 +125,3 @@ void up_timer_initialize(void)
irq_attach(C5471_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
up_enable_irq(C5471_IRQ_SYSTIMER);
}

2
arch/arm/src/c5471/c5471_watchdog.c
View File

@ -296,7 +296,7 @@ static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
/* Process the IOCTL command (see arch/watchdog.h) */
switch(cmd)
switch (cmd)
{
case WDIOC_KEEPALIVE:
wdt_setusec(MAX_WDT_USEC);

2
arch/arm/src/calypso/calypso_heap.c
View File

@ -80,7 +80,7 @@ void up_addregion(void)
/* Disable watchdog in first non-common function */
wdog_enable(0);
#endif
// XXX: change to initialization of extern memory with save defaults
/* XXX: change to initialization of extern memory with save defaults */
/* Configure memory interface */
calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1);
calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1);

4
arch/arm/src/calypso/calypso_keypad.c
View File

@ -143,7 +143,7 @@ static int pwr_btn_dec(uint32_t * state, uint8_t reg, char *buf, size_t * len)
*state |= 0x80000000;
}
return 1; // break loop in caller
return 1; /* break loop in caller */
}
else
{
@ -164,7 +164,7 @@ static int pwr_btn_dec(uint32_t * state, uint8_t reg, char *buf, size_t * len)
}
}
return 0; // continue with other columns
return 0; /* Continue with other columns */
}
/****************************************************************************

22
arch/arm/src/calypso/calypso_serial.c
View File

@ -73,7 +73,9 @@
#if UART_FCR_OFFS == UART_EFR_OFFS
# define UART_MULTIPLEX_REGS
// HW flow control not supported yet
/* HW flow control not supported yet */
# undef CONFIG_UART_HWFLOWCONTROL
#endif
@ -622,18 +624,18 @@ static int up_interrupt(int irq, void *context)
/* Is this an interrupt from the IrDA UART? */
if (irq == UART_IRQ_IRDA)
{
/* Save the currently enabled IrDA UART interrupts
* so that we can restore the IrDA interrupt state
* below.
*/
{
/* Save the currently enabled IrDA UART interrupts
* so that we can restore the IrDA interrupt state
* below.
*/
ier_val = up_inserial(priv, UART_IER_OFFS);
ier_val = up_inserial(priv, UART_IER_OFFS);
/* Then disable all IrDA UART interrupts */
/* Then disable all IrDA UART interrupts */
up_serialout(priv, UART_IER_OFFS, 0);
}
up_serialout(priv, UART_IER_OFFS, 0);
}
/* Receive characters from the RX fifo */

24
arch/arm/src/calypso/calypso_spi.c
View File

@ -223,18 +223,18 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
/* wait until the transfer is complete */
while (1)
{
reg_status = getreg16(SPI_REG(REG_STATUS));
dbg("status=0x%04x ", reg_status);
if (din && (reg_status & SPI_STATUS_RE))
{
break;
}
else if (reg_status & SPI_STATUS_WE)
{
break;
}
}
{
reg_status = getreg16(SPI_REG(REG_STATUS));
dbg("status=0x%04x ", reg_status);
if (din && (reg_status & SPI_STATUS_RE))
{
break;
}
else if (reg_status & SPI_STATUS_WE)
{
break;
}
}
/* FIXME: calibrate how much delay we really need (seven 13MHz cycles) */

10
arch/arm/src/calypso/calypso_timer.c
View File

@ -161,11 +161,11 @@ void wdog_enable(int on)
void wdog_reset(void)
{
// enable watchdog
/* Enable watchdog */
putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE));
// force expiration
/* Force expiration */
putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
@ -186,10 +186,10 @@ void wdog_reset(void)
int up_timerisr(int irq, uint32_t *regs)
{
/* Process timer interrupt */
/* Process timer interrupt */
sched_process_timer();
return 0;
sched_process_timer();
return 0;
}
/****************************************************************************

2
arch/arm/src/common/up_checkstack.c
View File

@ -136,7 +136,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
}
up_putc(ch);
}
}
up_putc('\n');
}

2
arch/arm/src/common/up_createstack.c
View File

@ -231,7 +231,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
return OK;
}
return ERROR;
return ERROR;
}
/****************************************************************************

2
arch/arm/src/common/up_interruptcontext.c
View File

@ -66,5 +66,5 @@
bool up_interrupt_context(void)
{
return current_regs != NULL;
return current_regs != NULL;
}

12
arch/arm/src/common/up_vfork.c
View File

@ -210,12 +210,12 @@ pid_t up_vfork(const struct vfork_s *context)
svdbg("Child: stack base:%08x SP:%08x FP:%08x\n",
child->cmn.adj_stack_ptr, newsp, newfp);
/* Update the stack pointer, frame pointer, and volatile registers. When
* the child TCB was initialized, all of the values were set to zero.
* up_initial_state() altered a few values, but the return value in R0
* should be cleared to zero, providing the indication to the newly started
* child thread.
*/
/* Update the stack pointer, frame pointer, and volatile registers. When
* the child TCB was initialized, all of the values were set to zero.
* up_initial_state() altered a few values, but the return value in R0
* should be cleared to zero, providing the indication to the newly started
* child thread.
*/
child->cmn.xcp.regs[REG_R4] = context->r4; /* Volatile register r4 */
child->cmn.xcp.regs[REG_R5] = context->r5; /* Volatile register r5 */

18
arch/arm/src/dm320/dm320_framebuffer.c
View File

@ -1201,15 +1201,15 @@ static int dm320_putcmap(FAR struct fb_vtable_s *vtable, FAR struct fb_cmap_s *c
flags = irqsave();
for (i = cmap.first, len = 0; i < 256 && len < cmap.len, i++, len++)
{
/* Convert the RGB to YUV */
/* Convert the RGB to YUV */
nxgl_rgb2yuv(cmap->red[i], cmap->green[i], cmap->blue[i], &y, &u, &v);
nxgl_rgb2yuv(cmap->red[i], cmap->green[i], cmap->blue[i], &y, &u, &v);
/* Program the CLUT */
/* Program the CLUT */
while (getreg16(DM320_OSD_MISCCTL) & 0x8);
putreg16(((uint16_t)y) << 8 | uint16_t(u)), DM320_OSD_CLUTRAMYCB);
putreg16(((uint16_t)v << 8 | i), DM320_OSD_CLUTRAMCR);
while (getreg16(DM320_OSD_MISCCTL) & 0x8);
putreg16(((uint16_t)y) << 8 | uint16_t(u)), DM320_OSD_CLUTRAMYCB);
putreg16(((uint16_t)v << 8 | i), DM320_OSD_CLUTRAMCR);
}
/* Select RAM clut */
@ -1296,10 +1296,10 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs
{
gvdbg("x=%d y=%d\n", settings->pos.x, settings->pos.y);
if (settings->pos.x > MAX_YRES)
{
if (settings->pos.x > MAX_YRES)
{
settings->pos.x = MAX_YRES;
}
}
if (settings->pos.y > MAX_YRES)
{

6
arch/arm/src/dm320/dm320_irq.c
View File

@ -102,9 +102,9 @@ void up_irqinitialize(void)
putreg16(0xffff, DM320_INTC_IRQ1);
putreg16(0xffff, DM320_INTC_IRQ2);
/* Make sure that the base addresses are zero and that
* the table increment is 4 bytes.
*/
/* Make sure that the base addresses are zero and that
* the table increment is 4 bytes.
*/
putreg16(0, DM320_INTC_EABASE0);
putreg16(0, DM320_INTC_EABASE1);

6
arch/arm/src/dm320/dm320_timerisr.c
View File

@ -119,10 +119,10 @@
int up_timerisr(int irq, uint32_t *regs)
{
/* Process timer interrupt */
/* Process timer interrupt */
sched_process_timer();
return 0;
sched_process_timer();
return 0;
}
/****************************************************************************

22
arch/arm/src/dm320/dm320_usbdev.c
View File

@ -441,10 +441,11 @@ static uint8_t dm320_getreg8(uint32_t addr)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return val;
}
}
@ -727,7 +728,7 @@ static int dm320_ep0write(uint8_t *buf, uint16_t nbytes)
uint16_t bytesleft;
uint16_t nwritten;
if ( nbytes <= DM320_EP0MAXPACKET)
if (nbytes <= DM320_EP0MAXPACKET)
{
bytesleft = nbytes;
csr0 |= USB_PERCSR0_DATAEND; /* Transaction end bit */
@ -762,13 +763,13 @@ static int dm320_epwrite(uint8_t epphy, uint8_t *buf, uint16_t nbytes)
uint16_t bytesleft;
int ret = ERROR;
if (/*epphy < USB_EP0_SELECT || */ epphy >= DM320_NENDPOINTS)
if (/* epphy < USB_EP0_SELECT || */ epphy >= DM320_NENDPOINTS)
{
return ret;
}
dm320_putreg8(epphy, DM320_USB_INDEX);
if (epphy == USB_EP0_SELECT )
if (epphy == USB_EP0_SELECT)
{
return dm320_ep0write(buf, nbytes);
}
@ -813,7 +814,7 @@ static int dm320_epread(uint8_t epphy, uint8_t *buf, uint16_t nbytes)
int bytesleft;
int ret = ERROR;
if (/*epphy < USB_EP0_SELECT || */ epphy >= DM320_NENDPOINTS)
if (/* epphy < USB_EP0_SELECT || */ epphy >= DM320_NENDPOINTS)
{
return ret;
}
@ -1848,7 +1849,7 @@ static void dm320_ctrlinitialize(FAR struct dm320_usbdev_s *priv)
priv->paddr = 0;
dm320_putreg8(0, DM320_USB_FADDR);
/* Finished -- set default endpoint as EP0*/
/* Finished -- set default endpoint as EP0 */
dm320_putreg8(USB_EP0_SELECT, DM320_USB_INDEX);
}
@ -2133,6 +2134,7 @@ static int dm320_epcancel(struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req)
return -EINVAL;
}
#endif
usbtrace(TRACE_EPCANCEL, privep->epphy);
priv = privep->dev;
@ -2516,7 +2518,7 @@ int usbdev_register(FAR struct usbdevclass_driver_s *driver)
/* Hook up the driver */
g_usbdev.driver = driver;
g_usbdev.driver = driver;
/* Then bind the class driver */

12
arch/arm/src/efm32/efm32_adc.c
View File

@ -113,8 +113,8 @@ struct efm32_dev_s
/* ADC Register access */
static uint32_t adc_getreg( struct efm32_dev_s *priv, int offset);
static void adc_putreg( struct efm32_dev_s *priv, int offset, uint32_t value);
static uint32_t adc_getreg(struct efm32_dev_s *priv, int offset);
static void adc_putreg(struct efm32_dev_s *priv, int offset, uint32_t value);
static void adc_hw_reset(struct efm32_dev_s *priv, bool reset);
/* ADC Interrupt Handler */
@ -662,9 +662,9 @@ uint8_t ADC_TimebaseCalc(uint32_t hfperFreq)
/* Just in case, make sure we get non-zero freq for below calculation */
if (!hfperFreq)
{
hfperFreq = 1;
}
{
hfperFreq = 1;
}
}
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
@ -675,7 +675,7 @@ uint8_t ADC_TimebaseCalc(uint32_t hfperFreq)
* See reference manual for details.
*/
if (hfperFreq > 32000000 )
if (hfperFreq > 32000000)
{
hfperFreq = 32000000;
}

4
arch/arm/src/efm32/efm32_clockconfig.c
View File

@ -154,7 +154,7 @@ static inline void efm32_statuswait(uint32_t bitset)
{
/* Wait for clock to stabilize if requested */
while ((getreg32(EFM32_CMU_STATUS) & bitset) == 0);
while ((getreg32(EFM32_CMU_STATUS) & bitset) == 0);
}
/****************************************************************************
@ -502,7 +502,7 @@ static inline uint32_t efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv)
****************************************************************************/
#ifdef CONFIG_EFM32_LECLOCK
uint32_t efm32_coreleclk_config( int frequency )
uint32_t efm32_coreleclk_config(int frequency)
{
#ifdef CMU_CTRL_HFLE
uint32_t regval;

8
arch/arm/src/efm32/efm32_flash.c
View File

@ -240,7 +240,9 @@ int __ramfunc__ msc_load_verify_address(uint32_t* address)
/* Check for invalid address */
if (status & MSC_STATUS_INVADDR)
return -EINVAL;
{
return -EINVAL;
}
/* Check for write protected page */
@ -374,7 +376,7 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words,
DEBUGASSERT(BOARD_SYSTEM_FREQUENCY >= 1000000);
word_index = 0;
while(word_index < num_words)
while (word_index < num_words)
{
putreg32(*data++,EFM32_MSC_WDATA);
word_index++;
@ -431,7 +433,7 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words,
word_index = 0;
while(word_index < num_words)
while (word_index < num_words)
{
/* Wait for the MSC to be ready for the next word. */

2
arch/arm/src/efm32/efm32_gpio.c
View File

@ -57,7 +57,7 @@
#define __GPIO_DOUT (1 << 2) /* Bit 2: An input modified with DOUT setting */
#define __GPIO_DRIVE (1 << 3) /* Bit 3: An output with drive selection */
/************************************************************************************
/************************************************************************************
* Private Data
************************************************************************************/

24
arch/arm/src/efm32/efm32_i2c.c
View File

@ -126,7 +126,7 @@
/* Macros to convert a I2C pin to a GPIO output */
#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD )
#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD)
#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
@ -873,8 +873,8 @@ static void efm32_i2c_setclock(FAR struct efm32_i2c_priv_s *priv,
#if defined(CONFIG_EFM32_I2C_CLHR_FAST)
# define n (11 + 6) /* Ratio is 11:3 */
#elif defined(CONFIG_EFM32_I2C_CLHR_ASYMMETRIC)
# define n ( 6 + 3) /* Ratio is 6:3 */
#else /* CLHR STANDARD */
# define n (6 + 3) /* Ratio is 6:3 */
#else /* CLHR STANDARD */
# define n ( 4 + 4) /* Ratio is 4:4 */
#endif
@ -1284,7 +1284,6 @@ static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv)
}
done:
if (priv->i2c_state == I2CSTATE_DONE)
{
#ifndef CONFIG_I2C_POLLED
@ -1607,35 +1606,35 @@ static int efm32_i2c_process(FAR struct i2c_dev_s *dev,
{
/* Check for error status conditions */
switch(priv->result)
switch (priv->result)
{
/* Arbitration lost during transfer. */
/* Arbitration lost during transfer. */
case I2CRESULT_ARBLOST:
errval = EAGAIN;
break;
/* NACK received during transfer. */
/* NACK received during transfer. */
case I2CRESULT_NACK:
errval = ENXIO;
break;
/* SW fault. */
/* SW fault. */
case I2CRESULT_SWFAULT:
errval = EIO;
break;
/* Usage fault. */
/* Usage fault. */
case I2CRESULT_USAGEFAULT:
errval = EINTR;
break;
/* Bus error during transfer (misplaced START/STOP).
* I2C Bus is for some reason busy
*/
/* Bus error during transfer (misplaced START/STOP).
* I2C Bus is for some reason busy
*/
case I2CRESULT_BUSERR:
errval = EBUSY;
@ -1975,7 +1974,6 @@ int up_i2creset(FAR struct i2c_dev_s *dev)
ret = OK;
out:
/* Release the port for re-use by other clients */
efm32_i2c_sem_post(dev);

4
arch/arm/src/efm32/efm32_irq.c
View File

@ -313,8 +313,8 @@ static int efm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
else
{
*regaddr = NVIC_SYSHCON;
if (irq == EFM32_IRQ_MEMFAULT)
*regaddr = NVIC_SYSHCON;
if (irq == EFM32_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}

12
arch/arm/src/efm32/efm32_leserial.c
View File

@ -343,9 +343,9 @@ static void efm32_disableuartint(struct efm32_leuart_s *priv, uint32_t *ien)
flags = irqsave();
if (ien)
{
*ien = priv->ien;
}
{
*ien = priv->ien;
}
efm32_restoreuartint(priv, 0);
irqrestore(flags);
@ -362,12 +362,12 @@ static void efm32_disableuartint(struct efm32_leuart_s *priv, uint32_t *ien)
static int efm32_setup(struct uart_dev_s *dev)
{
struct efm32_leuart_s *priv = (struct efm32_leuart_s*)dev->priv;
struct efm32_leuart_s *priv = (struct efm32_leuart_s*)dev->priv;
#ifndef CONFIG_SUPPRESS_LEUART_CONFIG
const struct efm32_config_s *config = priv->config;
const struct efm32_config_s *config = priv->config;
/* Configure the UART as an RS-232 UART */
/* Configure the UART as an RS-232 UART */
efm32_leuartconfigure(config->uartbase, config->baud, config->parity,
config->bits, config->stop2);

14
arch/arm/src/efm32/efm32_pwm.c
View File

@ -410,7 +410,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
#error "Not implemented ! Sorry"
#endif
if ( efm32_timer_set_freq(priv->base,priv->pclk,info->frequency) < 0 )
if (efm32_timer_set_freq(priv->base,priv->pclk,info->frequency) < 0)
{
pwmdbg("Cannot set TIMER frequency %dHz from clock %dHz\n",
info->frequency,
@ -421,7 +421,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
regval = ((uint32_t)(priv->pinloc)) << _TIMER_ROUTE_LOCATION_SHIFT;
switch(priv->channel)
switch (priv->channel)
{
case 0:
regval |= _TIMER_ROUTE_CC0PEN_MASK;
@ -439,7 +439,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
ASSERT(false);
}
pwm_putreg( priv, EFM32_TIMER_ROUTE_OFFSET, regval );
pwm_putreg(priv, EFM32_TIMER_ROUTE_OFFSET, regval);
regval = (info->duty * pwm_getreg(priv, EFM32_TIMER_TOP_OFFSET)) >> 16;
pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCV_OFFSET , regval);
@ -449,11 +449,11 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
(_TIMER_CC_CTRL_CMOA_CLEAR << _TIMER_CC_CTRL_CMOA_SHIFT) | \
(_TIMER_CC_CTRL_COFOA_SET << _TIMER_CC_CTRL_COFOA_SHIFT) ;
pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CTRL_OFFSET, regval );
pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CTRL_OFFSET, regval);
/* Start Timer */
pwm_putreg(priv, EFM32_TIMER_CMD_OFFSET, TIMER_CMD_START );
pwm_putreg(priv, EFM32_TIMER_CMD_OFFSET, TIMER_CMD_START);
pwm_dumpregs(priv, "After starting");
return OK;
}
@ -676,7 +676,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
/* Dnable TIMER clock */
switch(priv->timid)
switch (priv->timid)
{
case 0:
modifyreg32(EFM32_CMU_HFPERCLKEN0,0,CMU_HFPERCLKEN0_TIMER0);
@ -819,7 +819,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
pwm_putreg(priv, EFM32_TIMER_CMD_OFFSET, TIMER_CMD_STOP);
irqrestore( flags);
irqrestore(flags);
pwm_dumpregs(priv, "After stop");
return OK;

4
arch/arm/src/efm32/efm32_rtc_burtc.c
View File

@ -189,9 +189,9 @@ static int efm32_rtc_burtc_interrupt(int irq, void *context)
uint32_t source = getreg32(EFM32_BURTC_IF);
if (source & BURTC_IF_LFXOFAIL)
{
{
burtcdbg("BURTC_IF_LFXOFAIL");
}
}
#ifdef CONFIG_RTC_HIRES
if (source & BURTC_IF_OF)

6
arch/arm/src/efm32/efm32_serial.c
View File

@ -593,9 +593,9 @@ static void efm32_disableuartint(struct efm32_usart_s *priv, uint32_t *ien)
flags = irqsave();
if (ien)
{
*ien = priv->ien;
}
{
*ien = priv->ien;
}
efm32_restoreuartint(priv, 0);
irqrestore(flags);

22
arch/arm/src/efm32/efm32_spi.c
View File

@ -903,7 +903,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
* = 128 * fHFPERCLK / (256 + CLKDIV)
*/
actual = (BOARD_HFPERCLK_FREQUENCY << 7) / ( 256 + clkdiv);
actual = (BOARD_HFPERCLK_FREQUENCY << 7) / (256 + clkdiv);
spivdbg("frequency=%u actual=%u\n", frequency, actual);
#ifndef CONFIG_SPI_OWNBUS
@ -1745,18 +1745,18 @@ struct spi_dev_s *efm32_spi_initialize(int port)
/* Initialize the SPI device */
ret = spi_portinitialize(priv);
if (ret < 0)
{
spidbg("ERROR: Failed to initialize SPI port %d\n", port);
irqrestore(flags);
return NULL;
}
ret = spi_portinitialize(priv);
if (ret < 0)
{
spidbg("ERROR: Failed to initialize SPI port %d\n", port);
irqrestore(flags);
return NULL;
}
/* Now we are initialized */
/* Now we are initialized */
priv->initialized = true;
irqrestore(flags);
priv->initialized = true;
irqrestore(flags);
}
return (struct spi_dev_s *)priv;

2
arch/arm/src/efm32/efm32_start.c
View File

@ -312,6 +312,6 @@ void __start(void)
/* Shouldn't get here */
for(;;);
for (;;);
#endif
}

20
arch/arm/src/efm32/efm32_timer.c
View File

@ -191,11 +191,13 @@ void efm32_timer_reset(uintptr_t base)
putreg32(_TIMER_IEN_RESETVALUE, base + EFM32_TIMER_STATUS_OFFSET );
putreg32(_TIMER_IFC_MASK, base + EFM32_TIMER_IEN_OFFSET );
putreg32(_TIMER_TOP_RESETVALUE, base + EFM32_TIMER_IF_OFFSET );
putreg32(_TIMER_TOPB_RESETVALUE, base + EFM32_TIMER_CTRL_OFFSET );
putreg32(_TIMER_CNT_RESETVALUE, base + EFM32_TIMER_CMD_OFFSET );
putreg32(_TIMER_TOPB_RESETVALUE, base + EFM32_TIMER_CTRL_OFFSET );
putreg32(_TIMER_CNT_RESETVALUE, base + EFM32_TIMER_CMD_OFFSET );
/* Do not reset route register, setting should be done independently
* (Note: ROUTE register may be locked by DTLOCK register.)
*/
/* Do not reset route register, setting should be done independently */
/* (Note: ROUTE register may be locked by DTLOCK register.) */
//putreg32(_TIMER_ROUTE_RESETVALUE, base + EFM32_TIMER_ROUTE_OFFSET );
for(i = 0; i < EFM32_TIMER_NCC; i++)
@ -219,13 +221,13 @@ void efm32_timer_reset(uintptr_t base)
putreg32(_TIMER_DTOGEN_RESETVALUE,base + EFM32_TIMER_DTOGEN_OFFSET );
putreg32(_TIMER_DTFAULTC_MASK, base + EFM32_TIMER_DTFAULTC_OFFSET );
#endif
}
}
/****************************************************************************
* Name: efm32_timer_set_freq
*
* Description:
* set prescaler and top timer with best value to have "freq"
* set prescaler and top timer with best value to have "freq"
*
* Input parameters:
* base - A base address of timer
@ -239,14 +241,14 @@ void efm32_timer_reset(uintptr_t base)
int efm32_timer_set_freq(uintptr_t base, uint32_t clk_freq, uint32_t freq)
{
int prescaler = 0;
int cnt_freq = clk_freq>>16;
int cnt_freq = clk_freq >> 16;
int reload;
while ( cnt_freq > freq )
while (cnt_freq > freq)
{
prescaler++;
cnt_freq>>=1;
if ( prescaler > (_TIMER_CTRL_PRESC_MASK>>_TIMER_CTRL_PRESC_SHIFT))
if (prescaler > (_TIMER_CTRL_PRESC_MASK>>_TIMER_CTRL_PRESC_SHIFT))
{
return -1;
}

9
arch/arm/src/efm32/efm32_usbdev.c
View File

@ -813,10 +813,11 @@ static uint32_t efm32_getreg(uint32_t addr)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return val;
}
}

21
arch/arm/src/efm32/efm32_usbhost.c
View File

@ -73,8 +73,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ***************************************************************/
/*
* EFM32 USB OTG FS Host Driver Support
/* EFM32 USB OTG FS Host Driver Support
*
* Pre-requisites
*
@ -806,14 +805,14 @@ static void efm32_chan_free(FAR struct efm32_usbhost_s *priv, int chidx)
static inline void efm32_chan_freeall(FAR struct efm32_usbhost_s *priv)
{
uint8_t chidx;
uint8_t chidx;
/* Free all host channels */
/* Free all host channels */
for (chidx = 2; chidx < EFM32_NHOST_CHANNELS; chidx ++)
{
efm32_chan_free(priv, chidx);
}
for (chidx = 2; chidx < EFM32_NHOST_CHANNELS; chidx ++)
{
efm32_chan_free(priv, chidx);
}
}
/****************************************************************************
@ -2282,7 +2281,7 @@ static void efm32_out_next(FAR struct efm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK?*/
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2936,11 +2935,11 @@ static void efm32_gint_disconnected(FAR struct efm32_usbhost_s *priv)
/* Are we bound to a class driver? */
if ( priv->rhport.hport.devclass)
if (priv->rhport.hport.devclass)
{
/* Yes.. Disconnect the class driver */
CLASS_DISCONNECTED( priv->rhport.hport.devclass);
CLASS_DISCONNECTED(priv->rhport.hport.devclass);
priv->rhport.hport.devclass = NULL;
}

4
arch/arm/src/imx/imx_gpio.c
View File

@ -106,7 +106,7 @@ void imxgpio_configpfoutput(int port, int bit)
{
imxgpio_configinput(port, bit); /* Same as input except: */
imxgpio_peripheralfunc(port, bit); /* Use as peripheral */
imxgpio_primaryperipheralfunc(port, bit); /* Primary function*/
imxgpio_primaryperipheralfunc(port, bit); /* Primary function */
imxgpio_dirout(port, bit); /* Make output */
}
@ -118,5 +118,5 @@ void imxgpio_configpfinput(int port, int bit)
{
imxgpio_configinput(port, bit); /* Same as input except: */
imxgpio_peripheralfunc(port, bit); /* Use as peripheral */
imxgpio_primaryperipheralfunc(port, bit); /* Primary function*/
imxgpio_primaryperipheralfunc(port, bit); /* Primary function */
}

20
arch/arm/src/imx/imx_serial.c
View File

@ -524,7 +524,7 @@ static int up_setup(struct uart_dev_s *dev)
/* Set CTS trigger level */
regval |= 30 << UART_UCR4_CTSTL_SHIFT;
}
}
#endif
/* i.MX reference clock (PERCLK1) is configured for 16MHz */
@ -546,15 +546,15 @@ static int up_setup(struct uart_dev_s *dev)
* First, select a closest value we can for the divider
*/
div = (IMX_PERCLK1_FREQ >> 4) / priv->baud;
if (div > 7)
{
div = 7;
}
else if (div < 1)
{
div = 1;
}
div = (IMX_PERCLK1_FREQ >> 4) / priv->baud;
if (div > 7)
{
div = 7;
}
else if (div < 1)
{
div = 1;
}
/* Now find the numerator and denominator. These must have
* the ratio baud/(PERCLK / div / 16), but the values cannot

8
arch/arm/src/imx/imx_spi.c
View File

@ -139,7 +139,7 @@ struct imx_spidev_s
* Private Function Prototypes
****************************************************************************/
/* SPI register access */
/* SPI register access */
static inline uint32_t spi_getreg(struct imx_spidev_s *priv, unsigned int offset);
static inline void spi_putreg(struct imx_spidev_s *priv, unsigned int offset, uint32_t value);
@ -468,11 +468,11 @@ static void spi_startxfr(struct imx_spidev_s *priv, int ntxd)
*/
if (ntxd > 0)
{
{
regval = spi_getreg(priv, CSPI_CTRL_OFFSET);
regval |= CSPI_CTRL_XCH;
spi_putreg(priv, CSPI_CTRL_OFFSET, regval);
}
}
}
/****************************************************************************
@ -773,7 +773,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
freqbits = CSPI_CTRL_DIV256;
actual = IMX_PERCLK2_FREQ / 256;
}
else /*if (frequency >= IMX_PERCLK2_FREQ / 512) */
else /* if (frequency >= IMX_PERCLK2_FREQ / 512) */
{
freqbits = CSPI_CTRL_DIV512;
actual = IMX_PERCLK2_FREQ / 512;

6
arch/arm/src/kinetis/kinetis_enet.c
View File

@ -394,7 +394,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
txdesc->length = kinesis_swap16(priv->dev.d_len);
#ifdef CONFIG_ENET_ENHANCEDBD
txdesc->bdu = 0x00000000;
txdesc->status2 = TXDESC_INT | TXDESC_TS; // | TXDESC_IINS | TXDESC_PINS;
txdesc->status2 = TXDESC_INT | TXDESC_TS; /* | TXDESC_IINS | TXDESC_PINS; */
#endif
txdesc->status1 = (TXDESC_R | TXDESC_L | TXDESC_TC | TXDESC_W);
@ -480,7 +480,7 @@ static int kinetis_txpoll(struct net_driver_s *dev)
if (kinetics_txringfull(priv))
{
return -EBUSY;
return -EBUSY;
}
}
@ -603,7 +603,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
*/
if (priv->dev.d_len > 0)
{
{
/* Update the Ethernet header with the correct MAC address */
#ifdef CONFIG_NET_IPv4

4
arch/arm/src/kinetis/kinetis_irq.c
View File

@ -287,8 +287,8 @@ static int kinetis_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
else
{
*regaddr = NVIC_SYSHCON;
if (irq == KINETIS_IRQ_MEMFAULT)
*regaddr = NVIC_SYSHCON;
if (irq == KINETIS_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}

2
arch/arm/src/kinetis/kinetis_lowputc.c
View File

@ -169,7 +169,7 @@ void up_lowputc(char ch)
while ((getreg8(CONSOLE_BASE+KINETIS_UART_S1_OFFSET) & UART_S1_TDRE) == 0);
#endif
/* Then write the character to the UART data register */
/* Then write the character to the UART data register */
putreg8((uint8_t)ch, CONSOLE_BASE+KINETIS_UART_D_OFFSET);
#endif

4
arch/arm/src/kinetis/kinetis_pinirq.c
View File

@ -128,7 +128,7 @@ static int kinetis_portinterrupt(int irq, FAR void *context,
*/
uint32_t bit = (1 << i);
if ((isfr & bit ) != 0)
if ((isfr & bit) != 0)
{
/* I think that bits may be set in the ISFR for DMA activities
* well. So, no error is declared if there is no registered
@ -372,7 +372,7 @@ void kinetis_pinirqenable(uint32_t pinset)
regval |= PORT_PCR_IRQC_ZERO;
break;
case PIN_INT_RISING : /* Interrupt on rising edge*/
case PIN_INT_RISING : /* Interrupt on rising edge */
regval |= PORT_PCR_IRQC_RISING;
break;

14
arch/arm/src/kinetis/kinetis_sdhc.c
View File

@ -1047,7 +1047,7 @@ static void kinetis_endtransfer(struct kinetis_dev_s *priv, sdio_eventset_t wkup
/* If this was a DMA transfer, make sure that DMA is stopped */
#ifdef CONFIG_SDIO_DMA
/* Stop the DMA by resetting the data path*/
/* Stop the DMA by resetting the data path */
regval = getreg32(KINETIS_SDHC_SYSCTL);
regval |= SDHC_SYSCTL_RSTD;
@ -1420,8 +1420,8 @@ static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency)
* 96MHz / 16 <= 400KHz <= 96MHz / 16 / 16 -- YES, prescaler == 16
*/
if (/*frequency >= (BOARD_CORECLK_FREQ / 2) && */
frequency <= (BOARD_CORECLK_FREQ / 2 / 16))
if (/* frequency >= (BOARD_CORECLK_FREQ / 2) && */
frequency <= (BOARD_CORECLK_FREQ / 2 / 16))
{
sdclkfs = SDHC_SYSCTL_SDCLKFS_DIV2;
prescaler = 2;
@ -1791,7 +1791,7 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar
regval |= SDHC_XFERTYP_RSPTYP_NONE;
break;
case MMCSD_R1B_RESPONSE: /* Response length 48, check busy & cmdindex*/
case MMCSD_R1B_RESPONSE: /* Response length 48, check busy & cmdindex */
regval |= (SDHC_XFERTYP_RSPTYP_LEN48BSY|SDHC_XFERTYP_CICEN|SDHC_XFERTYP_CCCEN);
break;
@ -2002,7 +2002,7 @@ static int kinetis_cancel(FAR struct sdio_dev_s *dev)
/* If this was a DMA transfer, make sure that DMA is stopped */
#ifdef CONFIG_SDIO_DMA
/* Stop the DMA by resetting the data path*/
/* Stop the DMA by resetting the data path */
regval = getreg32(KINETIS_SDHC_SYSCTL);
regval |= SDHC_SYSCTL_RSTD;
@ -2233,7 +2233,7 @@ static int kinetis_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t r
}
}
/* Return the long response in CMDRSP3..0*/
/* Return the long response in CMDRSP3..0 */
if (rlong)
{
@ -2404,7 +2404,7 @@ static sdio_eventset_t kinetis_eventwait(FAR struct sdio_dev_s *dev,
if (!timeout)
{
return SDIOWAIT_TIMEOUT;
return SDIOWAIT_TIMEOUT;
}
/* Start the watchdog timer */

6
arch/arm/src/kinetis/kinetis_serial.c
View File

@ -590,9 +590,9 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *ie)
flags = irqsave();
if (ie)
{
*ie = priv->ie;
}
{
*ie = priv->ie;
}
up_restoreuartint(priv, 0);
irqrestore(flags);

6
arch/arm/src/kinetis/kinetis_timerisr.c
View File

@ -100,10 +100,10 @@
int up_timerisr(int irq, uint32_t *regs)
{
/* Process timer interrupt */
/* Process timer interrupt */
sched_process_timer();
return 0;
sched_process_timer();
return 0;
}
/****************************************************************************

1
arch/arm/src/kl/kl_clockconfig.c
View File

@ -243,4 +243,3 @@ void kl_clockconfig(void)
//kl_traceconfig();
//kl_fbconfig();
}

4
arch/arm/src/kl/kl_gpioirq.c
View File

@ -123,7 +123,7 @@ static int kl_portinterrupt(int irq, FAR void *context,
*/
uint32_t bit = (1 << i);
if ((isfr & bit ) != 0)
if ((isfr & bit) != 0)
{
/* I think that bits may be set in the ISFR for DMA activities
* well. So, no error is declared if there is no registered
@ -322,7 +322,7 @@ void kl_gpioirqenable(uint32_t pinset)
regval |= PORT_PCR_IRQC_ZERO;
break;
case PIN_INT_RISING : /* Interrupt on rising edge*/
case PIN_INT_RISING : /* Interrupt on rising edge */
regval |= PORT_PCR_IRQC_RISING;
break;

2
arch/arm/src/kl/kl_lowgetc.c
View File

@ -120,7 +120,7 @@ int kl_lowgetc(void)
while ((getreg8(CONSOLE_BASE+KL_UART_S1_OFFSET) & UART_S1_RDRF) == 0);
/* Then read a character from the UART data register */
/* Then read a character from the UART data register */
ch = getreg8(CONSOLE_BASE+KL_UART_D_OFFSET);
#endif

2
arch/arm/src/kl/kl_lowputc.c
View File

@ -136,7 +136,7 @@ void kl_lowputc(uint32_t ch)
while ((getreg8(CONSOLE_BASE+KL_UART_S1_OFFSET) & UART_S1_TDRE) == 0);
/* Then write the character to the UART data register */
/* Then write the character to the UART data register */
putreg8((uint8_t)ch, CONSOLE_BASE+KL_UART_D_OFFSET);

14
arch/arm/src/kl/kl_serial.c
View File

@ -376,9 +376,9 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *ie)
flags = irqsave();
if (ie)
{
*ie = priv->ie;
}
{
*ie = priv->ie;
}
up_restoreuartint(priv, 0);
irqrestore(flags);
@ -595,10 +595,10 @@ static int up_interrupts(int irq, void *context)
* OR: Receiver Overrun Flag. To clear OR, write a logic 1 to the OR flag.
*/
if ((s1 & UART_S1_ERRORS) != 0)
{
up_serialout(priv, KL_UART_S1_OFFSET, (s1 & UART_S1_ERRORS));
}
if ((s1 & UART_S1_ERRORS) != 0)
{
up_serialout(priv, KL_UART_S1_OFFSET, (s1 & UART_S1_ERRORS));
}
}
return OK;

6
arch/arm/src/kl/kl_timerisr.c
View File

@ -115,10 +115,10 @@
int up_timerisr(int irq, uint32_t *regs)
{
/* Process timer interrupt */
/* Process timer interrupt */
sched_process_timer();
return 0;
sched_process_timer();
return 0;
}
/****************************************************************************

32
arch/arm/src/lpc11xx/lpc11_gpioint.c
View File

@ -163,10 +163,10 @@ static void lpc11_setintedge(uint32_t intbase, unsigned int pin,
static int lpc11_irq2port(int irq)
{
/* Set 1:
* LPC176x: 12 interrupts p0.0-p0.11
* LPC178x: 16 interrupts p0.0-p0.15
*/
/* Set 1:
* LPC176x: 12 interrupts p0.0-p0.11
* LPC178x: 16 interrupts p0.0-p0.15
*/
if (irq >= LPC17_VALID_FIRST0L &&
irq < (LPC17_VALID_FIRST0L + LPC17_VALID_NIRQS0L))
@ -364,24 +364,24 @@ static void lpc11_gpiodemux(uint32_t intbase, uint32_t intmask,
if ((intmask & bit) != 0)
{
/* This pin can support an interrupt. Is there an interrupt pending
* and enabled?
*/
/* This pin can support an interrupt. Is there an interrupt pending
* and enabled?
*/
if ((intstatus & bit) != 0)
{
/* Clear the interrupt status */
if ((intstatus & bit) != 0)
{
/* Clear the interrupt status */
putreg32(bit, intbase + LPC17_GPIOINT_INTCLR_OFFSET);
putreg32(bit, intbase + LPC17_GPIOINT_INTCLR_OFFSET);
/* And dispatch the interrupt */
/* And dispatch the interrupt */
irq_dispatch(irq, context);
}
irq_dispatch(irq, context);
}
/* Increment the IRQ number on each interrupt pin */
/* Increment the IRQ number on each interrupt pin */
irq++;
irq++;
}
/* Next bit */

8
arch/arm/src/lpc11xx/lpc11_i2c.c
View File

@ -198,7 +198,7 @@ static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) dev;
DEBUGASSERT(dev != NULL);
DEBUGASSERT(nbits == 7 );
DEBUGASSERT(nbits == 7);
priv->msg.addr = addr << 1;
priv->msg.flags = 0 ;
@ -378,7 +378,7 @@ static int i2c_interrupt(int irq, FAR void *context)
switch (state)
{
case 0x00: // Bus Error
case 0x00: /* Bus Error */
case 0x20:
case 0x30:
case 0x38:
@ -386,8 +386,8 @@ static int i2c_interrupt(int irq, FAR void *context)
i2c_stop(priv);
break;
case 0x08: // START
case 0x10: // Repeat START
case 0x08: /* START */
case 0x10: /* Repeat START */
putreg32(priv->msg.addr, priv->base + LPC11_I2C_DAT_OFFSET);
putreg32(I2C_CONCLR_STAC, priv->base + LPC11_I2C_CONCLR_OFFSET);
break;

4
arch/arm/src/lpc11xx/lpc11_serial.c
View File

@ -313,7 +313,7 @@ static inline uint32_t lpc11_uartcclkdiv(uint32_t baud)
* BAUD <= CCLK / 16 / MinDL
*/
return 1;
return 1;
}
#endif /* LPC111x */
@ -378,8 +378,8 @@ static inline void lpc11_uart0config(void)
#ifdef LPC111x
static inline uint32_t lpc11_uartdl(uint32_t baud, uint8_t divcode)
{
/* TODO: Calculate DL automatically */
/*TODO: Calculate DL automatically */
uint32_t num = 312;
return num;

2
arch/arm/src/lpc11xx/lpc11_spi.c
View File

@ -483,7 +483,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
* the SPI data transfer.
*/
while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0);
while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0);
/* Read the SPI Status Register again to clear the status bit */

10
arch/arm/src/lpc11xx/lpc11_timer.c
View File

@ -387,7 +387,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
flags = irqsave();
/* Power on the timer peripherals*/
/* Power on the timer peripherals */
regval = getreg32(LPC17_SYSCON_PCONP);
regval |= SYSCON_PCONP_PCTIM0;
@ -396,7 +396,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
regval |= SYSCON_PCONP_PCTIM3;
putreg32(regval, LPC17_SYSCON_PCONP);
/* Select clock for the timer peripheral*/
/* Select clock for the timer peripheral */
regval = getreg32(LPC17_SYSCON_PCLKSEL0);
regval &= ~(0x3 << 2);
@ -424,7 +424,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
*/
putreg32(((1 << 1)|(3 << 6)), LPC17_TMR0_EMR);
putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0*/
putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0 */
/* Configure the output pins GPIO3.26 */
@ -436,8 +436,8 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */
putreg32(~(0x3 << 0), LPC17_TMR1_CTCR);/* Prescaler count frequency:Fpclk/1 */
putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */
// putreg32(((1 << 0)|(3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0*/
putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1*/
// putreg32(((1 << 0)|(3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0 */
putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */
/* configure the output pins GPIO3.26 */
// lpc11_configgpio(GPIO_MAT0p1_2);

6
arch/arm/src/lpc11xx/lpc11_timerisr.c
View File

@ -115,10 +115,10 @@
int up_timerisr(int irq, uint32_t *regs)
{
/* Process timer interrupt */
/* Process timer interrupt */
sched_process_timer();
return 0;
sched_process_timer();
return 0;
}
/****************************************************************************

2
arch/arm/src/lpc17xx/lpc176x_rtc.c
View File

@ -291,7 +291,7 @@ int up_rtcinitialize(void)
{
up_enable_irq(LPC17_IRQ_RTC);
}
#endif /*CONFIG_RTC_ALARM*/
#endif /* CONFIG_RTC_ALARM */
/* Perform the one-time setup of the RTC */

32
arch/arm/src/lpc17xx/lpc17_adc.c
View File

@ -174,7 +174,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
putreg32(0x100, LPC17_ADC_INTEN); /* Enable only global interrupt */
putreg32((priv->mask) | /* Select channels 0 to 7 on ADC0 */
// (clkdiv) << 8) | /* CLKDIV = divisor to make the samples
// (clkdiv) << 8) | /* CLKDIV = divisor to make the samples
// * per second conversion rate */
((32) << 8) | /* CLKDIV = divisor to make the faster
* conversion rate */
@ -187,14 +187,14 @@ static void adc_reset(FAR struct adc_dev_s *dev)
* trigger A/D conversion) */
LPC17_ADC_CR);
#else /*CONFIG_ADC_BURSTMODE*/
#else /* CONFIG_ADC_BURSTMODE */
clkdiv = LPC17_CCLK / 8 / 65 / priv->sps;
clkdiv <<= 8;
clkdiv &= 0xff00;
putreg32(ADC_CR_PDN | ADC_CR_BURST | clkdiv | priv->mask, LPC17_ADC_CR);
#endif /*CONFIG_ADC_BURSTMODE*/
#endif /* CONFIG_ADC_BURSTMODE */
if ((priv->mask & 0x01) != 0)
{
@ -322,11 +322,11 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
putreg32(ADC_INTEN_GLOBAL, LPC17_ADC_INTEN);
#endif
#else /*CONFIG_ADC_BURSTMODE*/
#else /* CONFIG_ADC_BURSTMODE */
/* Enable only global interrupt */
putreg32(0x100, LPC17_ADC_INTEN);
#endif /*CONFIG_ADC_BURSTMODE*/
#endif /* CONFIG_ADC_BURSTMODE */
}
else
{
@ -416,7 +416,7 @@ static int adc_interrupt(int irq, void *context)
return OK;
#endif
#else /*CONFIG_ADC_BURSTMODE*/
#else /* CONFIG_ADC_BURSTMODE */
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv;
volatile uint32_t regVal, regVal2, regVal3;
@ -462,21 +462,21 @@ static int adc_interrupt(int irq, void *context)
ADC1Buffer0[0] = regVal;
ADC0IntDone = 1;
#else /*CONFIG_ADC_DIRECT_ACCESS*/
#else /* CONFIG_ADC_DIRECT_ACCESS */
#ifdef CONFIG_ADC_WORKER_THREAD
/* Store the data value plus the status bits */
ADC1Buffer0[0] = regVal;
ADC0IntDone = 1;
#else /*CONFIG_ADC_WORKER_THREAD*/
#else /* CONFIG_ADC_WORKER_THREAD */
if ((regVal) & (1 << 31))
{
adc_receive(&g_adcdev, 1, (regVal >> 4) & 0xFFF);
}
#endif /*CONFIG_ADC_WORKER_THREAD*/
#endif /*CONFIG_ADC_DIRECT_ACCESS*/
#endif /* CONFIG_ADC_WORKER_THREAD */
#endif /* CONFIG_ADC_DIRECT_ACCESS */
}
if ((priv->mask & 0x04) != 0)
@ -489,21 +489,21 @@ static int adc_interrupt(int irq, void *context)
ADC2Buffer0[0] = regVal;
ADC0IntDone = 1;
#else /*CONFIG_ADC_DIRECT_ACCESS*/
#else /* CONFIG_ADC_DIRECT_ACCESS */
#ifdef CONFIG_ADC_WORKER_THREAD
/* Store the data value plus the status bits */
ADC2Buffer0[0] = regVal;
ADC0IntDone = 1;
#else /*CONFIG_ADC_WORKER_THREAD*/
#else /* CONFIG_ADC_WORKER_THREAD */
if ((regVal) & (1 << 31))
{
adc_receive(&g_adcdev, 2, (regVal >> 4) & 0xFFF);
}
#endif /*CONFIG_ADC_WORKER_THREAD*/
#endif /*CONFIG_ADC_DIRECT_ACCESS*/
#endif /* CONFIG_ADC_WORKER_THREAD */
#endif /* CONFIG_ADC_DIRECT_ACCESS */
}
if ((priv->mask & 0x08) != 0)
@ -558,7 +558,7 @@ static int adc_interrupt(int irq, void *context)
(FAR void *)priv, 0);
}
#endif /*CONFIG_ADC_WORKER_THREAD*/
#endif /* CONFIG_ADC_WORKER_THREAD */
}
regVal3 = getreg32(LPC17_ADC_GDR); /* Read ADGDR clear the DONE and OVERRUN bits */
@ -575,7 +575,7 @@ static int adc_interrupt(int irq, void *context)
//lpc17_gpiowrite(LPCXPRESSO_GPIO0_21, 0); /* Reset pin P0.21 */
//irqrestore(saved_state);
return OK;
#endif /*CONFIG_ADC_BURSTMODE*/
#endif /* CONFIG_ADC_BURSTMODE */
}
/****************************************************************************

9
arch/arm/src/lpc17xx/lpc17_can.c
View File

@ -322,10 +322,11 @@ static void can_printreg(uint32_t addr, uint32_t value)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return;
}
}

16
arch/arm/src/lpc17xx/lpc17_ethernet.c
View File

@ -1006,7 +1006,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
*/
if (priv->lp_dev.d_len > 0)
{
{
/* Update the Ethernet header with the correct MAC address */
#ifdef CONFIG_NET_IPv4
@ -2681,16 +2681,16 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
for (phyaddr = 1; phyaddr < 32; phyaddr++)
{
/* Check if we can see the selected device ID at this
* PHY address.
*/
/* Check if we can see the selected device ID at this
* PHY address.
*/
phyreg = (unsigned int)lpc17_phyread(phyaddr, MII_PHYID1);
nvdbg("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg);
phyreg = (unsigned int)lpc17_phyread(phyaddr, MII_PHYID1);
nvdbg("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg);
/* Compare OUI bits 3-18 */
/* Compare OUI bits 3-18 */
if (phyreg == LPC17_PHYID1)
if (phyreg == LPC17_PHYID1)
{
phyreg = lpc17_phyread(phyaddr, MII_PHYID2);
nvdbg("Addr: %d PHY ID2: %04x\n", phyaddr, phyreg);

12
arch/arm/src/lpc17xx/lpc17_gpdma.c
View File

@ -481,13 +481,13 @@ int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
* has the highest priority and DMA channel 7 the lowest priority.
*/
regval = getreg32(LPC17_DMA_ENBLDCHNS);
if ((regval & chbit) != 0)
{
/* There is an active DMA on this channel! */
regval = getreg32(LPC17_DMA_ENBLDCHNS);
if ((regval & chbit) != 0)
{
/* There is an active DMA on this channel! */
return -EBUSY;
}
return -EBUSY;
}
/* 2. "Clear any pending interrupts on the channel to be used by writing
* to the DMACIntTCClear and DMACIntErrClear register. The previous

8
arch/arm/src/lpc17xx/lpc17_i2c.c
View File

@ -196,7 +196,7 @@ static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev;
DEBUGASSERT(dev != NULL);
DEBUGASSERT(nbits == 7 );
DEBUGASSERT(nbits == 7);
priv->msg.addr = addr << 1;
priv->msg.flags = 0 ;
@ -375,7 +375,7 @@ static int i2c_interrupt(int irq, FAR void *context)
switch (state)
{
case 0x00: // Bus Error
case 0x00: /* Bus Error */
case 0x20:
case 0x30:
case 0x38:
@ -383,8 +383,8 @@ static int i2c_interrupt(int irq, FAR void *context)
i2c_stop(priv);
break;
case 0x08: // START
case 0x10: // Repeat START
case 0x08: /* START */
case 0x10: /* Repeat START */
putreg32(priv->msg.addr, priv->base + LPC17_I2C_DAT_OFFSET);
putreg32(I2C_CONCLR_STAC, priv->base + LPC17_I2C_CONCLR_OFFSET);
break;

4
arch/arm/src/lpc17xx/lpc17_irq.c
View File

@ -255,8 +255,8 @@ static int lpc17_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
else
{
*regaddr = NVIC_SYSHCON;
if (irq == LPC17_IRQ_MEMFAULT)
*regaddr = NVIC_SYSHCON;
if (irq == LPC17_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}

6
arch/arm/src/lpc17xx/lpc17_mcpwm.c
View File

@ -395,7 +395,7 @@ static void mcpwm_set_apb_clock(FAR struct lpc17_mcpwmtimer_s *priv, bool on)
modifyreg32(regaddr, en_bit, 0);
}
}
#endif /*XXXXX*/
#endif
/****************************************************************************
* Name: mcpwm_setup
@ -452,7 +452,7 @@ static int mcpwm_setup(FAR struct pwm_lowerhalf_s *dev)
putreg32((0xFFFFFFFF), LPC17_MCPWM_CAPCLR);/* Clear all event capture */
/* Configure the output pins*/
/* Configure the output pins */
lpc17_configgpio(GPIO_MCPWM_MCOA0);
lpc17_configgpio(GPIO_MCPWM_MCOB0);
@ -469,7 +469,7 @@ static int mcpwm_setup(FAR struct pwm_lowerhalf_s *dev)
putreg32(400, LPC17_MCPWM_LIM0); /* Set the starting duty cycle to 0.25 */
putreg32(0, LPC17_MCPWM_MAT0); /* Reset the timer */
putreg32(100000, LPC17_MCPWM_TC1); /* Count frequency:Fpclk/100000 = 50 MHz/100000 = 500 Hz*/
putreg32(100000, LPC17_MCPWM_TC1); /* Count frequency:Fpclk/100000 = 50 MHz/100000 = 500 Hz */
putreg32(50000, LPC17_MCPWM_LIM1); /* Set the starting duty cycle to 0.5 */
putreg32(0, LPC17_MCPWM_MAT1); /* Reset the timer */

2
arch/arm/src/lpc17xx/lpc17_pwm.c
View File

@ -413,7 +413,7 @@ static void pwm_set_apb_clock(FAR struct lpc17_pwmtimer_s *priv, bool on)
modifyreg32(regaddr, en_bit, 0);
}
}
#endif /*XXXXX*/
#endif
/****************************************************************************
* Name: pwm_setup

39
arch/arm/src/lpc17xx/lpc17_sdcard.c
View File

@ -860,10 +860,11 @@ static uint8_t lpc17_log2(uint16_t value)
DEBUGASSERT(value > 0);
while (value != 1)
{
value >>= 1;
log2++;
}
{
value >>= 1;
log2++;
}
return log2;
}
@ -959,27 +960,27 @@ static void lpc17_sendfifo(struct lpc17_dev_s *priv)
}
else
{
/* No.. transfer just the bytes remaining in the user buffer,
* padding with zero as necessary to extend to a full word.
*/
/* No.. transfer just the bytes remaining in the user buffer,
* padding with zero as necessary to extend to a full word.
*/
uint8_t *ptr = (uint8_t *)priv->remaining;
int i;
uint8_t *ptr = (uint8_t *)priv->remaining;
int i;
data.w = 0;
for (i = 0; i < priv->remaining; i++)
{
data.b[i] = *ptr++;
}
data.w = 0;
for (i = 0; i < priv->remaining; i++)
{
data.b[i] = *ptr++;
}
/* Now the transfer is finished */
/* Now the transfer is finished */
priv->remaining = 0;
}
priv->remaining = 0;
}
/* Put the word in the FIFO */
/* Put the word in the FIFO */
putreg32(data.w, LPC17_SDCARD_FIFO);
putreg32(data.w, LPC17_SDCARD_FIFO);
}
}

12
arch/arm/src/lpc17xx/lpc17_serial.c
View File

@ -478,7 +478,7 @@ static uart_dev_t g_uart3port =
# undef TTYS3_DEV /* No ttyS3 */
# endif
# endif
#endif /*HAVE_CONSOLE*/
#endif /* HAVE_CONSOLE */
/************************************************************************************
* Inline Functions
@ -609,7 +609,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud)
* BAUD <= CCLK / 16 / MinDL
*/
if (baud < (LPC17_CCLK / 16 / UART_MINDL ))
if (baud < (LPC17_CCLK / 16 / UART_MINDL))
{
return SYSCON_PCLKSEL_CCLK;
}
@ -625,7 +625,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud)
* BAUD <= CCLK / 8 / MinDL
*/
else if (baud < (LPC17_CCLK / 8 / UART_MINDL ))
else if (baud < (LPC17_CCLK / 8 / UART_MINDL))
{
return SYSCON_PCLKSEL_CCLK2;
}
@ -641,7 +641,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud)
* BAUD <= CCLK / 4 / MinDL
*/
else if (baud < (LPC17_CCLK / 4 / UART_MINDL ))
else if (baud < (LPC17_CCLK / 4 / UART_MINDL))
{
return SYSCON_PCLKSEL_CCLK4;
}
@ -657,7 +657,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud)
* BAUD <= CCLK / 2 / MinDL
*/
else /* if (baud < (LPC17_CCLK / 2 / UART_MINDL )) */
else /* if (baud < (LPC17_CCLK / 2 / UART_MINDL)) */
{
return SYSCON_PCLKSEL_CCLK8;
}
@ -1256,7 +1256,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
* and reset the divider in the CLKSEL0/1 register.
*/
#if 0 // ifdef LPC176x
#if 0 /* ifdef LPC176x */
priv->cclkdiv = lpc17_uartcclkdiv(priv->baud);
#endif
/* DLAB open latch */

8
arch/arm/src/lpc17xx/lpc17_spi.c
View File

@ -474,12 +474,12 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
* data transfer.
*/
while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0);
while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0);
/* Read the SPI Status Register again to clear the status bit */
/* Read the SPI Status Register again to clear the status bit */
(void)getreg32(LPC17_SPI_SR);
nwords--;
(void)getreg32(LPC17_SPI_SR);
nwords--;
}
}

10
arch/arm/src/lpc17xx/lpc17_timer.c
View File

@ -387,7 +387,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
flags = irqsave();
/* Power on the timer peripherals*/
/* Power on the timer peripherals */
regval = getreg32(LPC17_SYSCON_PCONP);
regval |= SYSCON_PCONP_PCTIM0;
@ -396,7 +396,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
regval |= SYSCON_PCONP_PCTIM3;
putreg32(regval, LPC17_SYSCON_PCONP);
/* Select clock for the timer peripheral*/
/* Select clock for the timer peripheral */
regval = getreg32(LPC17_SYSCON_PCLKSEL0);
regval &= ~(0x3 << 2);
@ -424,7 +424,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
*/
putreg32(((1 << 1)|(3 << 6)), LPC17_TMR0_EMR);
putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0*/
putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0 */
/* Configure the output pins GPIO3.26 */
@ -436,8 +436,8 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */
putreg32(~(0x3 << 0), LPC17_TMR1_CTCR);/* Prescaler count frequency:Fpclk/1 */
putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */
// putreg32(((1 << 0)|(3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0*/
putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1*/
// putreg32(((1 << 0)|(3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0 */
putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */
/* configure the output pins GPIO3.26 */
// lpc17_configgpio(GPIO_MAT0p1_2);

6
arch/arm/src/lpc17xx/lpc17_timerisr.c
View File

@ -101,10 +101,10 @@
int up_timerisr(int irq, uint32_t *regs)
{
/* Process timer interrupt */
/* Process timer interrupt */
sched_process_timer();
return 0;
sched_process_timer();
return 0;
}
/****************************************************************************

14
arch/arm/src/lpc214x/lpc214x_timerisr.c
View File

@ -98,20 +98,20 @@ int up_timerisr(uint32_t *regs)
int up_timerisr(int irq, uint32_t *regs)
#endif
{
/* Process timer interrupt */
/* Process timer interrupt */
sched_process_timer();
sched_process_timer();
/* Clear the MR0 match interrupt */
/* Clear the MR0 match interrupt */
tmr_putreg8(LPC214X_TMR_IR_MR0I, LPC214X_TMR_IR_OFFSET);
tmr_putreg8(LPC214X_TMR_IR_MR0I, LPC214X_TMR_IR_OFFSET);
/* Reset the VIC as well */
/* Reset the VIC as well */
#ifdef CONFIG_VECTORED_INTERRUPTS
vic_putreg(0, LPC214X_VIC_VECTADDR_OFFSET);
vic_putreg(0, LPC214X_VIC_VECTADDR_OFFSET);
#endif
return 0;
return 0;
}
/****************************************************************************

9
arch/arm/src/lpc214x/lpc214x_usbdev.c
View File

@ -537,10 +537,11 @@ static uint32_t lpc214x_getreg(uint32_t addr)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return val;
}
}

6
arch/arm/src/lpc2378/lpc23xx_i2c.c
View File

@ -311,9 +311,9 @@ static int i2c_start (struct lpc23xx_i2cdev_s *priv)
static void i2c_stop (struct lpc23xx_i2cdev_s *priv)
{
if (priv->state != 0x38)
{
putreg32(I2C_CONSET_STO | I2C_CONSET_AA, priv->base + I2C_CONSET_OFFSET);
}
{
putreg32(I2C_CONSET_STO | I2C_CONSET_AA, priv->base + I2C_CONSET_OFFSET);
}
sem_post (&priv->wait);
}

2
arch/arm/src/lpc2378/lpc23xx_timerisr.c
View File

@ -78,7 +78,7 @@
#define T0_PCLKSEL_MASK (0x0000000C)
#define T0_TICKS_COUNT ((CCLK / T0_PCLK_DIV ) / TICK_PER_SEC)
#define T0_TICKS_COUNT ((CCLK / T0_PCLK_DIV) / TICK_PER_SEC)
/****************************************************************************
* Private Types

7
arch/arm/src/lpc31xx/lpc31_clkfreq.c
View File

@ -167,11 +167,10 @@ uint32_t lpc31_clkfreq(enum lpc31_clockid_e clkid,
return 0;
}
/* Finally, calculate the frequency based on m and n values */
/* Finally, calculate the frequency based on m and n values */
freq = (freq * n) / m ;
}
freq = (freq * n) / m ;
}
return freq;
}

6
arch/arm/src/lpc31xx/lpc31_clkinit.c
View File

@ -138,8 +138,8 @@ static void lpc31_domaininit(struct lpc31_domainconfig_s* dmn)
regaddr = LPC31_CGU_ESR(esrndx);
putreg32((fdndx << CGU_ESR_ESRSEL_SHIFT) | CGU_ESR_ESREN, regaddr);
}
}
}
}
}
/* Enable the fractional divider */
@ -158,7 +158,7 @@ static void lpc31_domaininit(struct lpc31_domainconfig_s* dmn)
putreg32(CGU_BCR_FDRUN, regaddr);
}
/* Select input base clock for domain*/
/* Select input base clock for domain */
lpc31_selectfreqin(dmn->dmnid, dmn->finsel);
}

28
arch/arm/src/lpc31xx/lpc31_fdcndx.c
View File

@ -106,22 +106,22 @@ int lpc31_fdcndx(enum lpc31_clockid_e clkid, enum lpc31_domainid_e dmnid)
esrndx = lpc31_esrndx(clkid);
if (esrndx != ESRNDX_INVALID)
{
/* Read the clock's ESR to get the fractional divider */
uint32_t regval = getreg32(LPC31_CGU_ESR(esrndx));
/* Check if any fractional divider is enabled for this clock. */
if ((regval & CGU_ESR_ESREN) != 0)
{
/* Yes.. The FDC index is an offset from this fractional
* divider base for this domain.
*/
/* Read the clock's ESR to get the fractional divider */
fdcndx = CGU_ESRSEL(regval) + (int)g_fdcbase[dmnid];
uint32_t regval = getreg32(LPC31_CGU_ESR(esrndx));
/* Check if any fractional divider is enabled for this clock. */
if ((regval & CGU_ESR_ESREN) != 0)
{
/* Yes.. The FDC index is an offset from this fractional
* divider base for this domain.
*/
fdcndx = CGU_ESRSEL(regval) + (int)g_fdcbase[dmnid];
}
}
}
return fdcndx;
}

2
arch/arm/src/lpc31xx/lpc31_irq.c
View File

@ -102,7 +102,7 @@ void up_irqinitialize(void)
putreg32(0, LPC31_INTC_PRIORITYMASK0); /* Proc interrupt request 0: IRQ */
putreg32(0, LPC31_INTC_PRIORITYMASK1); /* Proc interrupt request 1: FIQ */
/* Disable all interrupts. Start from index 1 since 0 is unused.*/
/* Disable all interrupts. Start from index 1 since 0 is unused. */
for (irq = 0; irq < NR_IRQS; irq++)
{

65
arch/arm/src/lpc31xx/lpc31_resetclks.c
View File

@ -103,42 +103,43 @@ void lpc31_resetclks(void)
/* Disable all clocks except those that are necessary */
for (i = CLKID_FIRST; i <= CLKID_LAST; i++)
{
/* Check if this clock has an ESR register */
esrndx = lpc31_esrndx((enum lpc31_clockid_e)i);
if (esrndx != ESRNDX_INVALID)
{
/* Yes.. Clear the clocks ESR to deselect fractional divider */
/* Check if this clock has an ESR register */
putreg32(0, LPC31_CGU_ESR(esrndx));
esrndx = lpc31_esrndx((enum lpc31_clockid_e)i);
if (esrndx != ESRNDX_INVALID)
{
/* Yes.. Clear the clocks ESR to deselect fractional divider */
putreg32(0, LPC31_CGU_ESR(esrndx));
}
/* Enable external enabling for all possible clocks to conserve power */
lpc31_enableexten((enum lpc31_clockid_e)i);
/* Set enable-out's for only the following clocks */
regaddr = LPC31_CGU_PCR(i);
regval = getreg32(regaddr);
if (i == (int)CLKID_ARM926BUSIFCLK || i == (int)CLKID_MPMCCFGCLK)
{
regval |= CGU_PCR_ENOUTEN;
}
else
{
regval &= ~CGU_PCR_ENOUTEN;
}
putreg32(regval, regaddr);
/* Set/clear the RUN bit in the PCR regiser of all clocks, depending
* upon if the clock is needed by the board logic or not
*/
(void)lpc31_defclk((enum lpc31_clockid_e)i);
}
/* Enable external enabling for all possible clocks to conserve power */
lpc31_enableexten((enum lpc31_clockid_e)i);
/* Set enable-out's for only the following clocks */
regaddr = LPC31_CGU_PCR(i);
regval = getreg32(regaddr);
if (i == (int)CLKID_ARM926BUSIFCLK || i == (int)CLKID_MPMCCFGCLK)
{
regval |= CGU_PCR_ENOUTEN;
}
else
{
regval &= ~CGU_PCR_ENOUTEN;
}
putreg32(regval, regaddr);
/* Set/clear the RUN bit in the PCR regiser of all clocks, depending
* upon if the clock is needed by the board logic or not
*/
(void)lpc31_defclk((enum lpc31_clockid_e)i);
}
/* Disable all fractional dividers */
for (i = 0; i < CGU_NFRACDIV; i++)

15
arch/arm/src/lpc31xx/lpc31_spi.c
View File

@ -504,8 +504,7 @@ static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sel
return;
}
/*
* Since we don't use sequential multi-slave mode, but rather
/* Since we don't use sequential multi-slave mode, but rather
* perform the transfer piecemeal by consecutive calls to
* SPI_SEND, then we must manually assert the chip select
* across the whole transfer
@ -555,7 +554,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
uint32_t spi_clk, div, div1, div2;
if (priv->frequency != frequency)
{
{
/* The SPI clock is derived from the (main system oscillator / 2),
* so compute the best divider from that clock */
@ -580,8 +579,8 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
priv->slv1 = (priv->slv1 & ~(SPI_SLV_1_CLKDIV2_MASK | SPI_SLV_1_CLKDIV1_MASK)) | (div2 << SPI_SLV_1_CLKDIV2_SHIFT) | (div1 << SPI_SLV_1_CLKDIV1_SHIFT);
priv->frequency = frequency;
priv->actual = frequency; // FIXME
}
priv->actual = frequency; /* FIXME */
}
return priv->actual;
}
@ -689,10 +688,10 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
/* FIXME: is there anyway to determine this
* it should probably be board dependant anyway */
/* FIXME: is there anyway to determine this
* it should probably be board dependant anyway */
return SPI_STATUS_PRESENT;
return SPI_STATUS_PRESENT;
}
/************************************************************************************

14
arch/arm/src/lpc31xx/lpc31_timerisr.c
View File

@ -125,13 +125,13 @@ void up_timer_initialize(void)
regval = getreg32(LPC31_TIMER0_CTRL);
if (freq > 1000000)
{
/* Use the divide by 16 pre-divider */
{
/* Use the divide by 16 pre-divider */
regval &= ~TIMER_CTRL_PRESCALE_MASK;
regval |= TIMER_CTRL_PRESCALE_DIV16;
freq >>= 4;
}
regval &= ~TIMER_CTRL_PRESCALE_MASK;
regval |= TIMER_CTRL_PRESCALE_DIV16;
freq >>= 4;
}
load =((freq * (uint64_t)10000) / 1000000);
putreg32((uint32_t)load, LPC31_TIMER0_LOAD);
@ -145,7 +145,7 @@ void up_timer_initialize(void)
(void)irq_attach(LPC31_IRQ_TMR0, (xcpt_t)up_timerisr);
/* Clear any latched timer interrupt (Writing any value to the CLEAR register
/* Clear any latched timer interrupt (Writing any value to the CLEAR register
* clears the latched interrupt generated by the counter timer)
*/

61
arch/arm/src/lpc31xx/lpc31_usbdev.c
View File

@ -167,7 +167,10 @@
/* Hardware interface **********************************************************/
/* This represents a Endpoint Transfer Descriptor - note these must be 32 byte aligned */
/* This represents a Endpoint Transfer Descriptor - note these must be 32 byte
* aligned
*/
struct lpc31_dtd_s
{
volatile uint32_t nextdesc; /* Address of the next DMA descripto in RAM */
@ -180,7 +183,8 @@ struct lpc31_dtd_s
uint32_t xfer_len; /* Software only - transfer len that was queued */
};
/* DTD nextdesc field*/
/* DTD nextdesc field */
#define DTD_NEXTDESC_INVALID (1 << 0) /* Bit 0 : Next Descriptor Invalid */
/* DTD config field */
@ -495,10 +499,11 @@ static uint32_t lpc31_getreg(uint32_t addr)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return val;
}
}
@ -718,26 +723,34 @@ static inline void lpc31_ep0xfer(uint8_t epphy, uint8_t *buf, uint32_t nbytes)
* Read a Setup packet from the DTD.
*
****************************************************************************/
static void lpc31_readsetup(uint8_t epphy, struct usb_ctrlreq_s *ctrl)
{
struct lpc31_dqh_s *dqh = &g_qh[epphy];
int i;
struct lpc31_dqh_s *dqh = &g_qh[epphy];
int i;
do {
/* Set the trip wire */
lpc31_setbits(USBDEV_USBCMD_SUTW, LPC31_USBDEV_USBCMD);
do
{
/* Set the trip wire */
/* copy the request... */
for (i = 0; i < 8; i++)
((uint8_t *) ctrl)[i] = ((uint8_t *) dqh->setup)[i];
lpc31_setbits(USBDEV_USBCMD_SUTW, LPC31_USBDEV_USBCMD);
} while (!(lpc31_getreg(LPC31_USBDEV_USBCMD) & USBDEV_USBCMD_SUTW));
/* copy the request... */
/* Clear the trip wire */
lpc31_clrbits(USBDEV_USBCMD_SUTW, LPC31_USBDEV_USBCMD);
for (i = 0; i < 8; i++)
{
((uint8_t *) ctrl)[i] = ((uint8_t *) dqh->setup)[i];
}
}
while (!(lpc31_getreg(LPC31_USBDEV_USBCMD) & USBDEV_USBCMD_SUTW));
/* Clear the Setup Interrupt */
lpc31_putreg (LPC31_ENDPTMASK(LPC31_EP0_OUT), LPC31_USBDEV_ENDPTSETUPSTAT);
/* Clear the trip wire */
lpc31_clrbits(USBDEV_USBCMD_SUTW, LPC31_USBDEV_USBCMD);
/* Clear the Setup Interrupt */
lpc31_putreg (LPC31_ENDPTMASK(LPC31_EP0_OUT), LPC31_USBDEV_ENDPTSETUPSTAT);
}
/****************************************************************************
@ -909,12 +922,16 @@ static void lpc31_reqcomplete(struct lpc31_ep_s *privep,
static void lpc31_cancelrequests(struct lpc31_ep_s *privep, int16_t status)
{
if (!lpc31_rqempty(privep))
{
lpc31_flushep(privep);
}
while (!lpc31_rqempty(privep))
{
// FIXME: the entry at the head should be sync'd with the DTD
// FIXME: only report the error status if the transfer hasn't completed
/* FIXME: the entry at the head should be sync'd with the DTD
* FIXME: only report the error status if the transfer hasn't completed
*/
usbtrace(TRACE_COMPLETE(privep->epphy),
(lpc31_rqpeek(privep))->req.xfrd);
lpc31_reqcomplete(privep, lpc31_rqdequeue(privep), status);
@ -2193,7 +2210,7 @@ static int lpc31_epstall(FAR struct usbdev_ep_s *ep, bool resume)
****************************************************************************/
static FAR struct usbdev_ep_s *lpc31_allocep(FAR struct usbdev_s *dev, uint8_t eplog,
bool in, uint8_t eptype)
bool in, uint8_t eptype)
{
FAR struct lpc31_usbdev_s *priv = (FAR struct lpc31_usbdev_s *)dev;
uint32_t epset = LPC31_EPALLSET & ~LPC31_EPCTRLSET;

9
arch/arm/src/lpc43xx/lpc43_ethernet.c
View File

@ -700,10 +700,11 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return val;
}
}

23
arch/arm/src/lpc43xx/lpc43_i2c.c
View File

@ -373,7 +373,7 @@ void startStopNextMessage(struct lpc43_i2cdev_s *priv)
{
priv->nmsg--;
if(priv->nmsg > 0)
if (priv->nmsg > 0)
{
priv->msgs++;
putreg32(I2C_CONSET_STA,priv->base+LPC43_I2C_CONSET_OFFSET);
@ -442,22 +442,28 @@ static int i2c_interrupt(int irq, FAR void *context)
case 0x28: /* Data byte in DAT has been transmitted; ACK has been received. */
priv->wrcnt++;
if (priv->wrcnt < msg->length) {
if (priv->wrcnt < msg->length)
{
putreg32(msg->buffer[priv->wrcnt],priv->base+LPC43_I2C_DAT_OFFSET); /* Put next byte */
} else {
}
else
{
startStopNextMessage(priv);
}
}
break;
/* Read cases */
case 0x40: /* SLA+R has been transmitted; ACK has been received */
priv->rdcnt = 0;
if (msg->length > 1) {
if (msg->length > 1)
{
putreg32(I2C_CONSET_AA, priv->base + LPC43_I2C_CONSET_OFFSET); /* Set ACK next read */
} else {
}
else
{
putreg32(I2C_CONCLR_AAC,priv->base + LPC43_I2C_CONCLR_OFFSET); /* Do not ACK because only one byte */
}
}
break;
case 0x50: /* Data byte has been received; ACK has been returned. */
@ -567,12 +573,11 @@ struct i2c_dev_s *up_i2cinitialize(int port)
lpc43_pin_config(PINCONF_I2C1_SDA);
i2c_setfrequency(priv, I2C1_DEFAULT_FREQUENCY);
}
else
#endif
{
return NULL;
return NULL;
}
irqrestore(flags);

4
arch/arm/src/lpc43xx/lpc43_irq.c
View File

@ -264,8 +264,8 @@ static int lpc43_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
else
{
*regaddr = NVIC_SYSHCON;
if (irq == LPC43_IRQ_MEMFAULT)
*regaddr = NVIC_SYSHCON;
if (irq == LPC43_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}

6
arch/arm/src/lpc43xx/lpc43_pinconfig.c
View File

@ -103,9 +103,9 @@ int lpc43_pin_config(uint32_t pinconf)
/* Enable/disable input buffering */
if (PINCONF_INBUFFER_ENABLED(pinconf))
{
regval |= SCU_PIN_EZI; /* Set bit to enable */
}
{
regval |= SCU_PIN_EZI; /* Set bit to enable */
}
/* Enable/disable glitch filtering */

2
arch/arm/src/lpc43xx/lpc43_rit.c
View File

@ -195,7 +195,7 @@ void up_timer_initialize(void)
* complicated. When I have a better idea, I'll change this.
*/
while(!((mask_test >> mask_bits) & ticks_per_int)) mask_bits++;
while (!((mask_test >> mask_bits) & ticks_per_int)) mask_bits++;
lldbg("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n",
mask_bits, (0xFFFFFFFF<<(32 - mask_bits)), ticks_per_int);

20
arch/arm/src/lpc43xx/lpc43_serial.c
View File

@ -480,7 +480,7 @@ static uart_dev_t g_uart3port =
# undef TTYS3_DEV /* No ttyS3 */
# endif
# endif
#endif /*HAVE_CONSOLE*/
#endif /* HAVE_CONSOLE */
/****************************************************************************
* Inline Functions
@ -984,15 +984,15 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv,
}
else
{
tmp = ((priv->baud << 4) * mode->delay_rts_after_send) / 1000;
if (tmp > 255)
{
regval = 255;
}
else
{
regval = (uint32_t)tmp;
}
tmp = ((priv->baud << 4) * mode->delay_rts_after_send) / 1000;
if (tmp > 255)
{
regval = 255;
}
else
{
regval = (uint32_t)tmp;
}
}

8
arch/arm/src/lpc43xx/lpc43_spi.c
View File

@ -463,12 +463,12 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
* data transfer.
*/
while ((getreg32(LPC43_SPI_SR) & SPI_SR_SPIF) == 0);
while ((getreg32(LPC43_SPI_SR) & SPI_SR_SPIF) == 0);
/* Read the SPI Status Register again to clear the status bit */
/* Read the SPI Status Register again to clear the status bit */
(void)getreg32(LPC43_SPI_SR);
nwords--;
(void)getreg32(LPC43_SPI_SR);
nwords--;
}
}

8
arch/arm/src/lpc43xx/lpc43_spifi.c
View File

@ -1182,10 +1182,10 @@ FAR struct mtd_dev_s *lpc43_spifi_initialize(void)
/* Initialize the SPIFI ROM driver */
ret = lpc43_rominit(priv);
if (ret != OK)
{
return NULL;
}
if (ret != OK)
{
return NULL;
}
/* Check if we need to emulator a 512 byte sector */

5
arch/arm/src/lpc43xx/lpc43_start.c
View File

@ -33,8 +33,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/*
* Power-Up Reset Overview
/* Power-Up Reset Overview
* -----------------------
*
* The ARM core starts executing code on reset with the program counter set
@ -81,7 +80,7 @@
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
/****************************************************************************
* Name: showprogress
*
* Description:

18
arch/arm/src/lpc43xx/lpc43_usb0dev.c
View File

@ -514,10 +514,11 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return val;
}
}
@ -956,8 +957,10 @@ static void lpc43_cancelrequests(struct lpc43_ep_s *privep, int16_t status)
while (!lpc43_rqempty(privep))
{
// FIXME: the entry at the head should be sync'd with the DTD
// FIXME: only report the error status if the transfer hasn't completed
/* FIXME: the entry at the head should be sync'd with the DTD
* FIXME: only report the error status if the transfer hasn't completed
*/
usbtrace(TRACE_COMPLETE(privep->epphy),
(lpc43_rqpeek(privep))->req.xfrd);
lpc43_reqcomplete(privep, lpc43_rqdequeue(privep), status);
@ -2646,7 +2649,6 @@ void up_usbinitialize(void)
}
}
/* Clock */
regval = getreg32(LPC43_BASE_USB0_CLK);
@ -2660,7 +2662,7 @@ void up_usbinitialize(void)
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_M4_USB0_CFG);
/* Enable PLL0 clock*/
/* Enable PLL0 clock */
lpc43_pll0usbconfig();
lpc43_pll0usbenable();

11
arch/arm/src/moxart/moxart_16550.c
View File

@ -83,9 +83,11 @@ void uart_decodeirq(int irq, FAR void *context)
i = 0;
do
{
if (!(status & 0x1)) {
irq_dispatch(VIRQ_START + i, context);
}
if (!(status & 0x1))
{
irq_dispatch(VIRQ_START + i, context);
}
status >>= 1;
}
while (++i <= 4);
@ -102,8 +104,7 @@ int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
unsigned int opmode;
int bitm_off;
/*
* TODO: calculate bit offset from UART_BASE address.
/* TODO: calculate bit offset from UART_BASE address.
* E.g.:
* 0x9820_0000 -> 0
* 0x9820_0020 -> 1

3
arch/arm/src/moxart/moxart_irq.c
View File

@ -101,7 +101,8 @@ void up_irqinitialize(void)
(*(volatile uint32_t *)0x98100008) &= ~0x9;
while (!((*(volatile uint32_t *)0x98100008) & 0x2)) { ; }
while (!((*(volatile uint32_t *)0x98100008) & 0x2))
;
(*(volatile uint32_t *)0x98100008) |= 0x4;

2
arch/arm/src/moxart/moxart_systemreset.c
View File

@ -69,7 +69,7 @@ void up_systemreset(void)
{
putreg32(0, FTWDT010_CR);
putreg32(0, FTWDT010_LOAD);
putreg32(0x5ab9, FTWDT010_RESTART); // Magic
putreg32(0x5ab9, FTWDT010_RESTART); /* Magic */
putreg32(0x11, FTWDT010_CR);
putreg32(0x13, FTWDT010_CR);

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