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risc-v: Fix style issue in SoC's Make.defs

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-02-11 13:07:14 +08:00 committed by Xiang Xiao
parent 02ba5f4103
commit 3fe9c9523c
5 changed files with 25 additions and 25 deletions
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12
arch/risc-v/src/bl602/Make.defs
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@ -44,11 +44,11 @@ CMN_CSRCS += riscv_checkstack.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += riscv_fpu.S
CMN_ASRCS += riscv_fpu.S
endif
ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
CMN_CSRCS += riscv_vfork.c
CMN_CSRCS += riscv_vfork.c
endif
# Specify our C code within this directory to be included
@ -67,16 +67,16 @@ CHIP_CSRCS += bl602_spi.c
endif
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += bl602_tim_lowerhalf.c
CHIP_CSRCS += bl602_tim_lowerhalf.c
endif
ifeq ($(CONFIG_ONESHOT),y)
CHIP_CSRCS += bl602_oneshot_lowerhalf.c
CHIP_CSRCS += bl602_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_WATCHDOG),y)
CHIP_CSRCS += bl602_wdt_lowerhalf.c
CHIP_CSRCS += bl602_wdt_lowerhalf.c
endif
ifeq ($(CONFIG_PWM),y)
CHIP_CSRCS += bl602_pwm_lowerhalf.c
CHIP_CSRCS += bl602_pwm_lowerhalf.c
endif
ifeq ($(CONFIG_BL602_SPIFLASH),y)
CHIP_CSRCS += bl602_flash.c bl602_spiflash.c

4
arch/risc-v/src/c906/Make.defs
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@ -44,11 +44,11 @@ CMN_CSRCS += riscv_checkstack.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += riscv_fpu.S
CMN_ASRCS += riscv_fpu.S
endif
ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
CMN_CSRCS += riscv_vfork.c
CMN_CSRCS += riscv_vfork.c
endif
# Specify our C code within this directory to be included

26
arch/risc-v/src/esp32c3/Make.defs
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@ -23,19 +23,19 @@ include chip/Bootloader.mk
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = esp32c3_head.S
HEAD_ASRC = esp32c3_head.S
CHIP_ASRCS = esp32c3_vectors.S esp32c3_interrupt.S
CHIP_ASRCS = esp32c3_vectors.S esp32c3_interrupt.S
# Specify C code within the common directory to be included
CMN_CSRCS += riscv_initialize.c riscv_swint.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c riscv_exception.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c
CMN_CSRCS += riscv_initialize.c riscv_swint.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c riscv_exception.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c riscv_copyfullstate.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += riscv_backtrace.c
@ -184,10 +184,10 @@ CHIP_CSRCS += esp32c3_brownout.c
endif
ifeq ($(CONFIG_ESP32C3_WIRELESS),y)
WIRELESS_DRV_UNPACK = esp-wireless-drivers-3rdparty
WIRELESS_DRV_ID = 055f1ef
WIRELESS_DRV_ZIP = $(WIRELESS_DRV_ID).zip
WIRELESS_DRV_URL = https://github.com/espressif/esp-wireless-drivers-3rdparty/archive
WIRELESS_DRV_UNPACK = esp-wireless-drivers-3rdparty
WIRELESS_DRV_ID = 055f1ef
WIRELESS_DRV_ZIP = $(WIRELESS_DRV_ID).zip
WIRELESS_DRV_URL = https://github.com/espressif/esp-wireless-drivers-3rdparty/archive
$(WIRELESS_DRV_ZIP):
$(Q) echo "Downloading: ESP Wireless Drivers"

2
arch/risc-v/src/litex/Make.defs
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@ -44,7 +44,7 @@ CMN_CSRCS += riscv_checkstack.c
endif
ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
CMN_CSRCS += riscv_vfork.c
CMN_CSRCS += riscv_vfork.c
endif
# Specify our C code within this directory to be included

6
arch/risc-v/src/mpfs/Make.defs
View File

@ -61,9 +61,9 @@ CHIP_CSRCS += mpfs_dma.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += riscv_task_start.c
CMN_CSRCS += riscv_pthread_start.c
CMN_CSRCS += riscv_signal_dispatch.c
CMN_CSRCS += riscv_task_start.c
CMN_CSRCS += riscv_pthread_start.c
CMN_CSRCS += riscv_signal_dispatch.c
CMN_UASRCS += riscv_signal_handler.S