stm32h7: support SDRAM via FMC peripherial (#459)
* stm32h7: Add support for SDRAM connected to FMC
* stm32h7: nxstyle fixes in stm32_fmc.h and stm32h7x3xx_rcc.{c,h}
This commit is contained in:
Andrey Zabolotnyi
GitHub
parent
2991836ee8
commit
3ff956dc00
@ -58,6 +58,12 @@
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# define getreg32(a) (*(volatile uint32_t *)(a))
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# define putreg32(v,a) (*(volatile uint32_t *)(a) = (v))
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/* Non-atomic, but more effective modification of registers */
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# define modreg8(v,m,a) putreg8((getreg8(a) & ~(m)) | ((v) & (m)), a)
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# define modreg16(v,m,a) putreg16((getreg16(a) & ~(m)) | ((v) & (m)), a)
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# define modreg32(v,m,a) putreg32((getreg32(a) & ~(m)) | ((v) & (m)), a)
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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@ -289,9 +289,13 @@ config STM32H7_ETHMAC
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select ARCH_HAVE_PHY
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config STM32H7_FMC
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bool "FMC"
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default n
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depends on STM32H7_HAVE_FMC
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bool "FMC"
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default n
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depends on STM32H7_HAVE_FMC
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---help---
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Enable Flexible Memory Controller.
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To correctly configure FMC for your hardware, you will have to define
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a number of macros in your board.h file. See stm32_fmc.c for directions.
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config STM32H7_OTGFS
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bool "OTG FS"
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@ -1187,14 +1191,6 @@ endif # STM32H7_RTC_LSECLOCK
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endmenu # RTC Configuration
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config STM32H7_EXTERNAL_RAM
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bool "External RAM on FMC"
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default n
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depends on STM32H7_FMC
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select ARCH_HAVE_HEAP2
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---help---
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In addition to internal SDRAM, external RAM may be available through the FMC.
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menu "QuadSPI Configuration"
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depends on STM32H7_QUADSPI
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@ -1,4 +1,4 @@
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/************************************************************************************
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/*****************************************************************************************************************************************************
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* arch/arm/src/stm32h7/hardware/stm32_fmc.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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@ -31,360 +31,380 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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*****************************************************************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H
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#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H
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/************************************************************************************
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/*****************************************************************************************************************************************************
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* Included Files
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************************************************************************************/
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*****************************************************************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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/*****************************************************************************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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*****************************************************************************************************************************************************/
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/* Register Offsets *****************************************************************/
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/* Register Offsets **********************************************************************************************************************************/
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#define STM32_FMC_BCR_OFFSET(n) (8*((n)-1))
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#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */
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#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */
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#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */
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#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */
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#define STM32_FMC_BCR_OFFSET(n) (8*((n)-1))
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#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */
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#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */
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#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */
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#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */
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#define STM32_FMC_BTR_OFFSET(n) (8*((n)-1)+0x0004)
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#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */
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#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */
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#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */
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#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */
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#define STM32_FMC_BTR_OFFSET(n) (8*((n)-1)+0x0004)
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#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */
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#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */
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#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */
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#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */
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#define STM32_FMC_BWTR_OFFSET(n) (8*((n)-1)+0x0104)
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#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */
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#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */
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#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */
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#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */
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#define STM32_FMC_BWTR_OFFSET(n) (8*((n)-1)+0x0104)
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#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */
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#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */
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#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */
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#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */
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#define STM32_FMC_PCR_OFFSET(n) (0x0020*((n)-1)+0x0040)
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#define STM32_FMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */
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#define STM32_FMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */
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#define STM32_FMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */
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#define STM32_FMC_PCR_OFFSET 0x0080 /* NAND Flash control register */
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#define STM32_FMC_SR_OFFSET(n) (0x0020*((n)-1)+0x0044)
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#define STM32_FMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */
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#define STM32_FMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */
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#define STM32_FMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */
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#define STM32_FMC_SR_OFFSET 0x0084 /* FIFO status and interrupt register */
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#define STM32_FMC_PMEM_OFFSET(n) (0x0020*((n)-1)+0x0048)
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#define STM32_FMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */
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#define STM32_FMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */
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#define STM32_FMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */
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#define STM32_FMC_PMEM_OFFSET 0x0088 /* Common memory space timing register */
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#define STM32_FMC_PATT_OFFSET(n) (0x0020*((n)-1)+0x004c)
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#define STM32_FMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */
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#define STM32_FMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */
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#define STM32_FMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */
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#define STM32_FMC_PATT_OFFSET 0x008c /* Attribute memory space timing register */
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#define STM32_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */
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#define STM32_FMC_ECCR_OFFSET 0x0094 /* ECC result register */
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#define STM32_FMC_ECCR_OFFSET(n) (0x0020*((n)-1)+0x003c)
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#define STM32_FMC_ECCR2_OFFSET 0x0054 /* ECC result register 2 */
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#define STM32_FMC_ECCR3_OFFSET 0x0074 /* ECC result register 3 */
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#define STM32_FMC_SDCR_OFFSET(n) (4*((n)-1)+0x0140)
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#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 1 */
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#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */
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#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 0 */
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#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */
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#define STM32_FMC_SDTR_OFFSET(n) (4*((n)-1)+0x0148)
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#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 0 */
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#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 1 */
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#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 0 */
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#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 1 */
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#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Command mode register */
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#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */
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#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */
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#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Config Memory register */
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#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */
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#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */
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/* Register Addresses ********************************************************************************************************************************/
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/* Register Addresses ***************************************************************/
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#define STM32_FMC_BCR(n) (STM32_FMC_BASE+STM32_FMC_BCR_OFFSET(n))
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#define STM32_FMC_BCR1 (STM32_FMC_BASE+STM32_FMC_BCR1_OFFSET )
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#define STM32_FMC_BCR2 (STM32_FMC_BASE+STM32_FMC_BCR2_OFFSET )
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#define STM32_FMC_BCR3 (STM32_FMC_BASE+STM32_FMC_BCR3_OFFSET )
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#define STM32_FMC_BCR4 (STM32_FMC_BASE+STM32_FMC_BCR4_OFFSET )
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#define STM32_FMC_BCR(n) (STM32_FMC_BASE+STM32_FMC_BCR_OFFSET(n))
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#define STM32_FMC_BCR1 (STM32_FMC_BASE+STM32_FMC_BCR1_OFFSET )
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#define STM32_FMC_BCR2 (STM32_FMC_BASE+STM32_FMC_BCR2_OFFSET )
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#define STM32_FMC_BCR3 (STM32_FMC_BASE+STM32_FMC_BCR3_OFFSET )
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#define STM32_FMC_BCR4 (STM32_FMC_BASE+STM32_FMC_BCR4_OFFSET )
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#define STM32_FMC_BTR(n) (STM32_FMC_BASE+STM32_FMC_BTR_OFFSET(n))
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#define STM32_FMC_BTR1 (STM32_FMC_BASE+STM32_FMC_BTR1_OFFSET )
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#define STM32_FMC_BTR2 (STM32_FMC_BASE+STM32_FMC_BTR2_OFFSET )
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#define STM32_FMC_BTR3 (STM32_FMC_BASE+STM32_FMC_BTR3_OFFSET )
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#define STM32_FMC_BTR4 (STM32_FMC_BASE+STM32_FMC_BTR4_OFFSET )
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#define STM32_FMC_BTR(n) (STM32_FMC_BASE+STM32_FMC_BTR_OFFSET(n))
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#define STM32_FMC_BTR1 (STM32_FMC_BASE+STM32_FMC_BTR1_OFFSET )
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#define STM32_FMC_BTR2 (STM32_FMC_BASE+STM32_FMC_BTR2_OFFSET )
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#define STM32_FMC_BTR3 (STM32_FMC_BASE+STM32_FMC_BTR3_OFFSET )
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#define STM32_FMC_BTR4 (STM32_FMC_BASE+STM32_FMC_BTR4_OFFSET )
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#define STM32_FMC_BWTR(n) (STM32_FMC_BASE+STM32_FMC_BWTR_OFFSET(n))
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#define STM32_FMC_BWTR1 (STM32_FMC_BASE+STM32_FMC_BWTR1_OFFSET )
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#define STM32_FMC_BWTR2 (STM32_FMC_BASE+STM32_FMC_BWTR2_OFFSET )
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#define STM32_FMC_BWTR3 (STM32_FMC_BASE+STM32_FMC_BWTR3_OFFSET )
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#define STM32_FMC_BWTR4 (STM32_FMC_BASE+STM32_FMC_BWTR4_OFFSET )
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#define STM32_FMC_BWTR(n) (STM32_FMC_BASE+STM32_FMC_BWTR_OFFSET(n))
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#define STM32_FMC_BWTR1 (STM32_FMC_BASE+STM32_FMC_BWTR1_OFFSET )
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#define STM32_FMC_BWTR2 (STM32_FMC_BASE+STM32_FMC_BWTR2_OFFSET )
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#define STM32_FMC_BWTR3 (STM32_FMC_BASE+STM32_FMC_BWTR3_OFFSET )
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#define STM32_FMC_BWTR4 (STM32_FMC_BASE+STM32_FMC_BWTR4_OFFSET )
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#define STM32_FMC_PCR (STM32_FMC_BASE+STM32_FMC_PCR_OFFSET)
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#define STM32_FMC_PCR(n) (STM32_FMC_BASE+STM32_FMC_PCR_OFFSET(n))
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#define STM32_FMC_PCR2 (STM32_FMC_BASE+STM32_FMC_PCR2_OFFSET )
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#define STM32_FMC_PCR3 (STM32_FMC_BASE+STM32_FMC_PCR3_OFFSET )
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#define STM32_FMC_PCR4 (STM32_FMC_BASE+STM32_FMC_PCR4_OFFSET )
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#define STM32_FMC_SR (STM32_FMC_BASE+STM32_FMC_SR_OFFSET)
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#define STM32_FMC_SR(n) (STM32_FMC_BASE+STM32_FMC_SR_OFFSET(n))
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#define STM32_FMC_SR2 (STM32_FMC_BASE+STM32_FMC_SR2_OFFSET )
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#define STM32_FMC_SR3 (STM32_FMC_BASE+STM32_FMC_SR3_OFFSET )
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#define STM32_FMC_SR4 (STM32_FMC_BASE+STM32_FMC_SR4_OFFSET )
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#define STM32_FMC_PMEM (STM32_FMC_BASE+STM32_FMC_PMEM_OFFSET)
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#define STM32_FMC_PMEM(n) (STM32_FMC_BASE+STM32_FMC_PMEM_OFFSET(n))
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#define STM32_FMC_PMEM2 (STM32_FMC_BASE+STM32_FMC_PMEM2_OFFSET )
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#define STM32_FMC_PMEM3 (STM32_FMC_BASE+STM32_FMC_PMEM3_OFFSET )
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#define STM32_FMC_PMEM4 (STM32_FMC_BASE+STM32_FMC_PMEM4_OFFSET )
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#define STM32_FMC_PATT (STM32_FMC_BASE+STM32_FMC_PATT_OFFSET)
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#define STM32_FMC_PATT(n) (STM32_FMC_BASE+STM32_FMC_PATT_OFFSET(n))
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#define STM32_FMC_PATT2 (STM32_FMC_BASE+STM32_FMC_PATT2_OFFSET )
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#define STM32_FMC_PATT3 (STM32_FMC_BASE+STM32_FMC_PATT3_OFFSET )
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#define STM32_FMC_PATT4 (STM32_FMC_BASE+STM32_FMC_PATT4_OFFSET )
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#define STM32_FMC_ECCR (STM32_FMC_BASE+STM32_FMC_ECCR_OFFSET)
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#define STM32_PIO4 (STM32_FMC_BASE+STM32_FMC_PIO4_OFFSET )
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#define STM32_FMC_SDCR1 (STM32_FMC_BASE+STM32_FMC_SDCR1_OFFSET)
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#define STM32_FMC_SDCR2 (STM32_FMC_BASE+STM32_FMC_SDCR2_OFFSET)
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#define STM32_FMC_ECCR(n) (STM32_FMC_BASE+STM32_FMC_ECCR_OFFSET(n))
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#define STM32_FMC_ECCR2 (STM32_FMC_BASE+STM32_FMC_ECCR2_OFFSET )
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#define STM32_FMC_ECCR3 (STM32_FMC_BASE+STM32_FMC_ECCR3_OFFSET )
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#define STM32_FMC_SDTR1 (STM32_FMC_BASE+STM32_FMC_SDTR1_OFFSET)
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#define STM32_FMC_SDTR2 (STM32_FMC_BASE+STM32_FMC_SDTR2_OFFSET)
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#define STM32_FMC_SDCR1 (STM32_FMC_BASE+STM32_FMC_SDCR1_OFFSET)
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#define STM32_FMC_SDCR2 (STM32_FMC_BASE+STM32_FMC_SDCR2_OFFSET)
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#define STM32_FMC_SDCMR (STM32_FMC_BASE+STM32_FMC_SDCMR_OFFSET)
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#define STM32_FMC_SDRTR (STM32_FMC_BASE+STM32_FMC_SDRTR_OFFSET)
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#define STM32_FMC_SDSR (STM32_FMC_BASE+STM32_FMC_SDSR_OFFSET)
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#define STM32_FMC_SDTR1 (STM32_FMC_BASE+STM32_FMC_SDTR1_OFFSET)
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#define STM32_FMC_SDTR2 (STM32_FMC_BASE+STM32_FMC_SDTR2_OFFSET)
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/* Register Bitfield Definitions *********************************************************************************************************************/
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#define STM32_FMC_SDCMR (STM32_FMC_BASE+STM32_FMC_SDCMR_OFFSET)
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#define STM32_FMC_SDRTR (STM32_FMC_BASE+STM32_FMC_SDRTR_OFFSET)
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#define STM32_FMC_SDSR (STM32_FMC_BASE+STM32_FMC_SDSR_OFFSET)
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#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */
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#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */
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#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */
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#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT)
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# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT)
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# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT)
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# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT)
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# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT)
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# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT)
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#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */
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#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT)
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# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT)
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# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT)
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# define FMC_BCR_MWID32 (2 << FMC_BCR_MWID_SHIFT)
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#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */
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#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */
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#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */
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#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */
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#define FMC_BCR_WREN (1 << 12) /* Write enable bit */
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#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
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#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
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#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
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#define FMC_BCR_CPSIZE_SHIFT (16)
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#define FMC_BCR_CPSIZE_MASK (7 << FMC_BCR_CPSIZE_SHIFT)
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# define FMC_BCR_CPSIZE0 (0 << FMC_BCR_CPSIZE_SHIFT)
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# define FMC_BCR_CPSIZE128 (1 << FMC_BCR_CPSIZE_SHIFT)
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# define FMC_BCR_CPSIZE256 (2 << FMC_BCR_CPSIZE_SHIFT)
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# define FMC_BCR_CPSIZE1024 (3 << FMC_BCR_CPSIZE_SHIFT)
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#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
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#define FMC_BCR_CCLKEN (1 << 20) /* Continuous Clock Enable */
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#define FMC_BCR_WFDIS (1 << 21) /* Write FIFO Disable */
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#define FMC_BCR_BMAP_SHIFT (24)
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#define FMC_BCR_BMAP_MASK (3 << FMC_BCR_BMAP_SHIFT)
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# define FMC_BCR_BMAP0 (0 << FMC_BCR_BMAP_SHIFT) /* Default mapping */
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||||
# define FMC_BCR_BMAP1 (1 << FMC_BCR_BMAP_SHIFT) /* NOR/PSRAM bank and SDRAM bank 1/bank2 are swapped */
|
||||
# define FMC_BCR_BMAP2 (2 << FMC_BCR_BMAP_SHIFT) /* SDRAM Bank2 remapped on FMC bank2 and still accessible at default mapping */
|
||||
#define FMC_BCR_FMCEN (1 << 31) /* FMC controller Enable */
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
#define FMC_BCR_RSTVALUE(n) ((n == 0) ? 0x000030db : 0x000030d2) /* Reset value for BCR */
|
||||
|
||||
#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */
|
||||
#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */
|
||||
#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */
|
||||
#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT)
|
||||
# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT)
|
||||
# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT)
|
||||
# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT)
|
||||
# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT)
|
||||
# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT)
|
||||
#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */
|
||||
#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT)
|
||||
# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT)
|
||||
# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT)
|
||||
#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */
|
||||
#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */
|
||||
#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */
|
||||
#define FMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */
|
||||
#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */
|
||||
#define FMC_BCR_WREN (1 << 12) /* Write enable bit */
|
||||
#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
|
||||
#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
|
||||
#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
|
||||
#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
|
||||
#define FMC_BCR_BMAP_SHIFT (24)
|
||||
# define FMC_BCR_BMAP_0 (0 << FMC_BCR_BMAP_SHIFT)
|
||||
# define FMC_BCR_BMAP_1 (1 << FMC_BCR_BMAP_SHIFT)
|
||||
# define FMC_BCR_BMAP_2 (2 << FMC_BCR_BMAP_SHIFT)
|
||||
#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */
|
||||
#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT)
|
||||
# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
|
||||
#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT)
|
||||
# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
|
||||
#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */
|
||||
#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT)
|
||||
# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */
|
||||
#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT)
|
||||
# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT)/* (n)xHCLK n=1..16 */
|
||||
#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
|
||||
#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT)
|
||||
# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
|
||||
#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */
|
||||
#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT)
|
||||
# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT)
|
||||
/* (n)xHCLK n=2..17 */
|
||||
#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */
|
||||
#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT)
|
||||
# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT)
|
||||
# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT)
|
||||
# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT)
|
||||
# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT)
|
||||
|
||||
#define FMC_BCR_FMCEN (1 << 31) /* Write burst enable */
|
||||
#define FMC_BTR_RSTVALUE 0xffffffff
|
||||
|
||||
#define FMC_BCR_RSTVALUE 0x000003d2
|
||||
#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */
|
||||
#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT)
|
||||
# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT)/* (n)xHCLK n=1..16 */
|
||||
#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
|
||||
#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT)
|
||||
# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT)/* (n)xHCLK n=2..16 */
|
||||
#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */
|
||||
#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT)
|
||||
# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT)/* (n)xHCLK n=2..256 */
|
||||
#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
|
||||
#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT)
|
||||
# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT)/* (n)xHCLK n=2..16 */
|
||||
#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */
|
||||
#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT)
|
||||
# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT)/* (n)xHCLK n=2..17 */
|
||||
#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */
|
||||
#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
# define FMC_BWTR_ACCMODD (3 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
|
||||
#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */
|
||||
#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT)
|
||||
# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
|
||||
#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT)
|
||||
# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
|
||||
#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */
|
||||
#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT)
|
||||
# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */
|
||||
#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT)
|
||||
# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
|
||||
#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT)
|
||||
# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
|
||||
#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */
|
||||
#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT)
|
||||
# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
|
||||
#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */
|
||||
#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT)
|
||||
# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT)
|
||||
# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT)
|
||||
# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT)
|
||||
# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT)
|
||||
#define FMC_PCR_RSTVALUE (0x00000018)
|
||||
|
||||
#define FMC_BTR_RSTVALUE 0xffffffff
|
||||
#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */
|
||||
#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */
|
||||
#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */
|
||||
#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT)
|
||||
# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT)
|
||||
# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT)
|
||||
#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */
|
||||
#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */
|
||||
#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT)
|
||||
# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */
|
||||
#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK)
|
||||
# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */
|
||||
#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT)
|
||||
# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */
|
||||
# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */
|
||||
# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
|
||||
# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
|
||||
# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
|
||||
# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
|
||||
|
||||
#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */
|
||||
#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT)
|
||||
# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
|
||||
#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT)
|
||||
# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
|
||||
#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */
|
||||
#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT)
|
||||
# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
|
||||
#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT)
|
||||
# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
|
||||
#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */
|
||||
#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT)
|
||||
# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
|
||||
#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */
|
||||
#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
# define FMC_BWTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT)
|
||||
#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */
|
||||
#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */
|
||||
#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */
|
||||
#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */
|
||||
#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */
|
||||
#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */
|
||||
#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */
|
||||
|
||||
#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */
|
||||
#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */
|
||||
#define FMC_PCR_PTYP (1 << 3) /* Memory type */
|
||||
#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */
|
||||
#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT)
|
||||
# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT)
|
||||
# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT)
|
||||
#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */
|
||||
#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */
|
||||
#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT)
|
||||
# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */
|
||||
#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK)
|
||||
# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */
|
||||
#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT)
|
||||
# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */
|
||||
# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */
|
||||
# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
|
||||
# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
|
||||
# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
|
||||
# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
|
||||
#define FMC_PMEM_RSTVALUE (0xfcfcfcfc)
|
||||
|
||||
#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */
|
||||
#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */
|
||||
#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */
|
||||
#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */
|
||||
#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */
|
||||
#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */
|
||||
#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */
|
||||
#define FMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */
|
||||
#define FMC_PMEM_MEMSET_MASK (255 << FMC_PMEM_MEMSET_SHIFT)
|
||||
# define FMC_PMEM_MEMSET(n) ((n-1) << FMC_PMEM_MEMSET_SHIFT)/* (n)xHCLK n=1..256 */
|
||||
#define FMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */
|
||||
#define FMC_PMEM_MEMWAIT_MASK (255 << FMC_PMEM_MEMWAIT_SHIFT)
|
||||
# define FMC_PMEM_MEMWAIT(n) ((n-1)<<FMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */
|
||||
#define FMC_PMEM_MEMHOLD_MASK (255 << FMC_PMEM_MEMHOLD_SHIFT)
|
||||
# define FMC_PMEM_MEMHOLD(n) ((n) << FMC_PMEM_MEMHOLD_SHIFT)/* (n)xHCLK n=1..255 */
|
||||
#define FMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */
|
||||
#define FMC_PMEM_MEMHIZ_MASK (255 << FMC_PMEM_MEMHIZ_SHIFT)
|
||||
# define FMC_PMEM_MEMHIZ(n) ((n) << FMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
|
||||
|
||||
#define FMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */
|
||||
#define FMC_PMEM_MEMSET_MASK (255 << FMC_PMEM_MEMSET_SHIFT)
|
||||
# define FMC_PMEM_MEMSET(n) ((n-1) << FMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */
|
||||
#define FMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */
|
||||
#define FMC_PMEM_MEMWAIT_MASK (255 << FMC_PMEM_MEMWAIT_SHIFT)
|
||||
# define FMC_PMEM_MEMWAIT(n) ((n-1) << FMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */
|
||||
#define FMC_PMEM_MEMHOLD_MASK (255 << FMC_PMEM_MEMHOLD_SHIFT)
|
||||
# define FMC_PMEM_MEMHOLD(n) ((n) << FMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */
|
||||
#define FMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */
|
||||
#define FMC_PMEM_MEMHIZ_MASK (255 << FMC_PMEM_MEMHIZ_SHIFT)
|
||||
# define FMC_PMEM_MEMHIZ(n) ((n) << FMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
|
||||
#define FMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */
|
||||
#define FMC_PATT_ATTSET_MASK (255 << FMC_PATT_ATTSET_SHIFT)
|
||||
# define FMC_PATT_ATTSET(n) ((n-1) << FMC_PATT_ATTSET_SHIFT)/* (n)xHCLK n=1..256 */
|
||||
#define FMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */
|
||||
#define FMC_PATT_ATTWAIT_MASK (255 << FMC_PATT_ATTWAIT_SHIFT)
|
||||
# define FMC_PATT_ATTWAIT(n) ((n-1)<<FMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */
|
||||
#define FMC_PATT_ATTHOLD_MASK (255 << FMC_PATT_ATTHOLD_SHIFT)
|
||||
# define FMC_PATT_ATTHOLD(n) ((n) << FMC_PATT_ATTHOLD_SHIFT)/* (n)xHCLK n=1..255 */
|
||||
#define FMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */
|
||||
#define FMC_PATT_ATTHIZ_MASK (255 << FMC_PATT_ATTHIZ_SHIFT)
|
||||
# define FMC_PATT_ATTHIZ(n) ((n) << FMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
|
||||
|
||||
#define FMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */
|
||||
#define FMC_PATT_ATTSET_MASK (255 << FMC_PATT_ATTSET_SHIFT)
|
||||
# define FMC_PATT_ATTSET(n) ((n-1) << FMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */
|
||||
#define FMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */
|
||||
#define FMC_PATT_ATTWAIT_MASK (255 << FMC_PATT_ATTWAIT_SHIFT)
|
||||
# define FMC_PATT_ATTWAIT(n) ((n-1) << FMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */
|
||||
#define FMC_PATT_ATTHOLD_MASK (255 << FMC_PATT_ATTHOLD_SHIFT)
|
||||
# define FMC_PATT_ATTHOLD(n) ((n) << FMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */
|
||||
#define FMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */
|
||||
#define FMC_PATT_ATTHIZ_MASK (255 << FMC_PATT_ATTHIZ_SHIFT)
|
||||
# define FMC_PATT_ATTHIZ(n) ((n) << FMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
|
||||
# define FMC_SDCR_COLBITS_SHIFT (0)
|
||||
# define FMC_SDCR_COLBITS_MASK (3 << FMC_SDCR_COLBITS_SHIFT)
|
||||
# define FMC_SDCR_COLBITS_8 0x00000000
|
||||
# define FMC_SDCR_COLBITS_9 0x00000001
|
||||
# define FMC_SDCR_COLBITS_10 0x00000002
|
||||
# define FMC_SDCR_COLBITS_11 0x00000003
|
||||
|
||||
#define FMC_PIO4_IOSET_SHIFT (0) /* IOribute memory setup time */
|
||||
#define FMC_PIO4_IOSET_MASK (255 << FMC_PIO4_IOSET_SHIFT)
|
||||
# define FMC_PIO4_IOSET(n) ((n-1) << FMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */
|
||||
#define FMC_PIO4_IOWAIT_SHIFT (8) /* IOribute memory wait time */
|
||||
#define FMC_PIO4_IOWAIT_MASK (255 << FMC_PIO4_IOWAIT_SHIFT)
|
||||
# define FMC_PIO4_IOWAIT(n) ((n-1) << FMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_PIO4_IOHOLD_SHIFT (16) /* IOribute memory hold time */
|
||||
#define FMC_PIO4_IOHOLD_MASK (255 << FMC_PIO4_IOHOLD_SHIFT)
|
||||
# define FMC_PIO4_IOHOLD(n) ((n) << FMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */
|
||||
#define FMC_PIO4_IOHIZ_SHIFT (24) /* IOribute memory databus HiZ time */
|
||||
#define FMC_PIO4_IOHIZ_MASK (255 << FMC_PIO4_IOHIZ_SHIFT)
|
||||
# define FMC_PIO4_IOHIZ(n) ((n) << FMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */
|
||||
# define FMC_SDCR_ROWBITS_SHIFT (2)
|
||||
# define FMC_SDCR_ROWBITS_MASK (3 << FMC_SDCR_ROWBITS_SHIFT)
|
||||
# define FMC_SDCR_ROWBITS_11 0x00000000
|
||||
# define FMC_SDCR_ROWBITS_12 0x00000004
|
||||
# define FMC_SDCR_ROWBITS_13 0x00000008
|
||||
|
||||
#define FMC_SDCMR_RESERVED (0x3ff << 22) /* reserved bits */
|
||||
#define FMC_SDCMR_CMD_LOAD_MODE (4 << 0)
|
||||
# define FMC_SDCR_WIDTH_SHIFT (4)
|
||||
# define FMC_SDCR_WIDTH_MASK (3 << FMC_SDCR_WIDTH_SHIFT)
|
||||
# define FMC_SDCR_WIDTH_8 0x00000000
|
||||
# define FMC_SDCR_WIDTH_16 0x00000010
|
||||
# define FMC_SDCR_WIDTH_32 0x00000020
|
||||
|
||||
# define FMC_SDRAM_CR_COLBITS_8 0x00000000
|
||||
# define FMC_SDRAM_CR_COLBITS_9 0x00000001
|
||||
# define FMC_SDRAM_CR_COLBITS_10 0x00000002
|
||||
# define FMC_SDRAM_CR_COLBITS_11 0x00000003
|
||||
# define FMC_SDCR_BANKS_SHIFT (6)
|
||||
# define FMC_SDCR_BANKS_MASK (1 << FMC_SDCR_BANKS_SHIFT)
|
||||
# define FMC_SDCR_BANKS_2 0x00000000
|
||||
# define FMC_SDCR_BANKS_4 0x00000040
|
||||
|
||||
# define FMC_SDRAM_CR_ROWBITS_11 0x00000000
|
||||
# define FMC_SDRAM_CR_ROWBITS_12 0x00000004
|
||||
# define FMC_SDRAM_CR_ROWBITS_13 0x00000008
|
||||
# define FMC_SDCR_CASLAT_SHIFT (7)
|
||||
# define FMC_SDCR_CASLAT_MASK (3 << FMC_SDCR_CASLAT_SHIFT)
|
||||
# define FMC_SDCR_CASLAT_1 0x00000080
|
||||
# define FMC_SDCR_CASLAT_2 0x00000100
|
||||
# define FMC_SDCR_CASLAT_3 0x00000180
|
||||
|
||||
# define FMC_SDRAM_CR_WIDTH_8 0x00000000
|
||||
# define FMC_SDRAM_CR_WIDTH_16 0x00000010
|
||||
# define FMC_SDRAM_CR_WIDTH_32 0x00000020
|
||||
# define FMC_SDCR_WP 0x00000200
|
||||
|
||||
# define FMC_SDRAM_CR_BANKS_2 0x00000000
|
||||
# define FMC_SDRAM_CR_BANKS_4 0x00000040
|
||||
# define FMC_SDCR_SDCLK_SHIFT (10)
|
||||
# define FMC_SDCR_SDCLK_MASK (3 << FMC_SDCR_SDCLK_SHIFT)
|
||||
# define FMC_SDCR_SDCLK_DISABLE 0x00000000
|
||||
# define FMC_SDCR_SDCLK_2X 0x00000800
|
||||
# define FMC_SDCR_SDCLK_3X 0x00000C00
|
||||
|
||||
# define FMC_SDRAM_CR_CASLAT_1 0x00000080
|
||||
# define FMC_SDRAM_CR_CASLAT_2 0x00000100
|
||||
# define FMC_SDRAM_CR_CASLAT_3 0x00000180
|
||||
# define FMC_SDCR_BURST_READ 0x00001000
|
||||
|
||||
# define FMC_SDRAM_CR_WRITE_PROTECT 0x00000200
|
||||
# define FMC_SDCR_RPIPE_SHIFT (13)
|
||||
# define FMC_SDCR_RPIPE_MASK (3 << FMC_SDCR_RPIPE_SHIFT)
|
||||
# define FMC_SDCR_RPIPE_0 0x00000000
|
||||
# define FMC_SDCR_RPIPE_1 0x00002000
|
||||
# define FMC_SDCR_RPIPE_2 0x00004000
|
||||
|
||||
# define FMC_SDRAM_CR_SDCLK_DISABLE 0x00000000
|
||||
# define FMC_SDRAM_CR_SDCLK_2X 0x00000800
|
||||
# define FMC_SDRAM_CR_SDCLK_3X 0x00000C00
|
||||
#define FMC_SDCR_RESERVED (0x1FFFF << 15) /* reserved bits */
|
||||
|
||||
# define FMC_SDRAM_CR_BURST_READ 0x00001000
|
||||
#define FMC_SDTR_TMRD_SHIFT (0)
|
||||
#define FMC_SDTR_TMRD_MASK FMC_SDTR_TMRD(16)
|
||||
#define FMC_SDTR_TMRD(n) (((n)-1)<<FMC_SDTR_TMRD_SHIFT) /* 1 to 16 cycles */
|
||||
#define FMC_SDTR_TXSR_SHIFT (4)
|
||||
#define FMC_SDTR_TXSR_MASK FMC_SDTR_TXSR(16)
|
||||
#define FMC_SDTR_TXSR(n) (((n)-1) << FMC_SDTR_TXSR_SHIFT)/* 1 to 16 cycles */
|
||||
#define FMC_SDTR_TRAS_SHIFT (8)
|
||||
#define FMC_SDTR_TRAS_MASK FMC_SDTR_TRAS(16)
|
||||
#define FMC_SDTR_TRAS(n) (((n)-1) << FMC_SDTR_TRAS_SHIFT)/* 1 to 16 cycles */
|
||||
#define FMC_SDTR_TRC_SHIFT (12)
|
||||
#define FMC_SDTR_TRC_MASK FMC_SDTR_TRC(16)
|
||||
#define FMC_SDTR_TRC(n) (((n)-1) << FMC_SDTR_TRC_SHIFT) /* 1 to 16 cycles */
|
||||
#define FMC_SDTR_TWR_SHIFT (16)
|
||||
#define FMC_SDTR_TWR_MASK FMC_SDTR_TWR(16)
|
||||
#define FMC_SDTR_TWR(n) (((n)-1) << FMC_SDTR_TWR_SHIFT) /* 1 to 16 cycles */
|
||||
#define FMC_SDTR_TRP_SHIFT (20)
|
||||
#define FMC_SDTR_TRP_MASK FMC_SDTR_TRP(16)
|
||||
#define FMC_SDTR_TRP(n) (((n)-1) << FMC_SDTR_TRP_SHIFT) /* 1 to 16 cycles */
|
||||
#define FMC_SDTR_TRCD_SHIFT (24)
|
||||
#define FMC_SDTR_TRCD_MASK FMC_SDTR_TRCD(16)
|
||||
#define FMC_SDTR_TRCD(n) (((n)-1) << FMC_SDTR_TRCD_SHIFT)/* 1 to 16 cycles */
|
||||
|
||||
# define FMC_SDRAM_CR_RPIPE_0 0x00000000
|
||||
# define FMC_SDRAM_CR_RPIPE_1 0x00002000
|
||||
# define FMC_SDRAM_CR_RPIPE_2 0x00004000
|
||||
#define FMC_SDTR_RESERVED (0xF << 28) /* reserved bits */
|
||||
|
||||
# define FMC_SDRAM_CR_RESERVED (0x1FFFF << 15) /* reserved bits */
|
||||
#define FMC_SDCMR_MODE_SHIFT (0)
|
||||
#define FMC_SDCMR_MODE_MASK (7 << FMC_SDCMR_MODE_SHIFT)
|
||||
# define FMC_SDCMR_MODE_NORMAL (0 << FMC_SDCMR_MODE_SHIFT)
|
||||
# define FMC_SDCMR_MODE_CLK_ENABLE (1 << FMC_SDCMR_MODE_SHIFT)
|
||||
# define FMC_SDCMR_MODE_PALL (2 << FMC_SDCMR_MODE_SHIFT)
|
||||
# define FMC_SDCMR_MODE_AUTO_REFRESH (3 << FMC_SDCMR_MODE_SHIFT)
|
||||
# define FMC_SDCMR_MODE_LOAD_MODE (4 << FMC_SDCMR_MODE_SHIFT)
|
||||
# define FMC_SDCMR_MODE_SELF_REFRESH (5 << FMC_SDCMR_MODE_SHIFT)
|
||||
# define FMC_SDCMR_MODE_POWER_DOWN (6 << FMC_SDCMR_MODE_SHIFT)
|
||||
#define FMC_SDCMR_CTB2 (1 << 3)
|
||||
#define FMC_SDCMR_CTB1 (1 << 4)
|
||||
#define FMC_SDCMR_NRFS_SHIFT (5)
|
||||
#define FMC_SDCMR_NRFS(n) (((n)-1)<<FMC_SDCMR_NRFS_SHIFT) /* 1 to 16 cycles */
|
||||
#define FMC_SDCMR_MRD_SHIFT (9)
|
||||
#define FMC_SDCMR_MRD_MASK FMC_SDCMR_MRD(16383)
|
||||
#define FMC_SDCMR_MRD(n) ((n) << FMC_SDCMR_MRD_SHIFT) /* SDRAM Mode Register */
|
||||
# define FMC_SDCMR_MRD_BURST_LENGTH_1 FMC_SDCMR_MRD(0x0000)
|
||||
# define FMC_SDCMR_MRD_BURST_LENGTH_2 FMC_SDCMR_MRD(0x0001)
|
||||
# define FMC_SDCMR_MRD_BURST_LENGTH_4 FMC_SDCMR_MRD(0x0002)
|
||||
# define FMC_SDCMR_MRD_BURST_LENGTH_8 FMC_SDCMR_MRD(0x0004)
|
||||
# define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL FMC_SDCMR_MRD(0x0000)
|
||||
# define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED FMC_SDCMR_MRD(0x0008)
|
||||
# define FMC_SDCMR_MRD_CAS_LATENCY_2 FMC_SDCMR_MRD(0x0020)
|
||||
# define FMC_SDCMR_MRD_CAS_LATENCY_3 FMC_SDCMR_MRD(0x0030)
|
||||
# define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD FMC_SDCMR_MRD(0x0000)
|
||||
# define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED FMC_SDCMR_MRD(0x0000)
|
||||
# define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE FMC_SDCMR_MRD(0x0200)
|
||||
|
||||
# define FMC_SDRAM_TR_TMRD_SHIFT 0
|
||||
# define FMC_SDRAM_TR_TXSR_SHIFT 4
|
||||
# define FMC_SDRAM_TR_TRAS_SHIFT 8
|
||||
# define FMC_SDRAM_TR_TRC_SHIFT 12
|
||||
# define FMC_SDRAM_TR_TWR_SHIFT 16
|
||||
# define FMC_SDRAM_TR_TRP_SHIFT 20
|
||||
# define FMC_SDRAM_TR_TRCD_SHIFT 24
|
||||
#define FMC_SDCMR_RESERVED (0x1ff << 23) /* reserved bits */
|
||||
|
||||
# define FMC_SDRAM_TR_RESERVED (0xF << 28) /* reserved bits */
|
||||
#define FMC_SDRTR_CRE (1 << 0)
|
||||
#define FMC_SDRTR_COUNT_SHIFT (1)
|
||||
#define FMC_SDRTR_COUNT_MASK FMC_SDRTR_COUNT(0x1fff)
|
||||
#define FMC_SDRTR_COUNT(val) ((val) << FMC_SDRTR_COUNT_SHIFT)
|
||||
#define FMC_SDRTR_REIE (14 << 0)
|
||||
|
||||
# define FMC_SDRAM_MODE_CMD_NORMAL 0
|
||||
# define FMC_SDRAM_MODE_CMD_CLK_ENABLE 1
|
||||
# define FMC_SDRAM_MODE_CMD_PALL 2
|
||||
# define FMC_SDRAM_MODE_CMD_AUTO_REFRESH 3
|
||||
# define FMC_SDRAM_MODE_CMD_LOAD_MODE 4
|
||||
# define FMC_SDRAM_MODE_CMD_SELF_REFRESH 5
|
||||
# define FMC_SDRAM_MODE_CMD_POWER_DOWN 6
|
||||
|
||||
# define FMC_SDRAM_CMD_BANK_1 0x00000010
|
||||
# define FMC_SDRAM_CMD_BANK_2 0x00000008
|
||||
# define FMC_SDRAM_CMD_RESERVED (0x200 << 23) /* reserved bits */
|
||||
|
||||
# define FMC_SDRAM_AUTO_REFRESH_SHIFT 5
|
||||
# define FMC_SDRAM_MODEREG_SHIFT 9
|
||||
|
||||
# define FMC_SDRAM_MODEREG_BURST_LENGTH_1 (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_BURST_LENGTH_2 (0x0001 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_BURST_LENGTH_4 (0x0002 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_BURST_LENGTH_8 (0x0004 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_CAS_LATENCY_2 (0x0020 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_CAS_LATENCY_3 (0x0030 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
#define FMC_SDSR_RE (1 << 0)
|
||||
#define FMC_SDSR_MODES1_SHIFT (1)
|
||||
#define FMC_SDSR_MODES1_MASK FMC_SDSR_MODES1(3)
|
||||
#define FMC_SDSR_MODES1(n) ((n) << FMC_SDSR_MODES1_SHIFT)
|
||||
# define FMC_SDSR_MODES1_NORMAL FMC_SDSR_MODES1(FMC_SDSR_MODES_NORMAL)
|
||||
# define FMC_SDSR_MODES1_SELF_REFRESH FMC_SDSR_MODES1(FMC_SDSR_MODES_SELF_REFRESH)
|
||||
# define FMC_SDSR_MODES1_POWER_DOWN FMC_SDSR_MODES1(FMC_SDSR_MODES_POWER_DOWN)
|
||||
#define FMC_SDSR_MODES2_SHIFT (3)
|
||||
#define FMC_SDSR_MODES2_MASK FMC_SDSR_MODES2(3)
|
||||
#define FMC_SDSR_MODES2(n) ((n) << FMC_SDSR_MODES2_SHIFT)
|
||||
# define FMC_SDSR_MODES2_NORMAL FMC_SDSR_MODES2(FMC_SDSR_MODES_NORMAL)
|
||||
# define FMC_SDSR_MODES2_SELF_REFRESH FMC_SDSR_MODES2(FMC_SDSR_MODES_SELF_REFRESH)
|
||||
# define FMC_SDSR_MODES2_POWER_DOWN FMC_SDSR_MODES2(FMC_SDSR_MODES_POWER_DOWN)
|
||||
#define FMC_SDSR_MODES_NORMAL (0)
|
||||
#define FMC_SDSR_MODES_SELF_REFRESH (1)
|
||||
#define FMC_SDSR_MODES_POWER_DOWN (2)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -60,33 +60,57 @@
|
||||
#include "hardware/stm32_memorymap.h"
|
||||
#include "stm32_mpuinit.h"
|
||||
#include "stm32_dtcm.h"
|
||||
#include "stm32_fmc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Internal SRAM is available in all members of the STM32 family. The
|
||||
* following definitions must be provided to specify the size and
|
||||
* location of internal(system) SRAM:
|
||||
/* At startup the kernel will invoke up_addregion() so that platform code
|
||||
* may register available memories for use as part of system heap.
|
||||
* The global configuration option CONFIG_MM_REGIONS defines the maximal
|
||||
* number of non-contiguous memory ranges that may be registered with the
|
||||
* system heap. You must make sure it is large enough to hold all memory
|
||||
* regions you intend to use.
|
||||
*
|
||||
* In addition to internal SRAM, external RAM may also be available through
|
||||
* the FMC. In order to use FMC RAM, the following additional things need
|
||||
* to be present in the NuttX configuration file:
|
||||
* The following memory types can be used for heap on STM32H7 platform:
|
||||
*
|
||||
* CONFIG_STM32H7_FMC=y : Enables the FMC
|
||||
* CONFIG_STM32H7_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC.
|
||||
* Either of these autoselects
|
||||
* CONFIG_ARCH_HAVE_HEAP2 which is what we
|
||||
* are interested in here.
|
||||
* CONFIG_HEAP2_BASE : The base address of the external RAM in
|
||||
* the FMC address space
|
||||
* CONFIG_HEAP2_SIZE : The size of the external RAM in the FMC
|
||||
* address space
|
||||
* CONFIG_MM_REGIONS : Must be set to a large enough value to
|
||||
* include the FMC external RAM (as determined
|
||||
* by the rules provided below)
|
||||
* - AXI SRAM is a 512kb memory area. This will be automatically registered
|
||||
* with the system heap in up_allocate_heap, all the other memory
|
||||
* regions will be registered in up_addregion().
|
||||
* So, CONFIG_MM_REGIONS must be at least 1 to use AXI SRAM.
|
||||
*
|
||||
* CONFIG_STM32H7_DTCMEXCLUDE : Set to exclude the DTCM from heap
|
||||
* - Internal SRAM is available in all members of the STM32 family.
|
||||
* This is always registered with system heap.
|
||||
* There are two contiguous regions of internal SRAM:
|
||||
* SRAM1+SRAM2+SRAM3 and SRAM4 at a separate address.
|
||||
* So, add 2 more to CONFIG_MM_REGIONS.
|
||||
*
|
||||
* - Tightly Coupled Memory (TCM RAM), we can use Data TCM (DTCM) for system
|
||||
* heap. Note that DTCM has a number of limitations, for example DMA
|
||||
* transfers to/from DTCM are limited.
|
||||
* Define CONFIG_STM32H7_DTCMEXCLUDE to exclude the DTCM from heap.
|
||||
* +1 to CONFIG_MM_REGIONS if you want to use DTCM.
|
||||
*
|
||||
* - External SDRAM can be connected to the FMC peripherial. Initialization
|
||||
* of FMC is done as up_addregion() will invoke stm32_fmc_init().
|
||||
* Please read the comment in stm32_fmc.c how to initialize FMC
|
||||
* correctly.
|
||||
*
|
||||
* Then, up to two regions of SDRAM may be registered with the heap:
|
||||
*
|
||||
* - BOARD_SDRAM1_SIZE, if defined, declares the size of SDRAM
|
||||
* at address STM32_FMC_BANK5. +1 to CONFIG_MM_REGIONS.
|
||||
* - BOARD_SDRAM2_SIZE, if defined, declares the size of SDRAM
|
||||
* at address STM32_FMC_BANK6. +1 to CONFIG_MM_REGIONS.
|
||||
*
|
||||
* - Additionaly, you may use the following options to add one more region
|
||||
* of memory to system heap:
|
||||
*
|
||||
* - CONFIG_ARCH_HAVE_HEAP2=y
|
||||
* - CONFIG_HEAP2_BASE=base address of memory area.
|
||||
* - CONFIG_HEAP2_SIZE=size of memory area.
|
||||
* - +1 to CONFIG_MM_REGIONS
|
||||
*/
|
||||
|
||||
/* Set the start and end of the SRAMs */
|
||||
@ -114,28 +138,6 @@
|
||||
# undef HAVE_DTCM
|
||||
#endif
|
||||
|
||||
/* There are <x> possible heap configurations:
|
||||
*
|
||||
* Configuration 1. System SRAM (only)
|
||||
* CONFIG_MM_REGIONS == 1
|
||||
* Configuration 2. System SRAM and SRAM123
|
||||
* CONFIG_MM_REGIONS == 2
|
||||
* Configuration 3. System SRAM and SRAM123 and DTCM
|
||||
* CONFIG_MM_REGIONS == 3
|
||||
* HAVE_DTCM defined
|
||||
* Configuration 4. System SRAM and SRAM123 and DTCM and SRAM4
|
||||
* CONFIG_MM_REGIONS == 4
|
||||
* HAVE_DTCM defined
|
||||
* Configuration 5. System SRAM and SRAM123 and DTCM and SRAM4 and FMC RAM
|
||||
* CONFIG_MM_REGIONS == 5
|
||||
* HAVE_DTCM defined
|
||||
*
|
||||
* TODO ....
|
||||
*
|
||||
* Let's make sure that all definitions are consistent before doing
|
||||
* anything else
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
@ -204,7 +206,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
|
||||
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
|
||||
*/
|
||||
|
||||
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
|
||||
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
|
||||
CONFIG_MM_KERNEL_HEAPSIZE;
|
||||
size_t usize = SRAM123_END - ubase;
|
||||
int log2;
|
||||
|
||||
@ -246,6 +249,10 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
|
||||
|
||||
up_heap_color(*heap_start, *heap_size);
|
||||
#endif
|
||||
|
||||
/* Display memory ranges to help debugging */
|
||||
|
||||
minfo("%uKb of SRAM at %p\n", *heap_size / 1024, *heap_start);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -266,7 +273,8 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
|
||||
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
|
||||
*/
|
||||
|
||||
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
|
||||
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
|
||||
CONFIG_MM_KERNEL_HEAPSIZE;
|
||||
size_t usize = SRAM123_END - ubase;
|
||||
int log2;
|
||||
|
||||
@ -292,6 +300,38 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: addregion
|
||||
*
|
||||
* Description:
|
||||
* Make a range of memory available for allocation from system heap.
|
||||
* If debug is disabled, compiler should optimize out the "desc" strings.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void addregion (uintptr_t start, uint32_t size, const char *desc)
|
||||
{
|
||||
/* Display memory ranges to help debugging */
|
||||
|
||||
minfo("%uKb of %s at %p\n", size / 1024, desc, (FAR void *)start);
|
||||
|
||||
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
|
||||
|
||||
/* Allow user-mode access to the SRAM123 heap */
|
||||
|
||||
stm32_mpu_uheap(start, size);
|
||||
|
||||
#endif
|
||||
|
||||
/* Colorize the heap for debug */
|
||||
|
||||
up_heap_color((FAR void *)start, size);
|
||||
|
||||
/* Add the SRAM123 user heap region. */
|
||||
|
||||
kumm_addregion((FAR void *)start, size);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_addregion
|
||||
*
|
||||
@ -301,81 +341,51 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if CONFIG_MM_REGIONS > 1
|
||||
void up_addregion(void)
|
||||
{
|
||||
# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
|
||||
addregion (SRAM123_START, SRAM123_END - SRAM123_START, "SRAM1,2,3");
|
||||
|
||||
/* Allow user-mode access to the SRAM123 heap */
|
||||
unsigned mm_regions = 1;
|
||||
|
||||
stm32_mpu_uheap((uintptr_t)SRAM123_START, SRAM123_END - SRAM123_START);
|
||||
if (mm_regions < CONFIG_MM_REGIONS)
|
||||
{
|
||||
addregion (SRAM4_START, SRAM4_END - SRAM4_START, "SRAM4");
|
||||
mm_regions++;
|
||||
}
|
||||
|
||||
# endif
|
||||
|
||||
/* Colorize the heap for debug */
|
||||
|
||||
up_heap_color((FAR void *)SRAM123_START, SRAM123_END - SRAM123_START);
|
||||
|
||||
/* Add the SRAM123 user heap region. */
|
||||
|
||||
kumm_addregion((FAR void *)SRAM123_START, SRAM123_END - SRAM123_START);
|
||||
|
||||
# if CONFIG_MM_REGIONS > 2
|
||||
# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
|
||||
|
||||
/* Allow user-mode access to the SRAM4 user heap memory */
|
||||
|
||||
stm32_mpu_uheap((uintptr_t)SRAM4_START, SRAM4_END - SRAM4_START);
|
||||
|
||||
# endif
|
||||
|
||||
/* Colorize the heap for debug */
|
||||
|
||||
up_heap_color((FAR void *)SRAM4_START, SRAM4_END - SRAM4_START);
|
||||
|
||||
/* Add the external SRAM4 user heap region. */
|
||||
|
||||
kumm_addregion((FAR void *)SRAM4_START, SRAM4_END - SRAM4_START);
|
||||
# endif
|
||||
|
||||
# if CONFIG_MM_REGIONS > 3
|
||||
# ifdef HAVE_DTCM
|
||||
# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
|
||||
|
||||
/* Allow user-mode access to the DTCM heap */
|
||||
|
||||
stm32_mpu_uheap((uintptr_t)DTCM_START, DTCM_END - DTCM_START);
|
||||
|
||||
# endif
|
||||
|
||||
/* Colorize the heap for debug */
|
||||
|
||||
up_heap_color((FAR void *)DTCM_START, DTCM_END - DTCM_START);
|
||||
|
||||
/* Add the DTCM user heap region. */
|
||||
|
||||
kumm_addregion((FAR void *)DTCM_START, DTCM_END - DTCM_START);
|
||||
# endif
|
||||
# endif
|
||||
|
||||
# if CONFIG_MM_REGIONS > 4
|
||||
# ifdef CONFIG_ARCH_HAVE_HEAP2
|
||||
# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
|
||||
|
||||
/* Allow user-mode access to the FMC RAM user heap memory */
|
||||
|
||||
stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
|
||||
|
||||
# endif
|
||||
|
||||
/* Colorize the heap for debug */
|
||||
|
||||
up_heap_color((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
|
||||
|
||||
/* Add the external FMC RAM user heap region. */
|
||||
|
||||
kumm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
|
||||
# endif
|
||||
# endif
|
||||
}
|
||||
#ifdef HAVE_DTCM
|
||||
if (mm_regions < CONFIG_MM_REGIONS)
|
||||
{
|
||||
addregion (DTCM_START, DTCM_END - DTCM_START, "DTCM");
|
||||
mm_regions++;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_FMC
|
||||
stm32_fmc_init();
|
||||
#endif
|
||||
|
||||
#ifdef BOARD_SDRAM1_SIZE
|
||||
if (mm_regions < CONFIG_MM_REGIONS)
|
||||
{
|
||||
addregion (STM32_FMC_BANK5, BOARD_SDRAM1_SIZE, "SDRAM1");
|
||||
mm_regions++;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BOARD_SDRAM2_SIZE
|
||||
if (mm_regions < CONFIG_MM_REGIONS)
|
||||
{
|
||||
addregion (STM32_FMC_BANK6, BOARD_SDRAM2_SIZE, "SDRAM2");
|
||||
mm_regions++;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_HAVE_HEAP2
|
||||
if (mm_regions < CONFIG_MM_REGIONS)
|
||||
{
|
||||
addregion (CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE, "HEAP2");
|
||||
mm_regions++;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -39,40 +39,410 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32H7_FMC)
|
||||
|
||||
#include "stm32.h"
|
||||
|
||||
#if defined(CONFIG_STM32H7_FMC)
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
/****************************************************************************
|
||||
* To use FMC, you must first enable it in configuration:
|
||||
*
|
||||
* CONFIG_STM32H7_FMC=y
|
||||
*
|
||||
* FMC is statically configured at startup. Its configuration is adjusted
|
||||
* using BOARD_XXX macros described below, which should be declared
|
||||
* in your board.h file.
|
||||
*
|
||||
* The BOARD_FMC_CLK macro can be defined to select the clock source for FMC.
|
||||
* This can be one of RCC_D1CCIPR_FMCSEL_xxx macros, and defaults to
|
||||
* RCC_D1CCIPR_FMCSEL_PLL2 (which means PLL2R).
|
||||
*
|
||||
*
|
||||
* To correctly initialize GPIO pins the macro BOARD_FMC_GPIO_CONFIGS should
|
||||
* define a list of 32-bit GPIO configuration bitmasks. Example:
|
||||
*
|
||||
* #define BOARD_FMC_GPIO_CONFIGS GPIO_FMC_A0,GPIO_FMC_A1,\
|
||||
* GPIO_FMC_A2,...,GPIO_FMC_D0,...,GPIO_FMC_NBL0,...
|
||||
*
|
||||
*
|
||||
* For SRAM/NOR-Flash memories FMC defines 4 x 64Mb sub-banks at addresses
|
||||
* 0x60000000, 0x64000000, 0x68000000, 0x6C000000. The following macros
|
||||
* can be defined in board.h to initialize FMC for use with SRAM/NOR-Flash:
|
||||
*
|
||||
* *** CURRENTLY SRAM/NOR-FLASH SUPPORT IS NOT IMPLEMENTED ***
|
||||
*
|
||||
* BOARD_FMC_BCR[1..4] - Initial value for control registers
|
||||
* for subbanks 1-4.
|
||||
* BOARD_FMC_BTR[1..4] - Initial value for SRAM/NOR-Flash timing registers
|
||||
* for subbanks 1-4.
|
||||
* BOARD_FMC_BWTR[1..4] - Initial value for SRAM/NOR-Flash write timing
|
||||
* registers for subbanks 1-4.
|
||||
*
|
||||
*
|
||||
* For NAND flash memories FMC reserves 64Mb at 0x80000000. Define the
|
||||
* following macros in your board.h file to initialize FMC for this type
|
||||
* of memory:
|
||||
*
|
||||
* *** CURRENTLY NAND FLASH SUPPORT IS NOT IMPLEMENTED ***
|
||||
*
|
||||
* BOARD_FMC_PCR - Initial value for NAND flash control register.
|
||||
* BOARD_FMC_PMEM - Initial value for NAND flash common memory space timing
|
||||
* register.
|
||||
* BOARD_FMC_PATT - Initial value for NAND flash attribute memory space
|
||||
* timing register.
|
||||
*
|
||||
*
|
||||
* For SDRAM memory FMC reserves 2 x 256Mb address ranges at 0xC0000000
|
||||
* and 0xD0000000. Define the following macros to initialize FMC to work
|
||||
* with SDRAM:
|
||||
*
|
||||
* BOARD_FMC_SDCR[1..2] - Initial value for SDRAM control registers for SDRAM
|
||||
* bank 1-2. Note that some bits in SDCR1 influence both SDRAM banks and
|
||||
* are unused in SDCR2!
|
||||
* BOARD_FMC_SDTR[1..2] - Initial value for SDRAM timing registeres for SDRAM
|
||||
* bank 1-2. Note that some bits in SDTR1 influence both SDRAM banks and
|
||||
* are unused in SDTR2!
|
||||
* BOARD_FMC_SDRAM_REFR_PERIOD - The SDRAM refresh rate period in FMC clocks,
|
||||
* OR
|
||||
* BOARD_FMC_SDRAM_REFR_CYCLES and BOARD_FMC_SDRAM_REFR_PERIOD can be used to
|
||||
* automatically compute refresh counter using data from SDRAM datasheet
|
||||
* (cycles usually is 4096, 8192 and such, and typical period is 64 ms)
|
||||
* and knowing FMC clock frequency.
|
||||
* BOARD_FMC_SDRAM_AUTOREFRESH may be defined to a number between 1 and 16 to
|
||||
* issue given number of SDRAM auto-refresh cycles before using it. This
|
||||
* defaults to 3.
|
||||
*
|
||||
*
|
||||
* Special notes:
|
||||
* - FMC bank remapping (FMC_BCR_BMAP*) is not currently supported.
|
||||
*
|
||||
*
|
||||
* Here's a working example of a configured IS42S16320D SDRAM on a particular
|
||||
* board:
|
||||
*
|
||||
*#define BOARD_SDRAM1_SIZE (64*1024*1024)
|
||||
*
|
||||
*#define BOARD_FMC_SDCR1 \
|
||||
* (FMC_SDCR_COLBITS_10 | FMC_SDCR_ROWBITS_13 | FMC_SDCR_WIDTH_16 |\
|
||||
* FMC_SDCR_BANKS_4 | FMC_SDCR_CASLAT_2 | FMC_SDCR_SDCLK_2X |\
|
||||
* FMC_SDCR_BURST_READ | FMC_SDCR_RPIPE_1)
|
||||
*#define BOARD_FMC_SDTR1 \
|
||||
* (FMC_SDTR_TMRD(2) | FMC_SDTR_TXSR(7) | FMC_SDTR_TRAS(4) | \
|
||||
* FMC_SDTR_TRC(7) | FMC_SDTR_TWR(4) | FMC_SDTR_TRP(2) | \
|
||||
* FMC_SDTR_TRCD(2))
|
||||
*#define BOARD_FMC_SDRAM_REFR_CYCLES 8192
|
||||
*#define BOARD_FMC_SDRAM_REFR_PERIOD 64
|
||||
*#define BOARD_FMC_SDRAM_MODE \
|
||||
* FMC_SDCMR_MRD_BURST_LENGTH_8 | \
|
||||
* FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL | \
|
||||
* FMC_SDCMR_MRD_CAS_LATENCY_2
|
||||
*
|
||||
*#define BOARD_FMC_GPIO_CONFIGS \
|
||||
* GPIO_FMC_A0,GPIO_FMC_A1,GPIO_FMC_A2,GPIO_FMC_A3,GPIO_FMC_A4,\
|
||||
* GPIO_FMC_A5,GPIO_FMC_A6,GPIO_FMC_A7,GPIO_FMC_A8,GPIO_FMC_A9,\
|
||||
* GPIO_FMC_A10,GPIO_FMC_A11,GPIO_FMC_A12,\
|
||||
* GPIO_FMC_D0,GPIO_FMC_D1,GPIO_FMC_D2,GPIO_FMC_D3,GPIO_FMC_D4,\
|
||||
* GPIO_FMC_D5,GPIO_FMC_D6,GPIO_FMC_D7,GPIO_FMC_D8,GPIO_FMC_D9,\
|
||||
* GPIO_FMC_D10,GPIO_FMC_D11,GPIO_FMC_D12,GPIO_FMC_D13,\
|
||||
* GPIO_FMC_D14,GPIO_FMC_D15,\
|
||||
* GPIO_FMC_NBL0,GPIO_FMC_NBL1,GPIO_FMC_BA0,GPIO_FMC_BA1,\
|
||||
* GPIO_FMC_SDNWE_2,GPIO_FMC_SDNCAS,GPIO_FMC_SDNRAS,\
|
||||
* GPIO_FMC_SDNE0_1,GPIO_FMC_SDCKE0_1,GPIO_FMC_SDCLK
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef BOARD_FMC_CLK
|
||||
/* Clock FMC from PLL2R by default */
|
||||
|
||||
# define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_PLL2
|
||||
#endif
|
||||
|
||||
/* A couple of macros to know if user uses SDRAM1 and/or SDRAM2 */
|
||||
|
||||
#if defined BOARD_FMC_SDCR1 && ((BOARD_FMC_SDCR1 & FMC_SDCR_CASLAT_MASK) != 0)
|
||||
# define HAVE_FMC_SDRAM1 1
|
||||
#endif
|
||||
#if defined BOARD_FMC_SDCR2 && ((BOARD_FMC_SDCR2 & FMC_SDCR_CASLAT_MASK) != 0)
|
||||
# define HAVE_FMC_SDRAM2 1
|
||||
#endif
|
||||
|
||||
#if defined HAVE_FMC_SDRAM1 || defined HAVE_FMC_SDRAM2
|
||||
# define HAVE_FMC_SDRAM 1
|
||||
#endif
|
||||
|
||||
/* Number of auto-refresh cycles to issue at SDRAM initialization */
|
||||
|
||||
#ifndef BOARD_FMC_SDRAM_AUTOREFRESH
|
||||
# define BOARD_FMC_SDRAM_AUTOREFRESH 3
|
||||
#endif
|
||||
|
||||
/* Find out the clock frequency for FMC */
|
||||
|
||||
#if BOARD_FMC_CLK == RCC_D1CCIPR_FMCSEL_HCLK
|
||||
# define FMC_CLK_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#elif BOARD_FMC_CLK == RCC_D1CCIPR_FMCSEL_PLL1
|
||||
# define FMC_CLK_FREQUENCY STM32_PLL1Q_FREQUENCY
|
||||
#elif BOARD_FMC_CLK == RCC_D1CCIPR_FMCSEL_PLL2
|
||||
# define FMC_CLK_FREQUENCY STM32_PLL2R_FREQUENCY
|
||||
#elif BOARD_FMC_CLK == RCC_D1CCIPR_FMCSEL_PER
|
||||
# define FMC_CLK_FREQUENCY STM32_PER_FREQUENCY
|
||||
#else
|
||||
# error "BOARD_FMC_CLK has unknown value!"
|
||||
#endif
|
||||
|
||||
/* Compute the refresh rate in clocks */
|
||||
|
||||
#ifndef BOARD_FMC_SDRAM_REFR_PERIOD
|
||||
|
||||
# if !defined(BOARD_FMC_SDRAM_REFR_CYCLES) || !defined(BOARD_FMC_SDRAM_REFR_PERIOD)
|
||||
# error "Both BOARD_FMC_SDRAM_REFR_CYCLES and BOARD_FMC_SDRAM_REFR_PERIOD have to be defined to compute BOARD_FMC_SDRAM_REFR_PERIOD!"
|
||||
# else
|
||||
/* Take care not to overflow on 32-bit arithmetic */
|
||||
|
||||
# define BOARD_FMC_SDRAM_REFR_PERIOD ((uint32_t)((uint64_t)BOARD_FMC_SDRAM_REFR_PERIOD * FMC_CLK_FREQUENCY / BOARD_FMC_SDRAM_REFR_CYCLES - 20))
|
||||
# endif
|
||||
|
||||
#endif /* BOARD_FMC_SDRAM_REFR_PERIOD */
|
||||
|
||||
/* The bits in FMC_SDCR we will alter at initialization */
|
||||
|
||||
#define FMC_SDCR_MASK (FMC_SDCR_COLBITS_MASK | FMC_SDCR_ROWBITS_MASK | \
|
||||
FMC_SDCR_WIDTH_MASK | FMC_SDCR_BANKS_MASK | FMC_SDCR_CASLAT_MASK | FMC_SDCR_WP | \
|
||||
FMC_SDCR_SDCLK_MASK | FMC_SDCR_BURST_READ | FMC_SDCR_RPIPE_MASK)
|
||||
|
||||
/* The bits in FMC_SDTR we will alter at initialization */
|
||||
|
||||
#define FMC_SDTR_MASK (FMC_SDTR_TMRD_MASK | FMC_SDTR_TXSR_MASK | \
|
||||
FMC_SDTR_TRAS_MASK | FMC_SDTR_TRC_MASK | FMC_SDTR_TWR_MASK | FMC_SDTR_TRP_MASK | \
|
||||
FMC_SDTR_TRCD_MASK)
|
||||
|
||||
/* The timeout while waiting for SDRAM controller to initialize, in us */
|
||||
|
||||
#define SDRAM_INIT_TIMEOUT (1000)
|
||||
|
||||
/****************************************************************************
|
||||
* Private data
|
||||
****************************************************************************/
|
||||
|
||||
static uint32_t fmc_gpios[] =
|
||||
{
|
||||
BOARD_FMC_GPIO_CONFIGS
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
static void stm32_fmc_sdram_init(void);
|
||||
static int stm32_fmc_sdram_wait(unsigned timeout);
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_enable
|
||||
* Name: stm32_fmc_init
|
||||
*
|
||||
* Description:
|
||||
* Enable clocking to the FMC.
|
||||
* Initialize the FMC peripherial. Because FMC initialization is highly
|
||||
* dependent on the used parts, definition of the initial values for FMC
|
||||
* registers is mostly left to board designer.
|
||||
*
|
||||
* Typically called from up_addregion().
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_enable_clk(void)
|
||||
void stm32_fmc_init(void)
|
||||
{
|
||||
modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FMCEN);
|
||||
uint32_t regval;
|
||||
|
||||
/* Reset the FMC on the AHB3 bus */
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB3RSTR);
|
||||
regval |= RCC_AHB3RSTR_FMCRST;
|
||||
putreg32(regval, STM32_RCC_AHB3RSTR);
|
||||
|
||||
/* Leave reset state */
|
||||
|
||||
regval &= ~RCC_AHB3RSTR_FMCRST;
|
||||
putreg32(regval, STM32_RCC_AHB3RSTR);
|
||||
|
||||
/* Set FMC clocking */
|
||||
|
||||
modreg32 (BOARD_FMC_CLK, RCC_D1CCIPR_FMCSEL_MASK, STM32_RCC_D1CCIPR);
|
||||
|
||||
/* Set up FMC GPIOs */
|
||||
|
||||
for (regval = 0; regval < ARRAY_SIZE(fmc_gpios); regval++)
|
||||
stm32_configgpio(fmc_gpios[regval]);
|
||||
|
||||
/* Set up FMC registers */
|
||||
|
||||
#ifdef BOARD_FMC_SDCR1
|
||||
modreg32(BOARD_FMC_SDCR1, FMC_SDCR_MASK, STM32_FMC_SDCR1);
|
||||
#endif
|
||||
#ifdef BOARD_FMC_SDCR2
|
||||
modreg32(BOARD_FMC_SDCR2, FMC_SDCR_MASK, STM32_FMC_SDCR2);
|
||||
#endif
|
||||
|
||||
#ifdef BOARD_FMC_SDTR1
|
||||
modreg32(BOARD_FMC_SDTR1, FMC_SDTR_MASK, STM32_FMC_SDTR1);
|
||||
#endif
|
||||
#ifdef BOARD_FMC_SDTR2
|
||||
modreg32(BOARD_FMC_SDTR2, FMC_SDTR_MASK, STM32_FMC_SDTR2);
|
||||
#endif
|
||||
|
||||
/* Enable the FMC peripherial */
|
||||
|
||||
modreg32(FMC_BCR_FMCEN, FMC_BCR_FMCEN, STM32_FMC_BCR1);
|
||||
|
||||
/* Initialize the SDRAM chips themselves */
|
||||
|
||||
#ifdef HAVE_FMC_SDRAM
|
||||
stm32_fmc_sdram_init();
|
||||
#endif
|
||||
|
||||
/* Set up SDRAM refresh timings */
|
||||
|
||||
#ifdef BOARD_FMC_SDRAM_REFR_PERIOD
|
||||
/* ... The programmed COUNT value must not be equal to the sum of the
|
||||
* following timings: TWR+TRP+TRC+TRCD+4 memory clock cycles
|
||||
*/
|
||||
|
||||
#ifdef BOARD_FMC_SDTR1
|
||||
DEBUGASSERT (BOARD_FMC_SDRAM_REFR_PERIOD !=
|
||||
(4 +
|
||||
(1 + ((BOARD_FMC_SDTR1 & FMC_SDTR_TWR_MASK) >> FMC_SDTR_TWR_SHIFT)) +
|
||||
(1 + ((BOARD_FMC_SDTR1 & FMC_SDTR_TRP_MASK) >> FMC_SDTR_TRP_SHIFT)) +
|
||||
(1 + ((BOARD_FMC_SDTR1 & FMC_SDTR_TRC_MASK) >> FMC_SDTR_TRC_SHIFT)) +
|
||||
(1 + ((BOARD_FMC_SDTR1 & FMC_SDTR_TRCD_MASK) >> FMC_SDTR_TRCD_SHIFT))));
|
||||
#endif
|
||||
#ifdef BOARD_FMC_SDTR2
|
||||
DEBUGASSERT (BOARD_FMC_SDRAM_REFR_PERIOD !=
|
||||
(4 +
|
||||
(1 + ((BOARD_FMC_SDTR2 & FMC_SDTR_TWR_MASK) >> FMC_SDTR_TWR_SHIFT)) +
|
||||
(1 + ((BOARD_FMC_SDTR2 & FMC_SDTR_TRP_MASK) >> FMC_SDTR_TRP_SHIFT)) +
|
||||
(1 + ((BOARD_FMC_SDTR2 & FMC_SDTR_TRC_MASK) >> FMC_SDTR_TRC_SHIFT)) +
|
||||
(1 + ((BOARD_FMC_SDTR2 & FMC_SDTR_TRCD_MASK) >> FMC_SDTR_TRCD_SHIFT))));
|
||||
#endif
|
||||
|
||||
stm32_fmc_sdram_set_refresh_rate(BOARD_FMC_SDRAM_REFR_PERIOD);
|
||||
#endif /* BOARD_FMC_SDRTR */
|
||||
}
|
||||
|
||||
#ifdef HAVE_FMC_SDRAM
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_init
|
||||
*
|
||||
* Description:
|
||||
* Initialize the SDRAM chips.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined HAVE_FMC_SDRAM1 && defined HAVE_FMC_SDRAM2
|
||||
# define FMC_SDCMR_CTB FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2
|
||||
#elif defined HAVE_FMC_SDRAM1
|
||||
# define FMC_SDCMR_CTB FMC_SDCMR_CTB1
|
||||
#else
|
||||
# define FMC_SDCMR_CTB FMC_SDCMR_CTB2
|
||||
#endif
|
||||
|
||||
void stm32_fmc_sdram_init(void)
|
||||
{
|
||||
/* What is happening here:
|
||||
* ... A 100μs delay is required prior to issuing any command [...]
|
||||
* a PRECHARGE command should be applied once the 100μs delay has been
|
||||
* satisfied.
|
||||
*
|
||||
* All banks must be precharged. This will leave all banks in an idle
|
||||
* state after which at least two AUTO REFRESH cycles must be performed.
|
||||
* After the AUTO REFRESH cycles are complete, the SDRAM is then ready
|
||||
* for mode register programming.
|
||||
*
|
||||
* The mode register should be loaded prior to applying any operational
|
||||
* command because it will power up in an unknown state.
|
||||
*/
|
||||
|
||||
up_udelay(100);
|
||||
|
||||
/* Clock Configuration Enable */
|
||||
|
||||
stm32_fmc_sdram_command(FMC_SDCMR_CTB | FMC_SDCMR_MODE_CLK_ENABLE);
|
||||
|
||||
/* Wait for clock to stabilize */
|
||||
|
||||
up_mdelay(1);
|
||||
|
||||
/* Precharge all banks */
|
||||
|
||||
stm32_fmc_sdram_wait(SDRAM_INIT_TIMEOUT);
|
||||
stm32_fmc_sdram_command(FMC_SDCMR_CTB | FMC_SDCMR_MODE_PALL);
|
||||
|
||||
/* Auto refresh */
|
||||
|
||||
stm32_fmc_sdram_wait(SDRAM_INIT_TIMEOUT);
|
||||
stm32_fmc_sdram_command(FMC_SDCMR_CTB | FMC_SDCMR_MODE_AUTO_REFRESH |
|
||||
FMC_SDCMR_NRFS(BOARD_FMC_SDRAM_AUTOREFRESH));
|
||||
|
||||
/* Program the SDRAM mode register */
|
||||
|
||||
/* If using two SDRAM chips, this will write same mode for both.
|
||||
* If different mode is required for every chip (why?), it would be
|
||||
* needed to split code into two separate LOAD_MODE commands,
|
||||
* one for every SDRAM chip.
|
||||
*/
|
||||
|
||||
stm32_fmc_sdram_wait(SDRAM_INIT_TIMEOUT);
|
||||
stm32_fmc_sdram_command(FMC_SDCMR_CTB | FMC_SDCMR_MODE_LOAD_MODE |
|
||||
BOARD_FMC_SDRAM_MODE);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_disable
|
||||
* Name: stm32_fmc_sdram_wait
|
||||
*
|
||||
* Description:
|
||||
* Disable clocking to the FMC.
|
||||
* Wait until SDRAM controller is ready for all configured SDRAM banks.
|
||||
*
|
||||
* Parameters:
|
||||
* timeout - number of microseconds before giving up waiting.
|
||||
*
|
||||
* Returns:
|
||||
* 0 if all configured SDRAM banks are ready, -1 on timeout
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_disable(void)
|
||||
int stm32_fmc_sdram_wait(unsigned timeout)
|
||||
{
|
||||
modifyreg32(STM32_RCC_AHB3ENR, RCC_AHB3ENR_FMCEN, 0);
|
||||
/* Wait until the SDRAM controller is ready */
|
||||
|
||||
for (; timeout; timeout--)
|
||||
{
|
||||
uint32_t sdsr = getreg32(STM32_FMC_SDSR);
|
||||
if (1
|
||||
#if defined HAVE_FMC_SDRAM1
|
||||
&& ((sdsr & FMC_SDSR_MODES1_MASK) == FMC_SDSR_MODES1_NORMAL)
|
||||
#endif
|
||||
#if defined HAVE_FMC_SDRAM2
|
||||
&& ((sdsr & FMC_SDSR_MODES2_MASK) == FMC_SDSR_MODES2_NORMAL)
|
||||
#endif
|
||||
)
|
||||
return 0;
|
||||
|
||||
up_udelay(1);
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_write_protect
|
||||
*
|
||||
@ -92,11 +462,11 @@ void stm32_fmc_sdram_write_protect(int bank, bool state)
|
||||
val = getreg32(sdcr);
|
||||
if (state)
|
||||
{
|
||||
val |= FMC_SDRAM_CR_WRITE_PROTECT; /* wp == 1 */
|
||||
val |= FMC_SDCR_WP; /* wp == 1 */
|
||||
}
|
||||
else
|
||||
{
|
||||
val &= ~FMC_SDRAM_CR_WRITE_PROTECT; /* wp == 0 */
|
||||
val &= ~FMC_SDCR_WP; /* wp == 0 */
|
||||
}
|
||||
|
||||
putreg32(val, sdcr);
|
||||
@ -112,10 +482,8 @@ void stm32_fmc_sdram_write_protect(int bank, bool state)
|
||||
|
||||
void stm32_fmc_sdram_set_refresh_rate(int count)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
DEBUGASSERT(count <= 0x1fff && count >= 0x29);
|
||||
putreg32(count << 1, STM32_FMC_SDRTR);
|
||||
putreg32(FMC_SDRTR_COUNT(count), STM32_FMC_SDRTR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -132,11 +500,11 @@ void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
|
||||
uint32_t sdtr;
|
||||
|
||||
DEBUGASSERT((bank == 1) || (bank == 2));
|
||||
DEBUGASSERT((timing & FMC_SDRAM_TR_RESERVED) == 0);
|
||||
DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0);
|
||||
|
||||
sdtr = (bank == 1) ? STM32_FMC_SDTR1 : STM32_FMC_SDTR2;
|
||||
val = getreg32(sdtr);
|
||||
val &= FMC_SDRAM_TR_RESERVED; /* preserve reserved bits */
|
||||
val &= FMC_SDTR_RESERVED; /* preserve reserved bits */
|
||||
val |= timing;
|
||||
putreg32(val, sdtr);
|
||||
}
|
||||
@ -170,11 +538,11 @@ void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
|
||||
uint32_t sdcr;
|
||||
|
||||
DEBUGASSERT((bank == 1) || (bank == 2));
|
||||
DEBUGASSERT((ctrl & FMC_SDRAM_CR_RESERVED) == 0);
|
||||
DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0);
|
||||
|
||||
sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
|
||||
val = getreg32(sdcr);
|
||||
val &= FMC_SDRAM_CR_RESERVED; /* preserve reserved bits */
|
||||
val &= FMC_SDCR_RESERVED; /* preserve reserved bits */
|
||||
val |= ctrl;
|
||||
putreg32(val, sdcr);
|
||||
}
|
||||
@ -189,7 +557,7 @@ void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
|
||||
|
||||
void stm32_fmc_sdram_command(uint32_t cmd)
|
||||
{
|
||||
DEBUGASSERT((cmd & FMC_SDRAM_CMD_RESERVED) == 0);
|
||||
DEBUGASSERT((cmd & FMC_SDCMR_RESERVED) == 0);
|
||||
putreg32(cmd, STM32_FMC_SDCMR);
|
||||
}
|
||||
|
||||
|
||||
@ -45,10 +45,6 @@
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32_fmc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
@ -61,14 +57,22 @@ extern "C"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_wait
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_init
|
||||
*
|
||||
* Description:
|
||||
* Wait for the SDRAM controller to be ready.
|
||||
* Initialize the FMC peripherial. Because FMC initialization is highly
|
||||
* dependent on the used parts, definition of the initial values for FMC
|
||||
* registers is mostly left to board designer.
|
||||
*
|
||||
* Typically called from up_addregion().
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_wait(void);
|
||||
void stm32_fmc_init(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_enable
|
||||
|
||||
@ -298,6 +298,12 @@ static inline void rcc_enableahb3(void)
|
||||
regval |= RCC_AHB3ENR_SDMMC1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_FMC
|
||||
/* Flexible static memory controller module clock enable */
|
||||
|
||||
regval |= RCC_AHB3ENR_FMCEN;
|
||||
#endif
|
||||
|
||||
/* TODO: ... */
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
|
||||
@ -775,7 +781,7 @@ static void stm32_stdclockconfig(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Ww must write the lower byte of the PWR_CR3 register is written once
|
||||
/* We must write the lower byte of the PWR_CR3 register is written once
|
||||
* after POR and it shall be written before changing VOS level or
|
||||
* ck_sys clock frequency. No limitation applies to the upper bytes.
|
||||
*
|
||||
|
||||
@ -142,8 +142,8 @@ static inline void rcc_reset(void)
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR)
|
||||
/* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to data
|
||||
* read corruption. See ES0392 Rev 6.
|
||||
/* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to
|
||||
* data read corruption. See ES0392 Rev 6.
|
||||
*/
|
||||
|
||||
putreg32(AXI_TARG_READ_ISS_OVERRIDE, STM32_AXI_TARG7_FN_MOD);
|
||||
@ -298,6 +298,12 @@ static inline void rcc_enableahb3(void)
|
||||
regval |= RCC_AHB3ENR_SDMMC1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_FMC
|
||||
/* Flexible static memory controller module clock enable */
|
||||
|
||||
regval |= RCC_AHB3ENR_FMCEN;
|
||||
#endif
|
||||
|
||||
/* TODO: ... */
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
|
||||
@ -775,16 +781,16 @@ static void stm32_stdclockconfig(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Ww must write the lower byte of the PWR_CR3 register is written once
|
||||
* after POR and it shall be written before changing VOS level or ck_sys
|
||||
* clock frequency. No limitation applies to the upper bytes.
|
||||
/* We must write the lower byte of the PWR_CR3 register is written once
|
||||
* after POR and it shall be written before changing VOS level or
|
||||
* ck_sys clock frequency. No limitation applies to the upper bytes.
|
||||
*
|
||||
* Programming data corresponding to an invalid combination of
|
||||
* LDOEN and BYPASS bits will be ignored: data will not be written,
|
||||
* the written-once mechanism will lock the register and any further
|
||||
* write access will be ignored. The default supply configuration will
|
||||
* be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1)
|
||||
* will go on indicating invalid voltage levels.
|
||||
* be kept and the ACTVOSRDY bit in PWR control status register 1
|
||||
* (PWR_CSR1) will go on indicating invalid voltage levels.
|
||||
*
|
||||
* N.B. The system shall be power cycled before writing a new value.
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user