From 3ff956dc00e20be33476dca1da4cc4b987bc0ba2 Mon Sep 17 00:00:00 2001 From: Andrey Zabolotnyi Date: Wed, 25 Mar 2020 18:34:15 +0300 Subject: [PATCH] stm32h7: support SDRAM via FMC peripherial (#459) * stm32h7: Add support for SDRAM connected to FMC * stm32h7: nxstyle fixes in stm32_fmc.h and stm32h7x3xx_rcc.{c,h} --- arch/arm/src/common/up_arch.h | 6 + arch/arm/src/stm32h7/Kconfig | 18 +- arch/arm/src/stm32h7/hardware/stm32_fmc.h | 606 ++++---- .../src/stm32h7/hardware/stm32h7x3xx_rcc.h | 1272 +++++++++-------- arch/arm/src/stm32h7/stm32_allocateheap.c | 240 ++-- arch/arm/src/stm32h7/stm32_fmc.c | 406 +++++- arch/arm/src/stm32h7/stm32_fmc.h | 18 +- arch/arm/src/stm32h7/stm32h7x3xx_rcc.c | 8 +- arch/arm/src/stm32h7/stm32h7x7xx_rcc.c | 20 +- 9 files changed, 1507 insertions(+), 1087 deletions(-) diff --git a/arch/arm/src/common/up_arch.h b/arch/arm/src/common/up_arch.h index e43ecb0aac..a3536aee38 100644 --- a/arch/arm/src/common/up_arch.h +++ b/arch/arm/src/common/up_arch.h @@ -58,6 +58,12 @@ # define getreg32(a) (*(volatile uint32_t *)(a)) # define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) +/* Non-atomic, but more effective modification of registers */ + +# define modreg8(v,m,a) putreg8((getreg8(a) & ~(m)) | ((v) & (m)), a) +# define modreg16(v,m,a) putreg16((getreg16(a) & ~(m)) | ((v) & (m)), a) +# define modreg32(v,m,a) putreg32((getreg32(a) & ~(m)) | ((v) & (m)), a) + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index ea5db7febd..c0044dcc1b 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -289,9 +289,13 @@ config STM32H7_ETHMAC select ARCH_HAVE_PHY config STM32H7_FMC - bool "FMC" - default n - depends on STM32H7_HAVE_FMC + bool "FMC" + default n + depends on STM32H7_HAVE_FMC + ---help--- + Enable Flexible Memory Controller. + To correctly configure FMC for your hardware, you will have to define + a number of macros in your board.h file. See stm32_fmc.c for directions. config STM32H7_OTGFS bool "OTG FS" @@ -1187,14 +1191,6 @@ endif # STM32H7_RTC_LSECLOCK endmenu # RTC Configuration -config STM32H7_EXTERNAL_RAM - bool "External RAM on FMC" - default n - depends on STM32H7_FMC - select ARCH_HAVE_HEAP2 - ---help--- - In addition to internal SDRAM, external RAM may be available through the FMC. - menu "QuadSPI Configuration" depends on STM32H7_QUADSPI diff --git a/arch/arm/src/stm32h7/hardware/stm32_fmc.h b/arch/arm/src/stm32h7/hardware/stm32_fmc.h index 31f726fbf4..26ec2994f7 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_fmc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_fmc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/***************************************************************************************************************************************************** * arch/arm/src/stm32h7/hardware/stm32_fmc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -31,360 +31,380 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + *****************************************************************************************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H #define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H -/************************************************************************************ +/***************************************************************************************************************************************************** * Included Files - ************************************************************************************/ + *****************************************************************************************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/***************************************************************************************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + *****************************************************************************************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets **********************************************************************************************************************************/ -#define STM32_FMC_BCR_OFFSET(n) (8*((n)-1)) -#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */ -#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */ -#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */ -#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */ +#define STM32_FMC_BCR_OFFSET(n) (8*((n)-1)) +#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */ +#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */ +#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */ +#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */ -#define STM32_FMC_BTR_OFFSET(n) (8*((n)-1)+0x0004) -#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */ -#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */ -#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */ -#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */ +#define STM32_FMC_BTR_OFFSET(n) (8*((n)-1)+0x0004) +#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */ +#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */ +#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */ +#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */ -#define STM32_FMC_BWTR_OFFSET(n) (8*((n)-1)+0x0104) -#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */ -#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */ -#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */ -#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */ +#define STM32_FMC_BWTR_OFFSET(n) (8*((n)-1)+0x0104) +#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */ +#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */ +#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */ +#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */ -#define STM32_FMC_PCR_OFFSET(n) (0x0020*((n)-1)+0x0040) -#define STM32_FMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */ -#define STM32_FMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */ -#define STM32_FMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */ +#define STM32_FMC_PCR_OFFSET 0x0080 /* NAND Flash control register */ -#define STM32_FMC_SR_OFFSET(n) (0x0020*((n)-1)+0x0044) -#define STM32_FMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */ -#define STM32_FMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */ -#define STM32_FMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */ +#define STM32_FMC_SR_OFFSET 0x0084 /* FIFO status and interrupt register */ -#define STM32_FMC_PMEM_OFFSET(n) (0x0020*((n)-1)+0x0048) -#define STM32_FMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */ -#define STM32_FMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */ -#define STM32_FMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */ +#define STM32_FMC_PMEM_OFFSET 0x0088 /* Common memory space timing register */ -#define STM32_FMC_PATT_OFFSET(n) (0x0020*((n)-1)+0x004c) -#define STM32_FMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */ -#define STM32_FMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */ -#define STM32_FMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */ +#define STM32_FMC_PATT_OFFSET 0x008c /* Attribute memory space timing register */ -#define STM32_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */ +#define STM32_FMC_ECCR_OFFSET 0x0094 /* ECC result register */ -#define STM32_FMC_ECCR_OFFSET(n) (0x0020*((n)-1)+0x003c) -#define STM32_FMC_ECCR2_OFFSET 0x0054 /* ECC result register 2 */ -#define STM32_FMC_ECCR3_OFFSET 0x0074 /* ECC result register 3 */ +#define STM32_FMC_SDCR_OFFSET(n) (4*((n)-1)+0x0140) +#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 1 */ +#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */ -#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 0 */ -#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */ +#define STM32_FMC_SDTR_OFFSET(n) (4*((n)-1)+0x0148) +#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 0 */ +#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 1 */ -#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 0 */ -#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 1 */ +#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Command mode register */ +#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */ +#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */ -#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Config Memory register */ -#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */ -#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */ +/* Register Addresses ********************************************************************************************************************************/ -/* Register Addresses ***************************************************************/ +#define STM32_FMC_BCR(n) (STM32_FMC_BASE+STM32_FMC_BCR_OFFSET(n)) +#define STM32_FMC_BCR1 (STM32_FMC_BASE+STM32_FMC_BCR1_OFFSET ) +#define STM32_FMC_BCR2 (STM32_FMC_BASE+STM32_FMC_BCR2_OFFSET ) +#define STM32_FMC_BCR3 (STM32_FMC_BASE+STM32_FMC_BCR3_OFFSET ) +#define STM32_FMC_BCR4 (STM32_FMC_BASE+STM32_FMC_BCR4_OFFSET ) -#define STM32_FMC_BCR(n) (STM32_FMC_BASE+STM32_FMC_BCR_OFFSET(n)) -#define STM32_FMC_BCR1 (STM32_FMC_BASE+STM32_FMC_BCR1_OFFSET ) -#define STM32_FMC_BCR2 (STM32_FMC_BASE+STM32_FMC_BCR2_OFFSET ) -#define STM32_FMC_BCR3 (STM32_FMC_BASE+STM32_FMC_BCR3_OFFSET ) -#define STM32_FMC_BCR4 (STM32_FMC_BASE+STM32_FMC_BCR4_OFFSET ) +#define STM32_FMC_BTR(n) (STM32_FMC_BASE+STM32_FMC_BTR_OFFSET(n)) +#define STM32_FMC_BTR1 (STM32_FMC_BASE+STM32_FMC_BTR1_OFFSET ) +#define STM32_FMC_BTR2 (STM32_FMC_BASE+STM32_FMC_BTR2_OFFSET ) +#define STM32_FMC_BTR3 (STM32_FMC_BASE+STM32_FMC_BTR3_OFFSET ) +#define STM32_FMC_BTR4 (STM32_FMC_BASE+STM32_FMC_BTR4_OFFSET ) -#define STM32_FMC_BTR(n) (STM32_FMC_BASE+STM32_FMC_BTR_OFFSET(n)) -#define STM32_FMC_BTR1 (STM32_FMC_BASE+STM32_FMC_BTR1_OFFSET ) -#define STM32_FMC_BTR2 (STM32_FMC_BASE+STM32_FMC_BTR2_OFFSET ) -#define STM32_FMC_BTR3 (STM32_FMC_BASE+STM32_FMC_BTR3_OFFSET ) -#define STM32_FMC_BTR4 (STM32_FMC_BASE+STM32_FMC_BTR4_OFFSET ) +#define STM32_FMC_BWTR(n) (STM32_FMC_BASE+STM32_FMC_BWTR_OFFSET(n)) +#define STM32_FMC_BWTR1 (STM32_FMC_BASE+STM32_FMC_BWTR1_OFFSET ) +#define STM32_FMC_BWTR2 (STM32_FMC_BASE+STM32_FMC_BWTR2_OFFSET ) +#define STM32_FMC_BWTR3 (STM32_FMC_BASE+STM32_FMC_BWTR3_OFFSET ) +#define STM32_FMC_BWTR4 (STM32_FMC_BASE+STM32_FMC_BWTR4_OFFSET ) -#define STM32_FMC_BWTR(n) (STM32_FMC_BASE+STM32_FMC_BWTR_OFFSET(n)) -#define STM32_FMC_BWTR1 (STM32_FMC_BASE+STM32_FMC_BWTR1_OFFSET ) -#define STM32_FMC_BWTR2 (STM32_FMC_BASE+STM32_FMC_BWTR2_OFFSET ) -#define STM32_FMC_BWTR3 (STM32_FMC_BASE+STM32_FMC_BWTR3_OFFSET ) -#define STM32_FMC_BWTR4 (STM32_FMC_BASE+STM32_FMC_BWTR4_OFFSET ) +#define STM32_FMC_PCR (STM32_FMC_BASE+STM32_FMC_PCR_OFFSET) -#define STM32_FMC_PCR(n) (STM32_FMC_BASE+STM32_FMC_PCR_OFFSET(n)) -#define STM32_FMC_PCR2 (STM32_FMC_BASE+STM32_FMC_PCR2_OFFSET ) -#define STM32_FMC_PCR3 (STM32_FMC_BASE+STM32_FMC_PCR3_OFFSET ) -#define STM32_FMC_PCR4 (STM32_FMC_BASE+STM32_FMC_PCR4_OFFSET ) +#define STM32_FMC_SR (STM32_FMC_BASE+STM32_FMC_SR_OFFSET) -#define STM32_FMC_SR(n) (STM32_FMC_BASE+STM32_FMC_SR_OFFSET(n)) -#define STM32_FMC_SR2 (STM32_FMC_BASE+STM32_FMC_SR2_OFFSET ) -#define STM32_FMC_SR3 (STM32_FMC_BASE+STM32_FMC_SR3_OFFSET ) -#define STM32_FMC_SR4 (STM32_FMC_BASE+STM32_FMC_SR4_OFFSET ) +#define STM32_FMC_PMEM (STM32_FMC_BASE+STM32_FMC_PMEM_OFFSET) -#define STM32_FMC_PMEM(n) (STM32_FMC_BASE+STM32_FMC_PMEM_OFFSET(n)) -#define STM32_FMC_PMEM2 (STM32_FMC_BASE+STM32_FMC_PMEM2_OFFSET ) -#define STM32_FMC_PMEM3 (STM32_FMC_BASE+STM32_FMC_PMEM3_OFFSET ) -#define STM32_FMC_PMEM4 (STM32_FMC_BASE+STM32_FMC_PMEM4_OFFSET ) +#define STM32_FMC_PATT (STM32_FMC_BASE+STM32_FMC_PATT_OFFSET) -#define STM32_FMC_PATT(n) (STM32_FMC_BASE+STM32_FMC_PATT_OFFSET(n)) -#define STM32_FMC_PATT2 (STM32_FMC_BASE+STM32_FMC_PATT2_OFFSET ) -#define STM32_FMC_PATT3 (STM32_FMC_BASE+STM32_FMC_PATT3_OFFSET ) -#define STM32_FMC_PATT4 (STM32_FMC_BASE+STM32_FMC_PATT4_OFFSET ) +#define STM32_FMC_ECCR (STM32_FMC_BASE+STM32_FMC_ECCR_OFFSET) -#define STM32_PIO4 (STM32_FMC_BASE+STM32_FMC_PIO4_OFFSET ) +#define STM32_FMC_SDCR1 (STM32_FMC_BASE+STM32_FMC_SDCR1_OFFSET) +#define STM32_FMC_SDCR2 (STM32_FMC_BASE+STM32_FMC_SDCR2_OFFSET) -#define STM32_FMC_ECCR(n) (STM32_FMC_BASE+STM32_FMC_ECCR_OFFSET(n)) -#define STM32_FMC_ECCR2 (STM32_FMC_BASE+STM32_FMC_ECCR2_OFFSET ) -#define STM32_FMC_ECCR3 (STM32_FMC_BASE+STM32_FMC_ECCR3_OFFSET ) +#define STM32_FMC_SDTR1 (STM32_FMC_BASE+STM32_FMC_SDTR1_OFFSET) +#define STM32_FMC_SDTR2 (STM32_FMC_BASE+STM32_FMC_SDTR2_OFFSET) -#define STM32_FMC_SDCR1 (STM32_FMC_BASE+STM32_FMC_SDCR1_OFFSET) -#define STM32_FMC_SDCR2 (STM32_FMC_BASE+STM32_FMC_SDCR2_OFFSET) +#define STM32_FMC_SDCMR (STM32_FMC_BASE+STM32_FMC_SDCMR_OFFSET) +#define STM32_FMC_SDRTR (STM32_FMC_BASE+STM32_FMC_SDRTR_OFFSET) +#define STM32_FMC_SDSR (STM32_FMC_BASE+STM32_FMC_SDSR_OFFSET) -#define STM32_FMC_SDTR1 (STM32_FMC_BASE+STM32_FMC_SDTR1_OFFSET) -#define STM32_FMC_SDTR2 (STM32_FMC_BASE+STM32_FMC_SDTR2_OFFSET) +/* Register Bitfield Definitions *********************************************************************************************************************/ -#define STM32_FMC_SDCMR (STM32_FMC_BASE+STM32_FMC_SDCMR_OFFSET) -#define STM32_FMC_SDRTR (STM32_FMC_BASE+STM32_FMC_SDRTR_OFFSET) -#define STM32_FMC_SDSR (STM32_FMC_BASE+STM32_FMC_SDSR_OFFSET) +#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */ +#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */ +#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */ +#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT) +#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */ +#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT) +# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT) +# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT) +# define FMC_BCR_MWID32 (2 << FMC_BCR_MWID_SHIFT) +#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */ +#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */ +#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */ +#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */ +#define FMC_BCR_WREN (1 << 12) /* Write enable bit */ +#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ +#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ +#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ +#define FMC_BCR_CPSIZE_SHIFT (16) +#define FMC_BCR_CPSIZE_MASK (7 << FMC_BCR_CPSIZE_SHIFT) +# define FMC_BCR_CPSIZE0 (0 << FMC_BCR_CPSIZE_SHIFT) +# define FMC_BCR_CPSIZE128 (1 << FMC_BCR_CPSIZE_SHIFT) +# define FMC_BCR_CPSIZE256 (2 << FMC_BCR_CPSIZE_SHIFT) +# define FMC_BCR_CPSIZE1024 (3 << FMC_BCR_CPSIZE_SHIFT) +#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ +#define FMC_BCR_CCLKEN (1 << 20) /* Continuous Clock Enable */ +#define FMC_BCR_WFDIS (1 << 21) /* Write FIFO Disable */ +#define FMC_BCR_BMAP_SHIFT (24) +#define FMC_BCR_BMAP_MASK (3 << FMC_BCR_BMAP_SHIFT) +# define FMC_BCR_BMAP0 (0 << FMC_BCR_BMAP_SHIFT) /* Default mapping */ +# define FMC_BCR_BMAP1 (1 << FMC_BCR_BMAP_SHIFT) /* NOR/PSRAM bank and SDRAM bank 1/bank2 are swapped */ +# define FMC_BCR_BMAP2 (2 << FMC_BCR_BMAP_SHIFT) /* SDRAM Bank2 remapped on FMC bank2 and still accessible at default mapping */ +#define FMC_BCR_FMCEN (1 << 31) /* FMC controller Enable */ -/* Register Bitfield Definitions ****************************************************/ +#define FMC_BCR_RSTVALUE(n) ((n == 0) ? 0x000030db : 0x000030d2) /* Reset value for BCR */ -#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */ -#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */ -#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */ -#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT) -#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */ -#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT) -# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT) -# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT) -#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */ -#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */ -#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */ -#define FMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */ -#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */ -#define FMC_BCR_WREN (1 << 12) /* Write enable bit */ -#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ -#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ -#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ -#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ -#define FMC_BCR_BMAP_SHIFT (24) -# define FMC_BCR_BMAP_0 (0 << FMC_BCR_BMAP_SHIFT) -# define FMC_BCR_BMAP_1 (1 << FMC_BCR_BMAP_SHIFT) -# define FMC_BCR_BMAP_2 (2 << FMC_BCR_BMAP_SHIFT) +#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */ +#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT) +# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ +#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ +#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT) +# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ +#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */ +#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT) +# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ +#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */ +#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT) +# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT)/* (n)xHCLK n=1..16 */ +#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ +#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT) +# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ +#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */ +#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT) +# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT) + /* (n)xHCLK n=2..17 */ +#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */ +#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT) +# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT) +# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT) +# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT) +# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT) -#define FMC_BCR_FMCEN (1 << 31) /* Write burst enable */ +#define FMC_BTR_RSTVALUE 0xffffffff -#define FMC_BCR_RSTVALUE 0x000003d2 +#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */ +#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT) +# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT)/* (n)xHCLK n=1..16 */ +#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ +#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT) +# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT)/* (n)xHCLK n=2..16 */ +#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */ +#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT) +# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT)/* (n)xHCLK n=2..256 */ +#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ +#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT) +# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT)/* (n)xHCLK n=2..16 */ +#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */ +#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT) +# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT)/* (n)xHCLK n=2..17 */ +#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */ +#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT) +# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT) +# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT) +# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT) +# define FMC_BWTR_ACCMODD (3 << FMC_BWTR_ACCMOD_SHIFT) -#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */ -#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT) -# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ -#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ -#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT) -# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ -#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */ -#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT) -# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ -#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */ -#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT) -# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */ -#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ -#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT) -# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ -#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */ -#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT) -# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ -#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */ -#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT) -# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT) -# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT) -# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT) -# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT) +#define FMC_PCR_RSTVALUE (0x00000018) -#define FMC_BTR_RSTVALUE 0xffffffff +#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */ +#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */ +#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */ +#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT) +# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT) +# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT) +#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */ +#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */ +#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT) +# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */ +#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */ +#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK) +# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */ +#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */ +#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT) +# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */ +# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */ +# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ +# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */ +# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */ +# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ -#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */ -#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT) -# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ -#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ -#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT) -# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ -#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */ -#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT) -# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ -#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ -#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT) -# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ -#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */ -#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT) -# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ -#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */ -#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT) -# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT) -# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT) -# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT) -# define FMC_BWTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT) +#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */ +#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */ +#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */ +#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */ +#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */ +#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */ +#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */ -#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */ -#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */ -#define FMC_PCR_PTYP (1 << 3) /* Memory type */ -#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */ -#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT) -# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT) -# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT) -#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */ -#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */ -#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT) -# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */ -#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */ -#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK) -# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */ -#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */ -#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT) -# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */ -# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */ -# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ -# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */ -# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */ -# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ +#define FMC_PMEM_RSTVALUE (0xfcfcfcfc) -#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */ -#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */ -#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */ -#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */ -#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */ -#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */ -#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */ +#define FMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */ +#define FMC_PMEM_MEMSET_MASK (255 << FMC_PMEM_MEMSET_SHIFT) +# define FMC_PMEM_MEMSET(n) ((n-1) << FMC_PMEM_MEMSET_SHIFT)/* (n)xHCLK n=1..256 */ +#define FMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */ +#define FMC_PMEM_MEMWAIT_MASK (255 << FMC_PMEM_MEMWAIT_SHIFT) +# define FMC_PMEM_MEMWAIT(n) ((n-1)< -/**************************************************************************************************** +/*************************************************************************************************************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ***************************************************************************************************************************************************************************/ -/* Register Offsets *********************************************************************************/ +/* Register Offsets ********************************************************************************************************************************************************/ /* TODO: Complete comments */ #define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32_RCC_ICSCR_OFFSET 0x0004 /* */ -#define STM32_RCC_CRRCR_OFFSET 0x0008 /* */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 +#define STM32_RCC_CRRCR_OFFSET 0x0008 #define STM32_RCC_CFGR_OFFSET 0x0010 /* Clock configuration register */ -#define STM32_RCC_D1CFGR_OFFSET 0x0018 /* */ -#define STM32_RCC_D2CFGR_OFFSET 0x001c /* */ -#define STM32_RCC_D3CFGR_OFFSET 0x0020 /* */ -#define STM32_RCC_PLLCKSELR_OFFSET 0x0028 /* */ -#define STM32_RCC_PLLCFGR_OFFSET 0x002c /* */ -#define STM32_RCC_PLL1DIVR_OFFSET 0x0030 /* */ -#define STM32_RCC_PLL1FRACR_OFFSET 0x0034 /* */ -#define STM32_RCC_PLL2DIVR_OFFSET 0x0038 /* */ -#define STM32_RCC_PLL2FRACR_OFFSET 0x003c /* */ -#define STM32_RCC_PLL3DIVR_OFFSET 0x0040 /* */ -#define STM32_RCC_PLL3FRACR_OFFSET 0x0044 /* */ +#define STM32_RCC_D1CFGR_OFFSET 0x0018 +#define STM32_RCC_D2CFGR_OFFSET 0x001c +#define STM32_RCC_D3CFGR_OFFSET 0x0020 +#define STM32_RCC_PLLCKSELR_OFFSET 0x0028 +#define STM32_RCC_PLLCFGR_OFFSET 0x002c +#define STM32_RCC_PLL1DIVR_OFFSET 0x0030 +#define STM32_RCC_PLL1FRACR_OFFSET 0x0034 +#define STM32_RCC_PLL2DIVR_OFFSET 0x0038 +#define STM32_RCC_PLL2FRACR_OFFSET 0x003c +#define STM32_RCC_PLL3DIVR_OFFSET 0x0040 +#define STM32_RCC_PLL3FRACR_OFFSET 0x0044 #define STM32_RCC_D1CCIPR_OFFSET 0x004c /* Domain 1 Kernel Clock configuration register */ #define STM32_RCC_D2CCIP1R_OFFSET 0x0050 /* Domain 2 Kernel Clock configuration register 1 */ #define STM32_RCC_D2CCIP2R_OFFSET 0x0054 /* Domain 2 Kernel Clock configuration register 2 */ @@ -107,7 +107,7 @@ #define STM32_RCC_APB3LPENR_OFFSET 0x010c /* RCC APB3 low power mode peripheral clock enable register */ #define STM32_RCC_APB4LPENR_OFFSET 0x011c /* RCC APB4 low power mode peripheral clock enable register */ -/* Register Addresses *******************************************************************************/ +/* Register Addresses ******************************************************************************************************************************************************/ #define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) #define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) @@ -164,111 +164,111 @@ #define STM32_RCC_APB3LPENR (STM32_RCC_BASE + STM32_RCC_APB3LPENR_OFFSET) #define STM32_RCC_APB4LPENR (STM32_RCC_BASE + STM32_RCC_APB4LPENR_OFFSET) -/* Register Bitfield Definitions ********************************************************************/ +/* Register Bitfield Definitions *******************************************************************************************************************************************/ /* Source Control Register */ -#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ -#define RCC_CR_HSIKERON (1 << 1) /* Bit 1: Internal High Speed clock enable for some IPs Kernel ?? */ -#define RCC_CR_HSIRDY (1 << 2) /* Bit 2: Internal High Speed clock ready flag */ -#define RCC_CR_HSIDIV_SHIFT (3) /* Bits 3-4: HSI clock divider */ -#define RCC_CR_HSIDIV_MASK (3 << RCC_CR_HSIDIV_SHIFT) /* 00: */ -# define RCC_CR_HSIDIV_1 (0 << RCC_CR_HSIDIV_SHIFT) /* 01: */ -# define RCC_CR_HSIDIV_2 (1 << RCC_CR_HSIDIV_SHIFT) /* 10: */ -# define RCC_CR_HSIDIV_4 (2 << RCC_CR_HSIDIV_SHIFT) /* 10: */ -# define RCC_CR_HSIDIV_8 (3 << RCC_CR_HSIDIV_SHIFT) /* 11: */ -#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI Divider flag */ - /* Bit 6: Reserved */ -#define RCC_CR_CSION (1 << 7) /* Bit 7: The Internal RC 4MHz oscillator clock enable */ -#define RCC_CR_CSIRDY (1 << 8) /* Bit 8: The Internal RC 4MHz oscillator clock ready */ -#define RCC_CR_CSIKERON (1 << 9) /* Bit 9: Internal RC 4MHz oscillator clock enable for some IPs Kernel */ - /* Bits 10-11: Reserved */ -#define RCC_CR_HSI48ON (1 << 12) /* Bit 12: HSI48 clock enable clock enable */ -#define RCC_CR_HSI48RDY (1 << 13) /* Bit 13: HSI48 clock ready */ -#define RCC_CR_D1CKRDY (1 << 14) /* Bit 14: D1 domain clocks ready flag */ -#define RCC_CR_D2CKRDY (1 << 15) /* Bit 15: D2 domain clocks ready flag */ -#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ -#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready */ -#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */ -#define RCC_CR_CSSHSEON (1 << 19) /* Bit 19: HSE Clock security System enable */ - /* Bits 20-23: Reserved */ -#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: System PLL1 clock enable */ -#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: System PLL1 clock ready */ -#define RCC_CR_PLL2ON (1 << 26) /* Bit 26: System PLL2 clock enable */ -#define RCC_CR_PLL2RDY (1 << 27) /* Bit 27: System PLL2 clock ready */ -#define RCC_CR_PLL3ON (1 << 28) /* Bit 28: System PLL3 clock enable */ -#define RCC_CR_PLL3RDY (1 << 29) /* Bit 29: System PLL3 clock ready */ - /* Bits 30-31: Reserved */ +#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ +#define RCC_CR_HSIKERON (1 << 1) /* Bit 1: Internal High Speed clock enable for some IPs Kernel ?? */ +#define RCC_CR_HSIRDY (1 << 2) /* Bit 2: Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIV_SHIFT (3) /* Bits 3-4: HSI clock divider */ +#define RCC_CR_HSIDIV_MASK (3 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV_1 (0 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV_2 (1 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV_4 (2 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV_8 (3 << RCC_CR_HSIDIV_SHIFT) +#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI Divider flag */ + /* Bit 6: Reserved */ +#define RCC_CR_CSION (1 << 7) /* Bit 7: The Internal RC 4MHz oscillator clock enable */ +#define RCC_CR_CSIRDY (1 << 8) /* Bit 8: The Internal RC 4MHz oscillator clock ready */ +#define RCC_CR_CSIKERON (1 << 9) /* Bit 9: Internal RC 4MHz oscillator clock enable for some IPs Kernel */ + /* Bits 10-11: Reserved */ +#define RCC_CR_HSI48ON (1 << 12) /* Bit 12: HSI48 clock enable clock enable */ +#define RCC_CR_HSI48RDY (1 << 13) /* Bit 13: HSI48 clock ready */ +#define RCC_CR_D1CKRDY (1 << 14) /* Bit 14: D1 domain clocks ready flag */ +#define RCC_CR_D2CKRDY (1 << 15) /* Bit 15: D2 domain clocks ready flag */ +#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */ +#define RCC_CR_CSSHSEON (1 << 19) /* Bit 19: HSE Clock security System enable */ + /* Bits 20-23: Reserved */ +#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: System PLL1 clock enable */ +#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: System PLL1 clock ready */ +#define RCC_CR_PLL2ON (1 << 26) /* Bit 26: System PLL2 clock enable */ +#define RCC_CR_PLL2RDY (1 << 27) /* Bit 27: System PLL2 clock ready */ +#define RCC_CR_PLL3ON (1 << 28) /* Bit 28: System PLL3 clock enable */ +#define RCC_CR_PLL3RDY (1 << 29) /* Bit 29: System PLL3 clock ready */ + /* Bits 30-31: Reserved */ /* Internal Clock Source Calibration Register */ /* HSICAL configuration */ #define RCC_ICSCR_HSICAL_SHIFT (0ul) -#define RCC_ICSCR_HSICAL_MASK (0xFFFul << RCC_ICSCR_HSICAL_SHIFT) /* 0x00000FFF */ -#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_MASK /* HSICAL[11:0] bits */ +#define RCC_ICSCR_HSICAL_MASK (0xFFFul << RCC_ICSCR_HSICAL_SHIFT) +#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_MASK /* HSICAL[11:0] bits */ /* HSITRIM configuration */ #define RCC_ICSCR_HSITRIM_SHIFT (12ul) -#define RCC_ICSCR_HSITRIM_MASK (0x3Ful << RCC_ICSCR_HSITRIM_SHIFT) /* 0x0003F000 */ -#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_MASK /* HSITRIM[5:0] bits */ +#define RCC_ICSCR_HSITRIM_MASK (0x3Ful << RCC_ICSCR_HSITRIM_SHIFT) +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_MASK /* HSITRIM[5:0] bits */ /* CSICAL configuration */ #define RCC_ICSCR_CSICAL_SHIFT (18ul) -#define RCC_ICSCR_CSICAL_MASK (0xFFul << RCC_ICSCR_CSICAL_SHIFT) /* 0x03FC0000 */ -#define RCC_ICSCR_CSICAL RCC_ICSCR_CSICAL_MASK /* CSICAL[7:0] bits */ +#define RCC_ICSCR_CSICAL_MASK (0xFFul << RCC_ICSCR_CSICAL_SHIFT) +#define RCC_ICSCR_CSICAL RCC_ICSCR_CSICAL_MASK /* CSICAL[7:0] bits */ /* CSITRIM configuration */ #define RCC_ICSCR_CSITRIM_SHIFT (26ul) -#define RCC_ICSCR_CSITRIM_MASK (0x1Ful << RCC_ICSCR_CSITRIM_SHIFT) /* 0x7C000000 */ -#define RCC_ICSCR_CSITRIM RCC_ICSCR_CSITRIM_MASK /* CSITRIM[4:0] bits */ +#define RCC_ICSCR_CSITRIM_MASK (0x1Ful << RCC_ICSCR_CSITRIM_SHIFT) +#define RCC_ICSCR_CSITRIM RCC_ICSCR_CSITRIM_MASK /* CSITRIM[4:0] bits */ /* Clock Recovery RC Register */ /* HSI48CAL configuration */ #define RCC_CRRCR_HSI48CAL_SHIFT (0ul) -#define RCC_CRRCR_HSI48CAL_MASK (0x3FFul << RCC_CRRCR_HSI48CAL_SHIFT) /* 0x000003FF */ -#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_MASK /* HSI48CAL[9:0] bits */ +#define RCC_CRRCR_HSI48CAL_MASK (0x3FFul << RCC_CRRCR_HSI48CAL_SHIFT) +#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_MASK /* HSI48CAL[9:0] bits */ /* Clock Configuration Register (CFGR) */ -#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-2: System clock Switch */ +#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-2: System clock Switch */ #define RCC_CFGR_SW_MASK (7 << RCC_CFGR_SW_SHIFT) -# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 000: HSI selection as system clock */ -# define RCC_CFGR_SW_CSI (1 << RCC_CFGR_SW_SHIFT) /* 001: CSI selection as system clock */ -# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 010: HSE selection as system clock */ -# define RCC_CFGR_SW_PLL1 (3 << RCC_CFGR_SW_SHIFT) /* 011: PLL1 selection as system clock */ -#define RCC_CFGR_SWS_SHIFT (3) /* Bits 3-5: System Clock Switch Status */ +# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 000: HSI selection as system clock */ +# define RCC_CFGR_SW_CSI (1 << RCC_CFGR_SW_SHIFT) /* 001: CSI selection as system clock */ +# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 010: HSE selection as system clock */ +# define RCC_CFGR_SW_PLL1 (3 << RCC_CFGR_SW_SHIFT) /* 011: PLL1 selection as system clock */ +#define RCC_CFGR_SWS_SHIFT (3) /* Bits 3-5: System Clock Switch Status */ #define RCC_CFGR_SWS_MASK (7 << RCC_CFGR_SWS_SHIFT) -# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 000: HSI used as system clock */ -# define RCC_CFGR_SWS_CSI (1 << RCC_CFGR_SWS_SHIFT) /* 001: CSI used as system clock */ -# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 010: HSE used as system clock */ -# define RCC_CFGR_SWS_PLL1 (3 << RCC_CFGR_SWS_SHIFT) /* 011: PLL1 used as system clock */ -#define RCC_CFGR_STOPWUCK (1 << 6) /* Bit 6: Wake Up from stop and CSS backup clock selection */ -#define RCC_CFGR_STOPKERWUCK (1 << 7) /* Bit 7: Kernel Clock Selection after a Wake Up from STOP */ -#define RCC_CFGR_RTCPRE_SHIFT (8) /* Bits 8-13: HSE division factor for RTC clock */ +# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 000: HSI used as system clock */ +# define RCC_CFGR_SWS_CSI (1 << RCC_CFGR_SWS_SHIFT) /* 001: CSI used as system clock */ +# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 010: HSE used as system clock */ +# define RCC_CFGR_SWS_PLL1 (3 << RCC_CFGR_SWS_SHIFT) /* 011: PLL1 used as system clock */ +#define RCC_CFGR_STOPWUCK (1 << 6) /* Bit 6: Wake Up from stop and CSS backup clock selection */ +#define RCC_CFGR_STOPKERWUCK (1 << 7) /* Bit 7: Kernel Clock Selection after a Wake Up from STOP */ +#define RCC_CFGR_RTCPRE_SHIFT (8) /* Bits 8-13: HSE division factor for RTC clock */ #define RCC_CFGR_RTCPRE_MASK (0x3f << RCC_CFGR_RTCPRE_SHIFT) # define RCC_CFGR_RTCPRE(x) (((uint32_t)(x)) << RCC_CFGR_RTCPRE_SHIFT) -#define RCC_CFGR_HRTIMSEL (1 << 14) /* Bit 14: HRTIM TImer clock prescaler */ -#define RCC_CFGR_TIMPRE (1 << 15) /* Timers clocks prescaler */ -#define RCC_CFGR_MCO1PRE_SHIFT (18) /* Bits 18-21: MCO1 prescaler */ +#define RCC_CFGR_HRTIMSEL (1 << 14) /* Bit 14: HRTIM TImer clock prescaler */ +#define RCC_CFGR_TIMPRE (1 << 15) /* Timers clocks prescaler */ +#define RCC_CFGR_MCO1PRE_SHIFT (18) /* Bits 18-21: MCO1 prescaler */ #define RCC_CFGR_MCO1PRE_MASK (0xf << RCC_CFGR_MCO1PRE_SHIFT) # define RCC_CFGR_MCO1PRE(x) (((uint32_t)(x)) << 18) -#define RCC_CFGR_MCO1_SHIFT (22) /* Bits 22-24: Microcontroller Clock Output 1 */ +#define RCC_CFGR_MCO1_SHIFT (22) /* Bits 22-24: Microcontroller Clock Output 1 */ #define RCC_CFGR_MCO1_MASK (7 << RCC_CFGR_MCO1_SHIFT) # define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */ # define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */ # define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */ # define RCC_CFGR_MCO1_PLL1Q (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */ # define RCC_CFGR_MCO1_HSI48 (4 << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */ -#define RCC_CFGR_MCO2PRE_SHIFT (25) /* Bits 25-28: MCO2 prescaler */ +#define RCC_CFGR_MCO2PRE_SHIFT (25) /* Bits 25-28: MCO2 prescaler */ #define RCC_CFGR_MCO2PRE_MASK (0xf << RCC_CFGR_MCO2PRE_SHIFT) # define RCC_CFGR_MCO2PRE(x) (((uint32_t)(x)) << RCC_CFGR_MCO2PRE_SHIFT) -#define RCC_CFGR_MCO2_SHIFT (29) /* Bits 29-31: Microcontroller Clock Output 2 */ +#define RCC_CFGR_MCO2_SHIFT (29) /* Bits 29-31: Microcontroller Clock Output 2 */ #define RCC_CFGR_MCO2_MASK (7 << RCC_CFGR_MCO2_SHIFT) # define RCC_CFGR_MCO2_SYS (0 << RCC_CFGR_MCO2_SHIFT) /* 000: HSI clock selected */ # define RCC_CFGR_MCO2_PLL2P (1 << RCC_CFGR_MCO2_SHIFT) /* 001: PLL2 peripheral clock selected */ @@ -281,86 +281,86 @@ #define RCC_D1CFGR_HPRE_SHIFT (0) /* Bits 0-3: D1 domain AHB prescaler */ #define RCC_D1CFGR_HPRE_MASK (15 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLK (0 << RCC_D1CFGR_HPRE_SHIFT) /* 0xxx: */ -# define RCC_D1CFGR_HPRE_SYSCLKd2 (8 << RCC_D1CFGR_HPRE_SHIFT) /* 1000: */ -# define RCC_D1CFGR_HPRE_SYSCLKd4 (9 << RCC_D1CFGR_HPRE_SHIFT) /* 1001: */ -# define RCC_D1CFGR_HPRE_SYSCLKd8 (10 << RCC_D1CFGR_HPRE_SHIFT) /* 1010: */ -# define RCC_D1CFGR_HPRE_SYSCLKd16 (11 << RCC_D1CFGR_HPRE_SHIFT) /* 1011: */ -# define RCC_D1CFGR_HPRE_SYSCLKd64 (12 << RCC_D1CFGR_HPRE_SHIFT) /* 1100: */ -# define RCC_D1CFGR_HPRE_SYSCLKd128 (13 << RCC_D1CFGR_HPRE_SHIFT) /* 1101: */ -# define RCC_D1CFGR_HPRE_SYSCLKd256 (14 << RCC_D1CFGR_HPRE_SHIFT) /* 1110: */ -# define RCC_D1CFGR_HPRE_SYSCLKd512 (15 << RCC_D1CFGR_HPRE_SHIFT) /* 1111: */ +# define RCC_D1CFGR_HPRE_SYSCLK (0 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd2 (8 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd4 (9 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd8 (10 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd16 (11 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd64 (12 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd128 (13 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd256 (14 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd512 (15 << RCC_D1CFGR_HPRE_SHIFT) #define RCC_D1CFGR_D1PPRE_SHIFT (4) /* Bits 4-6: D1 domain APB3 prescaler */ #define RCC_D1CFGR_D1PPRE_MASK (7 << RCC_D1CFGR_D1PPRE_SHIFT) -# define RCC_D1CFGR_D1PPRE_HCLK (0 << RCC_D1CFGR_D1PPRE_SHIFT) /* 0xx: */ -# define RCC_D1CFGR_D1PPRE_HCLKd2 (4 << RCC_D1CFGR_D1PPRE_SHIFT) /* 100: */ -# define RCC_D1CFGR_D1PPRE_HCLKd4 (5 << RCC_D1CFGR_D1PPRE_SHIFT) /* 101: */ -# define RCC_D1CFGR_D1PPRE_HCLKd8 (6 << RCC_D1CFGR_D1PPRE_SHIFT) /* 110: */ -# define RCC_D1CFGR_D1PPRE_HCLKd16 (7 << RCC_D1CFGR_D1PPRE_SHIFT) /* 111: */ +# define RCC_D1CFGR_D1PPRE_HCLK (0 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLKd2 (4 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLKd4 (5 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLKd8 (6 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLKd16 (7 << RCC_D1CFGR_D1PPRE_SHIFT) /* Bit 7: Reserved */ #define RCC_D1CFGR_D1CPRE_SHIFT (8) /* Bits 8-11: D1 domain Core prescaler */ #define RCC_D1CFGR_D1CPRE_MASK (15 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLK (0 << RCC_D1CFGR_D1CPRE_SHIFT) /* 0xxx: */ -# define RCC_D1CFGR_D1CPRE_SYSCLKd2 (8 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1000: */ -# define RCC_D1CFGR_D1CPRE_SYSCLKd4 (9 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1001: */ -# define RCC_D1CFGR_D1CPRE_SYSCLKd8 (10 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1010: */ -# define RCC_D1CFGR_D1CPRE_SYSCLKd16 (11 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1011: */ -# define RCC_D1CFGR_D1CPRE_SYSCLKd64 (12 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1100: */ -# define RCC_D1CFGR_D1CPRE_SYSCLKd128 (13 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1101: */ -# define RCC_D1CFGR_D1CPRE_SYSCLKd256 (14 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1110: */ -# define RCC_D1CFGR_D1CPRE_SYSCLKd512 (15 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1111: */ +# define RCC_D1CFGR_D1CPRE_SYSCLK (0 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd2 (8 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd4 (9 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd8 (10 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd16 (11 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd64 (12 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd128 (13 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd256 (14 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd512 (15 << RCC_D1CFGR_D1CPRE_SHIFT) /* Bits 12-31: Reserved */ /* Bit definitions for RCC_D2CFGR */ - /* Bits 0-3: Reserved */ -#define RCC_D2CFGR_D2PPRE1_SHIFT (4) /* Bits 4-6: D2 domain APB1 prescaler */ + /* Bits 0-3: Reserved */ +#define RCC_D2CFGR_D2PPRE1_SHIFT (4) /* Bits 4-6: D2 domain APB1 prescaler */ #define RCC_D2CFGR_D2PPRE1_MASK (7 << RCC_D2CFGR_D2PPRE1_SHIFT) -# define RCC_D2CFGR_D2PPRE1_HCLK (0 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 0xx: */ -# define RCC_D2CFGR_D2PPRE1_HCLKd2 (4 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 100: */ -# define RCC_D2CFGR_D2PPRE1_HCLKd4 (5 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 101: */ -# define RCC_D2CFGR_D2PPRE1_HCLKd8 (6 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 110: */ -# define RCC_D2CFGR_D2PPRE1_HCLKd16 (7 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 111: */ - /* Bit 7: Reserved */ -#define RCC_D2CFGR_D2PPRE2_SHIFT (8) /* Bits 8-10: D2 domain APB2 prescaler */ +# define RCC_D2CFGR_D2PPRE1_HCLK (0 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLKd2 (4 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLKd4 (5 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLKd8 (6 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLKd16 (7 << RCC_D2CFGR_D2PPRE1_SHIFT) + /* Bit 7: Reserved */ +#define RCC_D2CFGR_D2PPRE2_SHIFT (8) /* Bits 8-10: D2 domain APB2 prescaler */ #define RCC_D2CFGR_D2PPRE2_MASK (7 << RCC_D2CFGR_D2PPRE2_SHIFT) -# define RCC_D2CFGR_D2PPRE2_HCLK (0 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 0xx: */ -# define RCC_D2CFGR_D2PPRE2_HCLKd2 (4 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 100: */ -# define RCC_D2CFGR_D2PPRE2_HCLKd4 (5 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 101: */ -# define RCC_D2CFGR_D2PPRE2_HCLKd8 (6 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 110: */ -# define RCC_D2CFGR_D2PPRE2_HCLKd16 (7 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 111: */ - /* Bits 11-31: Reserved */ +# define RCC_D2CFGR_D2PPRE2_HCLK (0 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLKd2 (4 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLKd4 (5 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLKd8 (6 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLKd16 (7 << RCC_D2CFGR_D2PPRE2_SHIFT) + /* Bits 11-31: Reserved */ /* Bit definitions for RCC_D3CFGR */ /* Bits 0-3: Reserved */ #define RCC_D3CFGR_D3PPRE_SHIFT (4) /* Bits 4-6: D3 domain APB4 prescaler */ #define RCC_D3CFGR_D3PPRE_MASK (7 << RCC_D3CFGR_D3PPRE_SHIFT) -# define RCC_D3CFGR_D3PPRE_HCLK (0 << RCC_D3CFGR_D3PPRE_SHIFT) /* 0xx: */ -# define RCC_D3CFGR_D3PPRE_HCLKd2 (4 << RCC_D3CFGR_D3PPRE_SHIFT) /* 100: */ -# define RCC_D3CFGR_D3PPRE_HCLKd4 (5 << RCC_D3CFGR_D3PPRE_SHIFT) /* 101: */ -# define RCC_D3CFGR_D3PPRE_HCLKd8 (6 << RCC_D3CFGR_D3PPRE_SHIFT) /* 110: */ -# define RCC_D3CFGR_D3PPRE_HCLKd16 (7 << RCC_D3CFGR_D3PPRE_SHIFT) /* 111: */ +# define RCC_D3CFGR_D3PPRE_HCLK (0 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLKd2 (4 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLKd4 (5 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLKd8 (6 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLKd16 (7 << RCC_D3CFGR_D3PPRE_SHIFT) /* Bits 7-31: Reserved */ /* Bit definitions for RCC_PLLCKSELR register */ -#define RCC_PLLCKSELR_PLLSRC_SHIFT (0) /* Bit 0: */ +#define RCC_PLLCKSELR_PLLSRC_SHIFT (0) /* Bit 0: */ #define RCC_PLLCKSELR_PLLSRC_MASK (0x3 << RCC_PLLCKSELR_PLLSRC_SHIFT) #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_MASK -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /* HSI source clock selected */ -#define RCC_PLLCKSELR_PLLSRC_CSI ((uint32_t)0x00000001) /* CSI source clock selected */ -#define RCC_PLLCKSELR_PLLSRC_HSE ((uint32_t)0x00000002) /* HSE source clock selected */ -#define RCC_PLLCKSELR_PLLSRC_NONE ((uint32_t)0x00000003) /* No source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /* HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_CSI ((uint32_t)0x00000001) /* CSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSE ((uint32_t)0x00000002) /* HSE source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_NONE ((uint32_t)0x00000003) /* No source clock selected */ #define RCC_PLLCKSELR_DIVM1_SHIFT (4ul) -#define RCC_PLLCKSELR_DIVM1(x) ((x) << RCC_PLLCKSELR_DIVM1_SHIFT) /* Prescaler for PLL1: 1 - 63, 0 = disabled */ +#define RCC_PLLCKSELR_DIVM1(x) ((x) << RCC_PLLCKSELR_DIVM1_SHIFT) /* Prescaler for PLL1: 1 - 63, 0 = disabled */ #define RCC_PLLCKSELR_DIVM2_SHIFT (12ul) -#define RCC_PLLCKSELR_DIVM2(x) ((x) << RCC_PLLCKSELR_DIVM2_SHIFT) /* Prescaler for PLL2: 1 - 63, 0 = disabled */ +#define RCC_PLLCKSELR_DIVM2(x) ((x) << RCC_PLLCKSELR_DIVM2_SHIFT) /* Prescaler for PLL2: 1 - 63, 0 = disabled */ #define RCC_PLLCKSELR_DIVM3_SHIFT (20ul) -#define RCC_PLLCKSELR_DIVM3(x) ((x) << RCC_PLLCKSELR_DIVM3_SHIFT) /* Prescaler for PLL3: 1 - 63, 0 = disabled */ +#define RCC_PLLCKSELR_DIVM3(x) ((x) << RCC_PLLCKSELR_DIVM3_SHIFT) /* Prescaler for PLL3: 1 - 63, 0 = disabled */ /* Bit definition for RCC_PLLCFGR register */ @@ -368,238 +368,236 @@ #define RCC_PLLCFGR_PLL1FRACEN_SHIFT (0ul) #define RCC_PLLCFGR_PLL1FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL1FRACEN_SHIFT) -#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_MASK /* Fractional latch enable */ +#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_MASK /* Fractional latch enable */ #define RCC_PLLCFGR_PLL1VCOSEL_SHIFT (1ul) #define RCC_PLLCFGR_PLL1VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL1VCOSEL_SHIFT) -#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_MASK /* VCO frequency range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ -#define RCC_PLLCFGR_PLL1VCOSEL_WIDE (0ul) /* VCO frequency range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ -#define RCC_PLLCFGR_PLL1VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO frequency range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ +#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ +#define RCC_PLLCFGR_PLL1VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ +#define RCC_PLLCFGR_PLL1VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ #define RCC_PLLCFGR_PLL1RGE_SHIFT (2ul) #define RCC_PLLCFGR_PLL1RGE_MASK (0x3ul << RCC_PLLCFGR_PLL1RGE_SHIFT) #define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_MASK -#define RCC_PLLCFGR_PLL1RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ -#define RCC_PLLCFGR_PLL1RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ -#define RCC_PLLCFGR_PLL1RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ -#define RCC_PLLCFGR_PLL1RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ +#define RCC_PLLCFGR_PLL1RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ +#define RCC_PLLCFGR_PLL1RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ +#define RCC_PLLCFGR_PLL1RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ +#define RCC_PLLCFGR_PLL1RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ -#define RCC_PLLCFGR_PLL2FRACEN_SHIFT (0ul) +#define RCC_PLLCFGR_PLL2FRACEN_SHIFT (4ul) #define RCC_PLLCFGR_PLL2FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL2FRACEN_SHIFT) -#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_MASK /* Fractional latch enable */ -#define RCC_PLLCFGR_PLL2VCOSEL_SHIFT (1ul) +#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_MASK /* Fractional latch enable */ +#define RCC_PLLCFGR_PLL2VCOSEL_SHIFT (5ul) #define RCC_PLLCFGR_PLL2VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL2VCOSEL_SHIFT) -#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_MASK /* VCO frequency range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ -#define RCC_PLLCFGR_PLL2VCOSEL_WIDE (0ul) /* VCO frequency range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ -#define RCC_PLLCFGR_PLL2VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO frequency range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ -#define RCC_PLLCFGR_PLL2RGE_SHIFT (2ul) +#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ +#define RCC_PLLCFGR_PLL2VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ +#define RCC_PLLCFGR_PLL2VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ +#define RCC_PLLCFGR_PLL2RGE_SHIFT (6ul) #define RCC_PLLCFGR_PLL2RGE_MASK (0x3ul << RCC_PLLCFGR_PLL2RGE_SHIFT) #define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_MASK -#define RCC_PLLCFGR_PLL2RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ -#define RCC_PLLCFGR_PLL2RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ -#define RCC_PLLCFGR_PLL2RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ -#define RCC_PLLCFGR_PLL2RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ +#define RCC_PLLCFGR_PLL2RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ +#define RCC_PLLCFGR_PLL2RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ +#define RCC_PLLCFGR_PLL2RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ +#define RCC_PLLCFGR_PLL2RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ -#define RCC_PLLCFGR_PLL3FRACEN_SHIFT (0ul) +#define RCC_PLLCFGR_PLL3FRACEN_SHIFT (8ul) #define RCC_PLLCFGR_PLL3FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL3FRACEN_SHIFT) -#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_MASK /* Fractional latch enable */ -#define RCC_PLLCFGR_PLL3VCOSEL_SHIFT (1ul) +#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_MASK /* Fractional latch enable */ +#define RCC_PLLCFGR_PLL3VCOSEL_SHIFT (9ul) #define RCC_PLLCFGR_PLL3VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL3VCOSEL_SHIFT) -#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_MASK /* VCO frequency range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ -#define RCC_PLLCFGR_PLL3VCOSEL_WIDE (0ul) /* VCO frequency range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ -#define RCC_PLLCFGR_PLL3VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO frequency range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ -#define RCC_PLLCFGR_PLL3RGE_SHIFT (2ul) +#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ +#define RCC_PLLCFGR_PLL3VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ +#define RCC_PLLCFGR_PLL3VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ +#define RCC_PLLCFGR_PLL3RGE_SHIFT (10ul) #define RCC_PLLCFGR_PLL3RGE_MASK (0x3ul << RCC_PLLCFGR_PLL3RGE_SHIFT) #define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_MASK -#define RCC_PLLCFGR_PLL3RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ -#define RCC_PLLCFGR_PLL3RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ -#define RCC_PLLCFGR_PLL3RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ -#define RCC_PLLCFGR_PLL3RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ +#define RCC_PLLCFGR_PLL3RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ +#define RCC_PLLCFGR_PLL3RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ +#define RCC_PLLCFGR_PLL3RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ +#define RCC_PLLCFGR_PLL3RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ #define RCC_PLLCFGR_DIVP1EN_SHIFT (16ul) -#define RCC_PLLCFGR_DIVP1EN_MASK (0x1ul << RCC_PLLCFGR_DIVP1EN_SHIFT) /* 0x00010000 */ +#define RCC_PLLCFGR_DIVP1EN_MASK (0x1ul << RCC_PLLCFGR_DIVP1EN_SHIFT) #define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_MASK #define RCC_PLLCFGR_DIVQ1EN_SHIFT (17ul) -#define RCC_PLLCFGR_DIVQ1EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ1EN_SHIFT) /* 0x00020000 */ +#define RCC_PLLCFGR_DIVQ1EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ1EN_SHIFT) #define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_MASK #define RCC_PLLCFGR_DIVR1EN_SHIFT (18ul) -#define RCC_PLLCFGR_DIVR1EN_MASK (0x1ul << RCC_PLLCFGR_DIVR1EN_SHIFT) /* 0x00040000 */ +#define RCC_PLLCFGR_DIVR1EN_MASK (0x1ul << RCC_PLLCFGR_DIVR1EN_SHIFT) #define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_MASK #define RCC_PLLCFGR_DIVP2EN_SHIFT (19ul) -#define RCC_PLLCFGR_DIVP2EN_MASK (0x1ul << RCC_PLLCFGR_DIVP2EN_SHIFT) /* 0x00080000 */ +#define RCC_PLLCFGR_DIVP2EN_MASK (0x1ul << RCC_PLLCFGR_DIVP2EN_SHIFT) #define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_MASK #define RCC_PLLCFGR_DIVQ2EN_SHIFT (20ul) -#define RCC_PLLCFGR_DIVQ2EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ2EN_SHIFT) /* 0x00100000 */ +#define RCC_PLLCFGR_DIVQ2EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ2EN_SHIFT) #define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_MASK #define RCC_PLLCFGR_DIVR2EN_SHIFT (21ul) -#define RCC_PLLCFGR_DIVR2EN_MASK (0x1ul << RCC_PLLCFGR_DIVR2EN_SHIFT) /* 0x00200000 */ +#define RCC_PLLCFGR_DIVR2EN_MASK (0x1ul << RCC_PLLCFGR_DIVR2EN_SHIFT) #define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_MASK #define RCC_PLLCFGR_DIVP3EN_SHIFT (22ul) -#define RCC_PLLCFGR_DIVP3EN_MASK (0x1ul << RCC_PLLCFGR_DIVP3EN_SHIFT) /* 0x00400000 */ +#define RCC_PLLCFGR_DIVP3EN_MASK (0x1ul << RCC_PLLCFGR_DIVP3EN_SHIFT) #define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_MASK #define RCC_PLLCFGR_DIVQ3EN_SHIFT (23ul) -#define RCC_PLLCFGR_DIVQ3EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ3EN_SHIFT) /* 0x00800000 */ +#define RCC_PLLCFGR_DIVQ3EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ3EN_SHIFT) #define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_MASK #define RCC_PLLCFGR_DIVR3EN_SHIFT (24ul) -#define RCC_PLLCFGR_DIVR3EN_MASK (0x1ul << RCC_PLLCFGR_DIVR3EN_SHIFT) /* 0x01000000 */ +#define RCC_PLLCFGR_DIVR3EN_MASK (0x1ul << RCC_PLLCFGR_DIVR3EN_SHIFT) #define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_MASK /* Bit definitions for RCC_PLL1DIVR register */ #define RCC_PLL1DIVR_N1_SHIFT (0ul) -#define RCC_PLL1DIVR_N1(x) (((x) - 1) << RCC_PLL1DIVR_N1_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ +#define RCC_PLL1DIVR_N1(x) (((x) - 1) << RCC_PLL1DIVR_N1_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ #define RCC_PLL1DIVR_P1_SHIFT (9ul) -#define RCC_PLL1DIVR_P1(x) (((x) - 1) << RCC_PLL1DIVR_P1_SHIFT) /* DIVP division factor: 2 - 128, must be even */ +#define RCC_PLL1DIVR_P1(x) (((x) - 1) << RCC_PLL1DIVR_P1_SHIFT) /* DIVP division factor: 2 - 128, must be even */ #define RCC_PLL1DIVR_Q1_SHIFT (16ul) -#define RCC_PLL1DIVR_Q1(x) (((x) - 1) << RCC_PLL1DIVR_Q1_SHIFT) /* DIVQ division factor: 2 - 128 */ +#define RCC_PLL1DIVR_Q1(x) (((x) - 1) << RCC_PLL1DIVR_Q1_SHIFT) /* DIVQ division factor: 2 - 128 */ #define RCC_PLL1DIVR_R1_SHIFT (24ul) -#define RCC_PLL1DIVR_R1(x) (((x) - 1) << RCC_PLL1DIVR_R1_SHIFT) /* DIVR division factor: 2 - 128 */ +#define RCC_PLL1DIVR_R1(x) (((x) - 1) << RCC_PLL1DIVR_R1_SHIFT) /* DIVR division factor: 2 - 128 */ /* Bit definitions for RCC_PLL1FRACR register */ #define RCC_PLL1FRACR_FRACN1_SHIFT (3ul) -#define RCC_PLL1FRACR_FRACN1_MASK (0x1FFFul << RCC_PLL1FRACR_FRACN1_SHIFT) /* 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACN1_MASK (0x1FFFul << RCC_PLL1FRACR_FRACN1_SHIFT) #define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_MASK /* Bit definitions for RCC_PLL2DIVR register */ #define RCC_PLL2DIVR_N2_SHIFT (0ul) -#define RCC_PLL2DIVR_N2(x) (((x) - 1) << RCC_PLL2DIVR_N2_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ +#define RCC_PLL2DIVR_N2(x) (((x) - 1) << RCC_PLL2DIVR_N2_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ #define RCC_PLL2DIVR_P2_SHIFT (9ul) -#define RCC_PLL2DIVR_P2(x) (((x) - 1) << RCC_PLL2DIVR_P2_SHIFT) /* DIVP division factor: 2 - 128 */ +#define RCC_PLL2DIVR_P2(x) (((x) - 1) << RCC_PLL2DIVR_P2_SHIFT) /* DIVP division factor: 2 - 128 */ #define RCC_PLL2DIVR_Q2_SHIFT (16ul) -#define RCC_PLL2DIVR_Q2(x) (((x) - 1) << RCC_PLL2DIVR_Q2_SHIFT) /* DIVQ division factor: 2 - 128 */ +#define RCC_PLL2DIVR_Q2(x) (((x) - 1) << RCC_PLL2DIVR_Q2_SHIFT) /* DIVQ division factor: 2 - 128 */ #define RCC_PLL2DIVR_R2_SHIFT (24ul) -#define RCC_PLL2DIVR_R2(x) (((x) - 1) << RCC_PLL2DIVR_R2_SHIFT) /* DIVR division factor: 2 - 128 */ +#define RCC_PLL2DIVR_R2(x) (((x) - 1) << RCC_PLL2DIVR_R2_SHIFT) /* DIVR division factor: 2 - 128 */ /* Bit definitions for RCC_PLL2FRACR register */ #define RCC_PLL2FRACR_FRACN2_SHIFT (3ul) -#define RCC_PLL2FRACR_FRACN2_MASK (0x1FFFul << RCC_PLL2FRACR_FRACN2_SHIFT) /* 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACN2_MASK (0x1FFFul << RCC_PLL2FRACR_FRACN2_SHIFT) #define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_MASK /* Bit definitions for RCC_PLL3DIVR register */ #define RCC_PLL3DIVR_N3_SHIFT (0ul) -#define RCC_PLL3DIVR_N3(x) (((x) - 1) << RCC_PLL3DIVR_N3_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ +#define RCC_PLL3DIVR_N3(x) (((x) - 1) << RCC_PLL3DIVR_N3_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ #define RCC_PLL3DIVR_P3_SHIFT (9ul) -#define RCC_PLL3DIVR_P3(x) (((x) - 1) << RCC_PLL3DIVR_P3_SHIFT) /* DIVP division factor: 2 - 128 */ +#define RCC_PLL3DIVR_P3(x) (((x) - 1) << RCC_PLL3DIVR_P3_SHIFT) /* DIVP division factor: 2 - 128 */ #define RCC_PLL3DIVR_Q3_SHIFT (16ul) -#define RCC_PLL3DIVR_Q3(x) (((x) - 1) << RCC_PLL3DIVR_Q3_SHIFT) /* DIVQ division factor: 2 - 128 */ +#define RCC_PLL3DIVR_Q3(x) (((x) - 1) << RCC_PLL3DIVR_Q3_SHIFT) /* DIVQ division factor: 2 - 128 */ #define RCC_PLL3DIVR_R3_SHIFT (24ul) -#define RCC_PLL3DIVR_R3(x) (((x) - 1) << RCC_PLL3DIVR_R3_SHIFT) /* DIVR division factor: 2 - 128 */ +#define RCC_PLL3DIVR_R3(x) (((x) - 1) << RCC_PLL3DIVR_R3_SHIFT) /* DIVR division factor: 2 - 128 */ /* Bit definitions for RCC_PLL3FRACR register */ #define RCC_PLL3FRACR_FRACN3_SHIFT (3ul) -#define RCC_PLL3FRACR_FRACN3_MASK (0x1FFFul << RCC_PLL3FRACR_FRACN3_SHIFT) /* 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_MASK +#define RCC_PLL3FRACR_FRACN3_MASK (0x1FFFul << RCC_PLL3FRACR_FRACN3_SHIFT) +#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_MASK /* Bit definitions for RCC_D1CCIPR register */ -#define RCC_D1CCIPR_FMCSEL_SHIFT (0) /* Bits 0-1: */ +#define RCC_D1CCIPR_FMCSEL_SHIFT (0) /* Bits 0-1: */ #define RCC_D1CCIPR_FMCSEL_MASK (3 << RCC_D1CCIPR_FMCSEL_SHIFT) -# define RCC_D1CCIPR_FMCSEL_HCLK (0 << RCC_D1CCIPR_FMCSEL_SHIFT) /* 00: */ -# define RCC_D1CCIPR_FMCSEL_PLL1 (1 << RCC_D1CCIPR_FMCSEL_SHIFT) /* 01: */ -# define RCC_D1CCIPR_FMCSEL_PLL2 (2 << RCC_D1CCIPR_FMCSEL_SHIFT) /* 10: */ -# define RCC_D1CCIPR_FMCSEL_PER (3 << RCC_D1CCIPR_FMCSEL_SHIFT) /* 11: */ - /* Bits 2-3: Reserved */ -#define RCC_D1CCIPR_QSPISEL_SHIFT (4) /* Bits 4-5: */ +# define RCC_D1CCIPR_FMCSEL_HCLK (0 << RCC_D1CCIPR_FMCSEL_SHIFT) +# define RCC_D1CCIPR_FMCSEL_PLL1 (1 << RCC_D1CCIPR_FMCSEL_SHIFT) +# define RCC_D1CCIPR_FMCSEL_PLL2 (2 << RCC_D1CCIPR_FMCSEL_SHIFT) +# define RCC_D1CCIPR_FMCSEL_PER (3 << RCC_D1CCIPR_FMCSEL_SHIFT) + /* Bits 2-3: Reserved */ +#define RCC_D1CCIPR_QSPISEL_SHIFT (4) /* Bits 4-5: */ #define RCC_D1CCIPR_QSPISEL_MASK (3 << RCC_D1CCIPR_QSPISEL_SHIFT) -# define RCC_D1CCIPR_QSPISEL_HCLK (0 << RCC_D1CCIPR_QSPISEL_SHIFT) /* 00: */ -# define RCC_D1CCIPR_QSPISEL_PLL1 (1 << RCC_D1CCIPR_QSPISEL_SHIFT) /* 01: */ -# define RCC_D1CCIPR_QSPISEL_PLL2 (2 << RCC_D1CCIPR_QSPISEL_SHIFT) /* 10: */ -# define RCC_D1CCIPR_QSPISEL_PER (3 << RCC_D1CCIPR_QSPISEL_SHIFT) /* 11: */ - /* Bits 6-15: Reserved */ +# define RCC_D1CCIPR_QSPISEL_HCLK (0 << RCC_D1CCIPR_QSPISEL_SHIFT) +# define RCC_D1CCIPR_QSPISEL_PLL1 (1 << RCC_D1CCIPR_QSPISEL_SHIFT) +# define RCC_D1CCIPR_QSPISEL_PLL2 (2 << RCC_D1CCIPR_QSPISEL_SHIFT) +# define RCC_D1CCIPR_QSPISEL_PER (3 << RCC_D1CCIPR_QSPISEL_SHIFT) + /* Bits 6-15: Reserved */ #define RCC_D1CCIPR_SDMMC_SHIFT (16) /* Bit 16: */ #define RCC_D1CCIPR_SDMMC_MASK (1 << RCC_D1CCIPR_SDMMC_SHIFT) -# define RCC_D1CCIPR_SDMMC_PLL1 (0 << RCC_D1CCIPR_SDMMC_SHIFT) /* 0: */ -# define RCC_D1CCIPR_SDMMC_PLL2 (1 << RCC_D1CCIPR_SDMMC_SHIFT) /* 1: */ - /* Bits 17-27: Reserved */ - /* Bits 17-27: Reserved */ +# define RCC_D1CCIPR_SDMMC_PLL1 (0 << RCC_D1CCIPR_SDMMC_SHIFT) +# define RCC_D1CCIPR_SDMMC_PLL2 (1 << RCC_D1CCIPR_SDMMC_SHIFT) + /* Bits 17-27: Reserved */ #define RCC_D1CCIPR_CKPERSEL_SHIFT (28) /* Bits 28-29: */ #define RCC_D1CCIPR_CKPERSEL_MASK (3 << RCC_D1CCIPR_CKPERSEL_SHIFT) -# define RCC_D1CCIPR_CKPERSEL_HSI (0 << RCC_D1CCIPR_CKPERSEL_SHIFT) /* 00: */ -# define RCC_D1CCIPR_CKPERSEL_CSI (1 << RCC_D1CCIPR_CKPERSEL_SHIFT) /* 01: */ -# define RCC_D1CCIPR_CKPERSEL_HSE (2 << RCC_D1CCIPR_CKPERSEL_SHIFT) /* 10: */ - /* 11: Reserved */ +# define RCC_D1CCIPR_CKPERSEL_HSI (0 << RCC_D1CCIPR_CKPERSEL_SHIFT) +# define RCC_D1CCIPR_CKPERSEL_CSI (1 << RCC_D1CCIPR_CKPERSEL_SHIFT) +# define RCC_D1CCIPR_CKPERSEL_HSE (2 << RCC_D1CCIPR_CKPERSEL_SHIFT) /* Bits 30-31: Reserved */ /* Bit definitions for RCC_D2CCIP1R register */ -#define RCC_D2CCIP1R_SAI1SEL_SHIFT (0) /* Bits 0-2 */ +#define RCC_D2CCIP1R_SAI1SEL_SHIFT (0) /* Bits 0-2 */ #define RCC_D2CCIP1R_SAI1SEL_MASK (7 << RCC_D2CCIP1R_SAI1SEL_MASK) -# define RCC_D2CCIP1R_SAI1SEL_PLL1 (0 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 000 */ -# define RCC_D2CCIP1R_SAI1SEL_PLL2 (1 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 001 */ -# define RCC_D2CCIP1R_SAI1SEL_PLL3 (2 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 010 */ -# define RCC_D2CCIP1R_SAI1SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 011 */ -# define RCC_D2CCIP1R_SAI1SEL_PER (4 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 100 */ - /* Bits 3-5: Reserved */ -#define RCC_D2CCIP1R_SAI23SEL_SHIFT (6) /* Bits 6-8 */ +# define RCC_D2CCIP1R_SAI1SEL_PLL1 (0 << RCC_D2CCIP1R_SAI1SEL_SHIFT) +# define RCC_D2CCIP1R_SAI1SEL_PLL2 (1 << RCC_D2CCIP1R_SAI1SEL_SHIFT) +# define RCC_D2CCIP1R_SAI1SEL_PLL3 (2 << RCC_D2CCIP1R_SAI1SEL_SHIFT) +# define RCC_D2CCIP1R_SAI1SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI1SEL_SHIFT) +# define RCC_D2CCIP1R_SAI1SEL_PER (4 << RCC_D2CCIP1R_SAI1SEL_SHIFT) + /* Bits 3-5: Reserved */ +#define RCC_D2CCIP1R_SAI23SEL_SHIFT (6) /* Bits 6-8 */ #define RCC_D2CCIP1R_SAI23SEL_MASK (7 << RCC_D2CCIP1R_SAI23SEL_SHIFT) -# define RCC_D2CCIP1R_SAI23SEL_PLL1 (0 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 000 */ -# define RCC_D2CCIP1R_SAI23SEL_PLL2 (1 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 001 */ -# define RCC_D2CCIP1R_SAI23SEL_PLL3 (2 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 010 */ -# define RCC_D2CCIP1R_SAI23SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 011 */ -# define RCC_D2CCIP1R_SAI23SEL_PER (4 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 100 */ - /* Bits 9-11: Reserved */ -#define RCC_D2CCIP1R_SPI123SEL_SHIFT (12) /* Bits 12-14 */ +# define RCC_D2CCIP1R_SAI23SEL_PLL1 (0 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_PLL2 (1 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_PLL3 (2 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_PER (4 << RCC_D2CCIP1R_SAI23SEL_SHIFT) + /* Bits 9-11: Reserved */ +#define RCC_D2CCIP1R_SPI123SEL_SHIFT (12) /* Bits 12-14 */ #define RCC_D2CCIP1R_SPI123SEL_MASK (7 << RCC_D2CCIP1R_SPI123SEL_SHIFT) -# define RCC_D2CCIP1R_SPI123SEL_PLL1 (0 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 000 */ -# define RCC_D2CCIP1R_SPI123SEL_PLL2 (1 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 001 */ -# define RCC_D2CCIP1R_SPI123SEL_PLL3 (2 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 010 */ -# define RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 011 */ -# define RCC_D2CCIP1R_SPI123SEL_PER (4 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 100 */ - /* Bit 15: Reserved */ -#define RCC_D2CCIP1R_SPI45SEL_SHIFT (16) /* Bits 16-18 */ +# define RCC_D2CCIP1R_SPI123SEL_PLL1 (0 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_PLL2 (1 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_PLL3 (2 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_PER (4 << RCC_D2CCIP1R_SPI123SEL_SHIFT) + /* Bit 15: Reserved */ +#define RCC_D2CCIP1R_SPI45SEL_SHIFT (16) /* Bits 16-18 */ #define RCC_D2CCIP1R_SPI45SEL_MASK (7 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_APB (0 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 000 */ -# define RCC_D2CCIP1R_SPI45SEL_PLL2 (1 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 001 */ -# define RCC_D2CCIP1R_SPI45SEL_PLL3 (2 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 010 */ -# define RCC_D2CCIP1R_SPI45SEL_HSI (3 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 011 */ -# define RCC_D2CCIP1R_SPI45SEL_CSI (4 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 100 */ -# define RCC_D2CCIP1R_SPI45SEL_HSE (5 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 101 */ - /* Bit 19: Reserved */ -#define RCC_D2CCIP1R_SPDIFSEL_SHIFT (20) /* Bits 20-21 */ +# define RCC_D2CCIP1R_SPI45SEL_APB (0 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_PLL2 (1 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_PLL3 (2 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_HSI (3 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_CSI (4 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_HSE (5 << RCC_D2CCIP1R_SPI45SEL_SHIFT) + /* Bit 19: Reserved */ +#define RCC_D2CCIP1R_SPDIFSEL_SHIFT (20) /* Bits 20-21 */ #define RCC_D2CCIP1R_SPDIFSEL_MASK (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) -# define RCC_D2CCIP1R_SPDIFSEL_PLL1 (0 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 00 */ -# define RCC_D2CCIP1R_SPDIFSEL_PLL2 (1 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 01 */ -# define RCC_D2CCIP1R_SPDIFSEL_PLL3 (2 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 10 */ -# define RCC_D2CCIP1R_SPDIFSEL_HSI (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 11 */ - /* Bits 22-23: Reserved */ -#define RCC_D2CCIP1R_DFSDM1SEL_SHIFT (24) /* Bit 24 */ +# define RCC_D2CCIP1R_SPDIFSEL_PLL1 (0 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) +# define RCC_D2CCIP1R_SPDIFSEL_PLL2 (1 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) +# define RCC_D2CCIP1R_SPDIFSEL_PLL3 (2 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) +# define RCC_D2CCIP1R_SPDIFSEL_HSI (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) + /* Bits 22-23: Reserved */ +#define RCC_D2CCIP1R_DFSDM1SEL_SHIFT (24) /* Bit 24 */ #define RCC_D2CCIP1R_DFSDM1SEL_MASK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) -# define RCC_D2CCIP1R_DFSDM1SEL_PCLK2 (0 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) /* 0 */ -# define RCC_D2CCIP1R_DFSDM1SEL_SYSCLK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) /* 1 */ - /* Bits 25-27: Reserved */ -#define RCC_D2CCIP1R_FDCANSEL_SHIFT (28) /* Bits 28-29 */ +# define RCC_D2CCIP1R_DFSDM1SEL_PCLK2 (0 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) +# define RCC_D2CCIP1R_DFSDM1SEL_SYSCLK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) + /* Bits 25-27: Reserved */ +#define RCC_D2CCIP1R_FDCANSEL_SHIFT (28) /* Bits 28-29 */ #define RCC_D2CCIP1R_FDCANSEL_MASK (3 << RCC_D2CCIP1R_FDCANSEL_SHIFT) -# define RCC_D2CCIP1R_FDCANSEL_HSE (0 << RCC_D2CCIP1R_FDCANSEL_SHIFT) /* 00 */ -# define RCC_D2CCIP1R_FDCANSEL_PLL1 (1 << RCC_D2CCIP1R_FDCANSEL_SHIFT) /* 01 */ -# define RCC_D2CCIP1R_FDCANSEL_PLL2 (2 << RCC_D2CCIP1R_FDCANSEL_SHIFT) /* 10 */ - /* Bit 30: Reserved */ -#define RCC_D2CCIP1R_SWPSEL_SHIFT (31) /* Bit 31 */ +# define RCC_D2CCIP1R_FDCANSEL_HSE (0 << RCC_D2CCIP1R_FDCANSEL_SHIFT) +# define RCC_D2CCIP1R_FDCANSEL_PLL1 (1 << RCC_D2CCIP1R_FDCANSEL_SHIFT) +# define RCC_D2CCIP1R_FDCANSEL_PLL2 (2 << RCC_D2CCIP1R_FDCANSEL_SHIFT) + /* Bit 30: Reserved */ +#define RCC_D2CCIP1R_SWPSEL_SHIFT (31) /* Bit 31 */ #define RCC_D2CCIP1R_SWPSEL_MASK (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) -# define RCC_D2CCIP1R_SWPSEL_PCLK (0 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* 0 */ -# define RCC_D2CCIP1R_SWPSEL_HSI (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* 1 */ +# define RCC_D2CCIP1R_SWPSEL_PCLK (0 << RCC_D2CCIP1R_SWPSEL_SHIFT) +# define RCC_D2CCIP1R_SWPSEL_HSI (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* Bit definitions for RCC_D2CCIP2R register */ -#define RCC_D2CCIP2R_USART234578SEL_SHIFT (0) /* Bits 0-2 */ +#define RCC_D2CCIP2R_USART234578SEL_SHIFT (0) /* Bits 0-2 */ # define RCC_D2CCIP2R_USART234578SEL_MASK (7 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -#define RCC_D2CCIP2R_USART16SEL_SHIFT (3) /* Bits 3-5 */ +#define RCC_D2CCIP2R_USART16SEL_SHIFT (3) /* Bits 3-5 */ # define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT) - /* Bits 6-7: Reserved */ -#define RCC_D2CCIP2R_RNGSEL_SHIFT (8) /* Bits 8-9 */ + /* Bits 6-7: Reserved */ +#define RCC_D2CCIP2R_RNGSEL_SHIFT (8) /* Bits 8-9 */ # define RCC_D2CCIP2R_RNGSEL_MASK (3 << RCC_D2CCIP2R_RNGSEL_SHIFT) - /* Bits 10-11: Reserved */ + /* Bits 10-11: Reserved */ #define RCC_D2CCIP2R_I2C123SEL_SHIFT (12) /* Bits 12-13 */ #define RCC_D2CCIP2R_I2C123SEL_MASK (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) -# define RCC_D2CCIP2R_I2C123SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 00 */ -# define RCC_D2CCIP2R_I2C123SEL_PLL3 (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 01 */ -# define RCC_D2CCIP2R_I2C123SEL_HSI (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 10 */ -# define RCC_D2CCIP2R_I2C123SEL_CSI (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 11 */ - /* Bits 14-19: Reserved */ +# define RCC_D2CCIP2R_I2C123SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C123SEL_SHIFT) +# define RCC_D2CCIP2R_I2C123SEL_PLL3 (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) +# define RCC_D2CCIP2R_I2C123SEL_HSI (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) +# define RCC_D2CCIP2R_I2C123SEL_CSI (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) + /* Bits 14-19: Reserved */ #define RCC_D2CCIP2R_USBSEL_SHIFT (20) /* Bits 20-21 */ # define RCC_D2CCIP2R_USBSEL_MASK (3 << RCC_D2CCIP2R_USBSEL_SHIFT) # define RCC_D2CCIP2R_USBSEL_DISABLE (0 << RCC_D2CCIP2R_USBSEL_SHIFT) @@ -608,78 +606,80 @@ # define RCC_D2CCIP2R_USBSEL_HSI48 (3 << RCC_D2CCIP2R_USBSEL_SHIFT) #define RCC_D2CCIP2R_CECSEL_SHIFT (22) /* Bits 22-23 */ # define RCC_D2CCIP2R_CECSEL_MASK (3 << RCC_D2CCIP2R_CECSEL_SHIFT) - /* Bits 24-27: Reserved */ + /* Bits 24-27: Reserved */ #define RCC_D2CCIP2R_LPTIM1SEL_SHIFT (28) /* Bits 28-30 */ # define RCC_D2CCIP2R_LPTIM1SEL_MASK (3 << RCC_D2CCIP2R_LPTIM1SEL_SHIFT) - /* Bit 31: Reserved */ + /* Bit 31: Reserved */ /* Bit definitions for RCC_D3CCIPR register */ #define RCC_D3CCIPR_LPUART1SEL_SHIFT (0) /* Bits 0-2: LPUART1 kernel clock source selection */ #define RCC_D3CCIPR_LPUART1SEL_MASK (7 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_PCLK (0 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 000 */ -# define RCC_D3CCIPR_LPUART1SEL_PLL2 (1 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 001 */ -# define RCC_D3CCIPR_LPUART1SEL_PLL3 (2 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 010 */ -# define RCC_D3CCIPR_LPUART1SEL_HSI (3 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 011 */ -# define RCC_D3CCIPR_LPUART1SEL_CSI (4 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 100 */ -# define RCC_D3CCIPR_LPUART1SEL_LSE (5 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* 101 */ +# define RCC_D3CCIPR_LPUART1SEL_PCLK (0 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_PLL2 (1 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_PLL3 (2 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_HSI (3 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_CSI (4 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_LSE (5 << RCC_D3CCIPR_LPUART1SEL_SHIFT) /* Bits 3-7: Reserved */ #define RCC_D3CCIPR_I2C4SEL_SHIFT (8) /* Bits 8-9: I2C4 kernel clock source selection */ #define RCC_D3CCIPR_I2C4SEL_MASK (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) -# define RCC_D3CCIPR_I2C4SEL_PCLK4 (0 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 00 */ -# define RCC_D3CCIPR_I2C4SEL_PLL3 (1 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 01 */ -# define RCC_D3CCIPR_I2C4SEL_HSI (2 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 10 */ -# define RCC_D3CCIPR_I2C4SEL_CSI (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 11 */ +# define RCC_D3CCIPR_I2C4SEL_PCLK4 (0 << RCC_D3CCIPR_I2C4SEL_SHIFT) +# define RCC_D3CCIPR_I2C4SEL_PLL3 (1 << RCC_D3CCIPR_I2C4SEL_SHIFT) +# define RCC_D3CCIPR_I2C4SEL_HSI (2 << RCC_D3CCIPR_I2C4SEL_SHIFT) +# define RCC_D3CCIPR_I2C4SEL_CSI (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) #define RCC_D3CCIPR_LPTIM2SEL_SHIFT (10) /* Bits 10-12: LPTIM2 kernel clock source selection */ #define RCC_D3CCIPR_LPTIM2SEL_MASK (7 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 000 */ -# define RCC_D3CCIPR_LPTIM2SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 001 */ -# define RCC_D3CCIPR_LPTIM2SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 010 */ -# define RCC_D3CCIPR_LPTIM2SEL_LSE (3 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 011 */ -# define RCC_D3CCIPR_LPTIM2SEL_LSI (4 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 100 */ -# define RCC_D3CCIPR_LPTIM2SEL_PER (5 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) /* 101 */ +# define RCC_D3CCIPR_LPTIM2SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_LSE (3 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_LSI (4 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_PER (5 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) #define RCC_D3CCIPR_LPTIM345SEL_SHIFT (13) /* Bits 13-15: LPTIM3,4,5 kernel clock source selection */ #define RCC_D3CCIPR_LPTIM345SEL_MASK (7 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 000 */ -# define RCC_D3CCIPR_LPTIM345SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 001 */ -# define RCC_D3CCIPR_LPTIM345SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 010 */ -# define RCC_D3CCIPR_LPTIM345SEL_LSE (3 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 011 */ -# define RCC_D3CCIPR_LPTIM345SEL_LSI (4 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 100 */ -# define RCC_D3CCIPR_LPTIM345SEL_PER (5 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) /* 101 */ +# define RCC_D3CCIPR_LPTIM345SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_LSE (3 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_LSI (4 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_PER (5 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) #define RCC_D3CCIPR_ADCSEL_SHIFT (16) /* Bits 16-17: SAR ADC kernel clock source selection */ #define RCC_D3CCIPR_ADCSEL_MASK (3 << RCC_D3CCIPR_ADCSEL_SHIFT) -# define RCC_D3CCIPR_ADCSEL_PLL2 (0 << RCC_D3CCIPR_ADCSEL_SHIFT) /* 00 */ -# define RCC_D3CCIPR_ADCSEL_PLL3 (1 << RCC_D3CCIPR_ADCSEL_SHIFT) /* 01 */ -# define RCC_D3CCIPR_ADCSEL_PER (2 << RCC_D3CCIPR_ADCSEL_SHIFT) /* 10 */ +# define RCC_D3CCIPR_ADCSEL_PLL2 (0 << RCC_D3CCIPR_ADCSEL_SHIFT) +# define RCC_D3CCIPR_ADCSEL_PLL3 (1 << RCC_D3CCIPR_ADCSEL_SHIFT) +# define RCC_D3CCIPR_ADCSEL_PER (2 << RCC_D3CCIPR_ADCSEL_SHIFT) /* Bits 18-20: Reserved */ #define RCC_D3CCIPR_SAI4ASEL_SHIFT (21) /* Bits 21-23: Sub-Block A of SAI4 kernel clock source selection */ #define RCC_D3CCIPR_SAI4ASEL_MASK (7 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -# define RCC_D3CCIPR_SAI4ASEL_PLL1 (0 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 000 */ -# define RCC_D3CCIPR_SAI4ASEL_PLL2 (1 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 001 */ -# define RCC_D3CCIPR_SAI4ASEL_PLL3 (2 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 010 */ -# define RCC_D3CCIPR_SAI4ASEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 011 */ -# define RCC_D3CCIPR_SAI4ASEL_PER (4 << RCC_D3CCIPR_SAI4ASEL_SHIFT) /* 100 */ +# define RCC_D3CCIPR_SAI4ASEL_PLL1 (0 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_PLL2 (1 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_PLL3 (2 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_PER (4 << RCC_D3CCIPR_SAI4ASEL_SHIFT) #define RCC_D3CCIPR_SAI4BSEL_SHIFT (24) /* Bits 24-26: Sub-Block B of SAI4 kernel clock source selection */ #define RCC_D3CCIPR_SAI4BSEL_MASK (7 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -# define RCC_D3CCIPR_SAI4BSEL_PLL1 (0 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 000 */ -# define RCC_D3CCIPR_SAI4BSEL_PLL2 (1 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 001 */ -# define RCC_D3CCIPR_SAI4BSEL_PLL3 (2 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 010 */ -# define RCC_D3CCIPR_SAI4BSEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 011 */ -# define RCC_D3CCIPR_SAI4BSEL_PER (4 << RCC_D3CCIPR_SAI4BSEL_SHIFT) /* 100 */ +# define RCC_D3CCIPR_SAI4BSEL_PLL1 (0 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_PLL2 (1 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_PLL3 (2 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_PER (4 << RCC_D3CCIPR_SAI4BSEL_SHIFT) #define RCC_D3CCIPR_SPI6SEL_SHIFT (28) /* Bits 28-30: SPI6 kernel clock source selection */ #define RCC_D3CCIPR_SPI6SEL_MASK (7 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_PCLK4 (0 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 000 */ -# define RCC_D3CCIPR_SPI6SEL_PLL2 (1 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 001 */ -# define RCC_D3CCIPR_SPI6SEL_PLL3 (2 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 010 */ -# define RCC_D3CCIPR_SPI6SEL_HSI (3 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 011 */ -# define RCC_D3CCIPR_SPI6SEL_CSI (4 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 100 */ -# define RCC_D3CCIPR_SPI6SEL_HSE (5 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* 101 */ +# define RCC_D3CCIPR_SPI6SEL_PCLK4 (0 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_PLL2 (1 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_PLL3 (2 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_HSI (3 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_CSI (4 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_HSE (5 << RCC_D3CCIPR_SPI6SEL_SHIFT) /* Bit 31: Reserved */ -/* ... */ /* TODO: CIER */ + /* TODO: CIFR */ + /* TODO: CICR */ + /* TODO: BDCR */ /* Bit definitions for RCC_CSR register */ @@ -699,210 +699,214 @@ /* AHB1 peripheral reset register */ -#define RCC_AHB1RSTR_DMA1RST (1 << 0) /* RCC AHB1RSTR: DMA1RST */ -#define RCC_AHB1RSTR_DMA2RST (1 << 1) /* RCC AHB1RSTR: DMA2RST */ -#define RCC_AHB1RSTR_ADC12RST (1 << 5) /* RCC AHB1RSTR: ADC12RST */ - /* Bits 6-14: Reserved */ -#define RCC_AHB1RSTR_ETH1MACRST (1 << 15) /* RCC AHB1RSTR: ETH1MACRST */ - /* Bits 16-24: Reserved */ -#define RCC_AHB1RSTR_OTGHSRST (1 << 25) /* RCC AHB1RSTR: OTGHSRST */ - /* Bit 26: Reserved */ -#define RCC_AHB1RSTR_OTGFSRST (1 << 27) /* RCC AHB1RSTR: OTGFSRST */ - /* Bits 28-31: Reserved */ +#define RCC_AHB1RSTR_DMA1RST (1 << 0) /* RCC AHB1RSTR: DMA1RST */ +#define RCC_AHB1RSTR_DMA2RST (1 << 1) /* RCC AHB1RSTR: DMA2RST */ +#define RCC_AHB1RSTR_ADC12RST (1 << 5) /* RCC AHB1RSTR: ADC12RST */ + /* Bits 6-14: Reserved */ +#define RCC_AHB1RSTR_ETH1MACRST (1 << 15) /* RCC AHB1RSTR: ETH1MACRST */ + /* Bits 16-24: Reserved */ +#define RCC_AHB1RSTR_OTGHSRST (1 << 25) /* RCC AHB1RSTR: OTGHSRST */ + /* Bit 26: Reserved */ +#define RCC_AHB1RSTR_OTGFSRST (1 << 27) /* RCC AHB1RSTR: OTGFSRST */ + /* Bits 28-31: Reserved */ /* AHB2 peripheral reset register */ -#define RCC_AHB2RSTR_CAMITFRST (1 << 0) /* RCC AHB2RSTR: CAMITFRST */ - /* Bits 1-3: Reserved */ -#define RCC_AHB2RSTR_CRYPTRST (1 << 4) /* RCC AHB2RSTR: CRYPTRST */ -#define RCC_AHB2RSTR_HASHRST (1 << 5) /* RCC AHB2RSTR: HASHRST */ -#define RCC_AHB2RSTR_RNGRST (1 << 6) /* RCC AHB2RSTR: RNGRST */ - /* Bits 7-8: Reserved */ -#define RCC_AHB2RSTR_SDMMC2RST (1 << 9) /* RCC AHB2RSTR: SDMMC2RST */ - /* Bits 10-31: Reserved */ +#define RCC_AHB2RSTR_CAMITFRST (1 << 0) /* RCC AHB2RSTR: CAMITFRST */ + /* Bits 1-3: Reserved */ +#define RCC_AHB2RSTR_CRYPTRST (1 << 4) /* RCC AHB2RSTR: CRYPTRST */ +#define RCC_AHB2RSTR_HASHRST (1 << 5) /* RCC AHB2RSTR: HASHRST */ +#define RCC_AHB2RSTR_RNGRST (1 << 6) /* RCC AHB2RSTR: RNGRST */ + /* Bits 7-8: Reserved */ +#define RCC_AHB2RSTR_SDMMC2RST (1 << 9) /* RCC AHB2RSTR: SDMMC2RST */ + /* Bits 10-31: Reserved */ /* AHB4 peripheral reset register */ -#define RCC_AHB4RSTR_GPIOARST (1 << 0) /* RCC AHB4RSTR: GPIOARST */ -#define RCC_AHB4RSTR_GPIOBRST (1 << 1) /* RCC AHB4RSTR: GPIOBRST */ -#define RCC_AHB4RSTR_GPIOCRST (1 << 2) /* RCC AHB4RSTR: GPIOCRST */ -#define RCC_AHB4RSTR_GPIODRST (1 << 3) /* RCC AHB4RSTR: GPIODRST */ -#define RCC_AHB4RSTR_GPIOERST (1 << 4) /* RCC AHB4RSTR: GPIOERST */ -#define RCC_AHB4RSTR_GPIOFRST (1 << 5) /* RCC AHB4RSTR: GPIOFRST */ -#define RCC_AHB4RSTR_GPIOGRST (1 << 6) /* RCC AHB4RSTR: GPIOGRST */ -#define RCC_AHB4RSTR_GPIOHRST (1 << 7) /* RCC AHB4RSTR: GPIOHRST */ -#define RCC_AHB4RSTR_GPIOIRST (1 << 8) /* RCC AHB4RSTR: GPIOIRST */ -#define RCC_AHB4RSTR_GPIOJRST (1 << 9) /* RCC AHB4RSTR: GPIOJRST */ -#define RCC_AHB4RSTR_GPIOKRST (1 << 10) /* RCC AHB4RSTR: GPIOKRST */ - /* Bits 11-18: Reserved */ -#define RCC_AHB4RSTR_CRCRST (1 << 19) /* RCC AHB4RSTR: CRCRST */ - /* Bit 20: Reserved */ -#define RCC_AHB4RSTR_BDMARST (1 << 21) /* RCC AHB4RSTR: BDMARST */ - /* Bits 22-23: Reserved */ -#define RCC_AHB4RSTR_ADC3RST (1 << 24) /* RCC AHB4RSTR: ADC3RST */ -#define RCC_AHB4RSTR_HSEMRST (1 << 25) /* RCC AHB4RSTR: HSEMRST */ - /* Bits 26-31: Reserved */ +#define RCC_AHB4RSTR_GPIOARST (1 << 0) /* RCC AHB4RSTR: GPIOARST */ +#define RCC_AHB4RSTR_GPIOBRST (1 << 1) /* RCC AHB4RSTR: GPIOBRST */ +#define RCC_AHB4RSTR_GPIOCRST (1 << 2) /* RCC AHB4RSTR: GPIOCRST */ +#define RCC_AHB4RSTR_GPIODRST (1 << 3) /* RCC AHB4RSTR: GPIODRST */ +#define RCC_AHB4RSTR_GPIOERST (1 << 4) /* RCC AHB4RSTR: GPIOERST */ +#define RCC_AHB4RSTR_GPIOFRST (1 << 5) /* RCC AHB4RSTR: GPIOFRST */ +#define RCC_AHB4RSTR_GPIOGRST (1 << 6) /* RCC AHB4RSTR: GPIOGRST */ +#define RCC_AHB4RSTR_GPIOHRST (1 << 7) /* RCC AHB4RSTR: GPIOHRST */ +#define RCC_AHB4RSTR_GPIOIRST (1 << 8) /* RCC AHB4RSTR: GPIOIRST */ +#define RCC_AHB4RSTR_GPIOJRST (1 << 9) /* RCC AHB4RSTR: GPIOJRST */ +#define RCC_AHB4RSTR_GPIOKRST (1 << 10) /* RCC AHB4RSTR: GPIOKRST */ + /* Bits 11-18: Reserved */ +#define RCC_AHB4RSTR_CRCRST (1 << 19) /* RCC AHB4RSTR: CRCRST */ + /* Bit 20: Reserved */ +#define RCC_AHB4RSTR_BDMARST (1 << 21) /* RCC AHB4RSTR: BDMARST */ + /* Bits 22-23: Reserved */ +#define RCC_AHB4RSTR_ADC3RST (1 << 24) /* RCC AHB4RSTR: ADC3RST */ +#define RCC_AHB4RSTR_HSEMRST (1 << 25) /* RCC AHB4RSTR: HSEMRST */ + /* Bits 26-31: Reserved */ /* APB3 peripheral reset register */ - /* Bits 0-2: Reserved */ -#define RCC_APB3RSTR_LTDCRST (1 << 3) /* RCC APB3RSTR: LTDCRST */ - /* Bits 4-31: Reserved */ + /* Bits 0-2: Reserved */ +#define RCC_APB3RSTR_LTDCRST (1 << 3) /* RCC APB3RSTR: LTDCRST */ + /* Bits 4-31: Reserved */ /* APB3 L peripheral reset register */ -#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* RCC APB1LRSTR: TIM2RST */ -#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* RCC APB1LRSTR: TIM3RST */ -#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* RCC APB1LRSTR: TIM4RST */ -#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* RCC APB1LRSTR: TIM5RST */ -#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* RCC APB1LRSTR: TIM6RST */ -#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* RCC APB1LRSTR: TIM7RST */ -#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* RCC APB1LRSTR: TIM12RST */ -#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* RCC APB1LRSTR: TIM13RST */ -#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* RCC APB1LRSTR: TIM14RST */ -#define RCC_APB1LRSTR_LPTIM1RST (1 << 9) /* RCC APB1LRSTR: LPTIM1RST */ - /* Bits 10-13: Reserved */ -#define RCC_APB1LRSTR_SPI2RST (1 << 14) /* RCC APB1LRSTR: SPI2RST */ -#define RCC_APB1LRSTR_SPI3RST (1 << 15) /* RCC APB1LRSTR: SPI3RST */ -#define RCC_APB1LRSTR_SPDIFRXRST (1 << 16) /* RCC APB1LRSTR: SPDIFRXRST */ -#define RCC_APB1LRSTR_USART2RST (1 << 17) /* RCC APB1LRSTR: USART2RST */ -#define RCC_APB1LRSTR_USART3RST (1 << 18) /* RCC APB1LRSTR: USART3RST */ -#define RCC_APB1LRSTR_UART4RST (1 << 19) /* RCC APB1LRSTR: UART4RST */ -#define RCC_APB1LRSTR_UART5RST (1 << 20) /* RCC APB1LRSTR: UART5RST */ -#define RCC_APB1LRSTR_I2C1RST (1 << 21) /* RCC APB1LRSTR: I2C1RST */ -#define RCC_APB1LRSTR_I2C2RST (1 << 22) /* RCC APB1LRSTR: I2C2RST */ -#define RCC_APB1LRSTR_I2C3RST (1 << 23) /* RCC APB1LRSTR: I2C3RST */ - /* Bits 24-26: Reserved */ -#define RCC_APB1LRSTR_HDMICECRST (1 << 27) /* RCC APB1LRSTR: HDMICECRST */ - /* Bit 28: Reserved */ -#define RCC_APB1LRSTR_DAC1RST (1 << 29) /* RCC APB1LRSTR: DAC1RST */ -#define RCC_APB1LRSTR_UART7RST (1 << 30) /* RCC APB1LRSTR: UART7RST */ -#define RCC_APB1LRSTR_UART8RST (1 << 31) /* RCC APB1LRSTR: UART8RST */ +#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* RCC APB1LRSTR: TIM2RST */ +#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* RCC APB1LRSTR: TIM3RST */ +#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* RCC APB1LRSTR: TIM4RST */ +#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* RCC APB1LRSTR: TIM5RST */ +#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* RCC APB1LRSTR: TIM6RST */ +#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* RCC APB1LRSTR: TIM7RST */ +#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* RCC APB1LRSTR: TIM12RST */ +#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* RCC APB1LRSTR: TIM13RST */ +#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* RCC APB1LRSTR: TIM14RST */ +#define RCC_APB1LRSTR_LPTIM1RST (1 << 9) /* RCC APB1LRSTR: LPTIM1RST */ + /* Bits 10-13: Reserved */ +#define RCC_APB1LRSTR_SPI2RST (1 << 14) /* RCC APB1LRSTR: SPI2RST */ +#define RCC_APB1LRSTR_SPI3RST (1 << 15) /* RCC APB1LRSTR: SPI3RST */ +#define RCC_APB1LRSTR_SPDIFRXRST (1 << 16) /* RCC APB1LRSTR: SPDIFRXRST */ +#define RCC_APB1LRSTR_USART2RST (1 << 17) /* RCC APB1LRSTR: USART2RST */ +#define RCC_APB1LRSTR_USART3RST (1 << 18) /* RCC APB1LRSTR: USART3RST */ +#define RCC_APB1LRSTR_UART4RST (1 << 19) /* RCC APB1LRSTR: UART4RST */ +#define RCC_APB1LRSTR_UART5RST (1 << 20) /* RCC APB1LRSTR: UART5RST */ +#define RCC_APB1LRSTR_I2C1RST (1 << 21) /* RCC APB1LRSTR: I2C1RST */ +#define RCC_APB1LRSTR_I2C2RST (1 << 22) /* RCC APB1LRSTR: I2C2RST */ +#define RCC_APB1LRSTR_I2C3RST (1 << 23) /* RCC APB1LRSTR: I2C3RST */ + /* Bits 24-26: Reserved */ +#define RCC_APB1LRSTR_HDMICECRST (1 << 27) /* RCC APB1LRSTR: HDMICECRST */ + /* Bit 28: Reserved */ +#define RCC_APB1LRSTR_DAC1RST (1 << 29) /* RCC APB1LRSTR: DAC1RST */ +#define RCC_APB1LRSTR_UART7RST (1 << 30) /* RCC APB1LRSTR: UART7RST */ +#define RCC_APB1LRSTR_UART8RST (1 << 31) /* RCC APB1LRSTR: UART8RST */ /* APB1 H peripheral reset register */ - /* Bit 0: Reserved */ -#define RCC_APB1HRSTR_CRSRST (1 << 1) /* RCC APB1HRSTR: CRSRST */ -#define RCC_APB1HRSTR_SWPRST (1 << 2) /* RCC APB1HRSTR: SWPRST */ - /* Bit 3: Reserved */ -#define RCC_APB1HRSTR_OPAMPRST (1 << 4) /* RCC APB1HRSTR: OPAMPRST*/ -#define RCC_APB1HRSTR_MDIOSRST (1 << 5) /* RCC APB1HRSTR: MDIOSRST */ - /* Bits 6-7: Reserved */ -#define RCC_APB1HRSTR_FDCANRST (1 << 8) /* RCC APB1HRSTR: FDCANRST*/ - /* Bits 9-31: Reserved */ + /* Bit 0: Reserved */ +#define RCC_APB1HRSTR_CRSRST (1 << 1) /* RCC APB1HRSTR: CRSRST */ +#define RCC_APB1HRSTR_SWPRST (1 << 2) /* RCC APB1HRSTR: SWPRST */ + +/* Bit 3: Reserved */ + +#define RCC_APB1HRSTR_OPAMPRST (1 << 4) /* RCC APB1HRSTR: OPAMPRST*/ +#define RCC_APB1HRSTR_MDIOSRST (1 << 5) /* RCC APB1HRSTR: MDIOSRST */ + /* Bits 6-7: Reserved */ +#define RCC_APB1HRSTR_FDCANRST (1 << 8) /* RCC APB1HRSTR: FDCANRST*/ + +/* Bits 9-31: Reserved */ /* APB2 peripheral reset register */ -#define RCC_APB2RSTR_TIM1RST (1 << 0) /* RCC APB2RSTR: TIM1RST */ -#define RCC_APB2RSTR_TIM8RST (1 << 1) /* RCC APB2RSTR: TIM8RST */ -#define RCC_APB2RSTR_USART1RST (1 << 4) /* RCC APB2RSTR: USART1RST */ -#define RCC_APB2RSTR_USART6RST (1 << 5) /* RCC APB2RSTR: USART6RST */ -#define RCC_APB2RSTR_SPI1RST (1 << 12) /* RCC APB2RSTR: SPI1RST */ -#define RCC_APB2RSTR_SPI4RST (1 << 13) /* RCC APB2RSTR: SPI4RST */ -#define RCC_APB2RSTR_TIM15RST (1 << 16) /* RCC APB2RSTR: TIM15RST */ -#define RCC_APB2RSTR_TIM16RST (1 << 17) /* RCC APB2RSTR: TIM16RST */ -#define RCC_APB2RSTR_TIM17RST (1 << 18) /* RCC APB2RSTR: TIM17RST */ -#define RCC_APB2RSTR_SPI5RST (1 << 20) /* RCC APB2RSTR: SPI5RST */ -#define RCC_APB2RSTR_SAI1RST (1 << 22) /* RCC APB2RSTR: SAI1RST */ -#define RCC_APB2RSTR_SAI2RST (1 << 23) /* RCC APB2RSTR: SAI2RST */ -#define RCC_APB2RSTR_SAI3RST (1 << 24) /* RCC APB2RSTR: SAI3RST */ -#define RCC_APB2RSTR_DFSDM1RST (1 << 28) /* RCC APB2RSTR: DFSDM1RST */ -#define RCC_APB2RSTR_HRTIMRST (1 << 29) /* RCC APB2RSTR: HRTIMRST */ +#define RCC_APB2RSTR_TIM1RST (1 << 0) /* RCC APB2RSTR: TIM1RST */ +#define RCC_APB2RSTR_TIM8RST (1 << 1) /* RCC APB2RSTR: TIM8RST */ +#define RCC_APB2RSTR_USART1RST (1 << 4) /* RCC APB2RSTR: USART1RST */ +#define RCC_APB2RSTR_USART6RST (1 << 5) /* RCC APB2RSTR: USART6RST */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) /* RCC APB2RSTR: SPI1RST */ +#define RCC_APB2RSTR_SPI4RST (1 << 13) /* RCC APB2RSTR: SPI4RST */ +#define RCC_APB2RSTR_TIM15RST (1 << 16) /* RCC APB2RSTR: TIM15RST */ +#define RCC_APB2RSTR_TIM16RST (1 << 17) /* RCC APB2RSTR: TIM16RST */ +#define RCC_APB2RSTR_TIM17RST (1 << 18) /* RCC APB2RSTR: TIM17RST */ +#define RCC_APB2RSTR_SPI5RST (1 << 20) /* RCC APB2RSTR: SPI5RST */ +#define RCC_APB2RSTR_SAI1RST (1 << 22) /* RCC APB2RSTR: SAI1RST */ +#define RCC_APB2RSTR_SAI2RST (1 << 23) /* RCC APB2RSTR: SAI2RST */ +#define RCC_APB2RSTR_SAI3RST (1 << 24) /* RCC APB2RSTR: SAI3RST */ +#define RCC_APB2RSTR_DFSDM1RST (1 << 28) /* RCC APB2RSTR: DFSDM1RST */ +#define RCC_APB2RSTR_HRTIMRST (1 << 29) /* RCC APB2RSTR: HRTIMRST */ /* APB4 peripheral reset register */ -#define RCC_APB4RSTR_SYSCFGRST (1 << 1) /* RCC APB4RSTR: SYSCFGRST */ -#define RCC_APB4RSTR_LPUART1RST (1 << 3) /* RCC APB4RSTR: LPUART1RST */ -#define RCC_APB4RSTR_SPI6RST (1 << 5) /* RCC APB4RSTR: SPI6RST */ -#define RCC_APB4RSTR_I2C4RST (1 << 7) /* RCC APB4RSTR: I2C4RST */ -#define RCC_APB4RSTR_LPTIM2RST (1 << 9) /* RCC APB4RSTR: LPTIM2RST */ -#define RCC_APB4RSTR_LPTIM3RST (1 << 10) /* RCC APB4RSTR: LPTIM3RST */ -#define RCC_APB4RSTR_LPTIM4RST (1 << 11) /* RCC APB4RSTR: LPTIM4RST */ -#define RCC_APB4RSTR_LPTIM5RST (1 << 12) /* RCC APB4RSTR: LPTIM5RST */ -#define RCC_APB4RSTR_COMP12RST (1 << 14) /* RCC APB4RSTR: COMP12RST */ -#define RCC_APB4RSTR_VREFRST (1 << 15) /* RCC APB4RSTR: VREFRST */ -#define RCC_APB4RSTR_SAI4RST (1 << 21) /* RCC APB4RSTR: SAI4RST */ +#define RCC_APB4RSTR_SYSCFGRST (1 << 1) /* RCC APB4RSTR: SYSCFGRST */ +#define RCC_APB4RSTR_LPUART1RST (1 << 3) /* RCC APB4RSTR: LPUART1RST */ +#define RCC_APB4RSTR_SPI6RST (1 << 5) /* RCC APB4RSTR: SPI6RST */ +#define RCC_APB4RSTR_I2C4RST (1 << 7) /* RCC APB4RSTR: I2C4RST */ +#define RCC_APB4RSTR_LPTIM2RST (1 << 9) /* RCC APB4RSTR: LPTIM2RST */ +#define RCC_APB4RSTR_LPTIM3RST (1 << 10) /* RCC APB4RSTR: LPTIM3RST */ +#define RCC_APB4RSTR_LPTIM4RST (1 << 11) /* RCC APB4RSTR: LPTIM4RST */ +#define RCC_APB4RSTR_LPTIM5RST (1 << 12) /* RCC APB4RSTR: LPTIM5RST */ +#define RCC_APB4RSTR_COMP12RST (1 << 14) /* RCC APB4RSTR: COMP12RST */ +#define RCC_APB4RSTR_VREFRST (1 << 15) /* RCC APB4RSTR: VREFRST */ +#define RCC_APB4RSTR_SAI4RST (1 << 21) /* RCC APB4RSTR: SAI4RST */ /* RCC Global Control register */ -#define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */ +#define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */ /* TODO: D3 Autonomous mode register */ /* RCC Reset Status register */ - /* Bits 0-15: Reserved */ -#define RCC_RSR_RMVF (1 << 16) /* Bit 16: Remove reset flag */ -#define RCC_RSR_CPURSTF (1 << 17) /* Bit 17: CPU reset flag */ - /* Bit 18: Reserved */ -#define RCC_RSR_D1RSTF (1 << 19) /* Bit 19: D1 domain power switch reset flag */ -#define RCC_RSR_D2RSTF (1 << 20) /* Bit 20: D2 domain power switch reset flag */ -#define RCC_RSR_BORRSTF (1 << 21) /* Bit 21: BOR reset flag */ -#define RCC_RSR_PINRSTF (1 << 22) /* Bit 22: Pin reset flag */ -#define RCC_RSR_PORRSTF (1 << 23) /* Bit 23: POR/PDR reset flag */ -#define RCC_RSR_SFTRSTF (1 << 24) /* Bit 24: System reset from CPU flag */ - /* Bit 25: Reserved */ -#define RCC_RSR_IWDG1RSTF (1 << 26) /* Bit 26: Independent watchdog reset flag */ - /* Bit 27: Reserved */ -#define RCC_RSR_WWDG1RSTF (1 << 28) /* Bit 28: Window watchdog reset flag */ - /* Bit 29: Reserved */ -#define RCC_RSR_LPWRRSTF (1 << 30) /* Bit 30: Reset due to illegal D1 DStandby or CPU Cstop flag */ - /* Bit 31: Reserved */ + /* Bits 0-15: Reserved */ +#define RCC_RSR_RMVF (1 << 16) /* Bit 16: Remove reset flag */ +#define RCC_RSR_CPURSTF (1 << 17) /* Bit 17: CPU reset flag */ + /* Bit 18: Reserved */ +#define RCC_RSR_D1RSTF (1 << 19) /* Bit 19: D1 domain power switch reset flag */ +#define RCC_RSR_D2RSTF (1 << 20) /* Bit 20: D2 domain power switch reset flag */ +#define RCC_RSR_BORRSTF (1 << 21) /* Bit 21: BOR reset flag */ +#define RCC_RSR_PINRSTF (1 << 22) /* Bit 22: Pin reset flag */ +#define RCC_RSR_PORRSTF (1 << 23) /* Bit 23: POR/PDR reset flag */ +#define RCC_RSR_SFTRSTF (1 << 24) /* Bit 24: System reset from CPU flag */ + /* Bit 25: Reserved */ +#define RCC_RSR_IWDG1RSTF (1 << 26) /* Bit 26: Independent watchdog reset flag */ + /* Bit 27: Reserved */ +#define RCC_RSR_WWDG1RSTF (1 << 28) /* Bit 28: Window watchdog reset flag */ + /* Bit 29: Reserved */ +#define RCC_RSR_LPWRRSTF (1 << 30) /* Bit 30: Reset due to illegal D1 DStandby or CPU Cstop flag */ + /* Bit 31: Reserved */ /* AHB3 Peripheral Clock enable register */ -#define RCC_AHB3ENR_MDMAEN (1 << 0) /* RCC AHB3ENR: MDMAEN */ -#define RCC_AHB3ENR_DMA2DEN (1 << 4) /* RCC AHB3ENR: DMA2DEN */ -#define RCC_AHB3ENR_JPGDECEN (1 << 5) /* RCC AHB3ENR: JPGDECEN */ -#define RCC_AHB3ENR_FMCEN (1 << 12) /* RCC AHB3ENR: FMCEN */ -#define RCC_AHB3ENR_QSPIEN (1 << 14) /* RCC AHB3ENR: QSPIEN */ -#define RCC_AHB3ENR_SDMMC1EN (1 << 16) /* RCC AHB3ENR: SDMMC1EN */ +#define RCC_AHB3ENR_MDMAEN (1 << 0) /* RCC AHB3ENR: MDMAEN */ +#define RCC_AHB3ENR_DMA2DEN (1 << 4) /* RCC AHB3ENR: DMA2DEN */ +#define RCC_AHB3ENR_JPGDECEN (1 << 5) /* RCC AHB3ENR: JPGDECEN */ +#define RCC_AHB3ENR_FMCEN (1 << 12) /* RCC AHB3ENR: FMCEN */ +#define RCC_AHB3ENR_QSPIEN (1 << 14) /* RCC AHB3ENR: QSPIEN */ +#define RCC_AHB3ENR_SDMMC1EN (1 << 16) /* RCC AHB3ENR: SDMMC1EN */ + /* AHB1 Peripheral Clock enable register */ -#define RCC_AHB1ENR_DMA1EN (1 << 0) /* RCC AHB1ENR: DMA1EN */ -#define RCC_AHB1ENR_DMA2EN (1 << 1) /* RCC AHB1ENR: DMA2EN */ -#define RCC_AHB1ENR_ADC12EN (1 << 5) /* RCC AHB1ENR: ADC12EN */ -#define RCC_AHB1ENR_ETH1MACEN (1 << 15) /* RCC AHB1ENR: ETH1MACEN */ -#define RCC_AHB1ENR_ETH1TXEN (1 << 16) /* RCC AHB1ENR: ETH1TXEN */ -#define RCC_AHB1ENR_ETH1RXEN (1 << 17) /* RCC AHB1ENR: ETH1RXEN */ -#define RCC_AHB1ENR_OTGHSEN (1 << 25) /* RCC AHB1ENR: OTGHSEN */ -#define RCC_AHB1ENR_OTGHSULPIEN (1 << 26) /* RCC AHB1ENR: OTGHSULPIEN */ -#define RCC_AHB1ENR_OTGFSEN (1 << 27) /* RCC AHB1ENR: OTGFSEN */ +#define RCC_AHB1ENR_DMA1EN (1 << 0) /* RCC AHB1ENR: DMA1EN */ +#define RCC_AHB1ENR_DMA2EN (1 << 1) /* RCC AHB1ENR: DMA2EN */ +#define RCC_AHB1ENR_ADC12EN (1 << 5) /* RCC AHB1ENR: ADC12EN */ +#define RCC_AHB1ENR_ETH1MACEN (1 << 15) /* RCC AHB1ENR: ETH1MACEN */ +#define RCC_AHB1ENR_ETH1TXEN (1 << 16) /* RCC AHB1ENR: ETH1TXEN */ +#define RCC_AHB1ENR_ETH1RXEN (1 << 17) /* RCC AHB1ENR: ETH1RXEN */ +#define RCC_AHB1ENR_OTGHSEN (1 << 25) /* RCC AHB1ENR: OTGHSEN */ +#define RCC_AHB1ENR_OTGHSULPIEN (1 << 26) /* RCC AHB1ENR: OTGHSULPIEN */ +#define RCC_AHB1ENR_OTGFSEN (1 << 27) /* RCC AHB1ENR: OTGFSEN */ /* AHB2 Peripheral Clock enable register */ -#define RCC_AHB2ENR_CAMITFEN (1 << 0) /* RCC AHB2ENR: CAMITFEN */ -#define RCC_AHB2ENR_CRYPTEN (1 << 4) /* RCC AHB2ENR: CRYPTEN */ -#define RCC_AHB2ENR_HASHEN (1 << 5) /* RCC AHB2ENR: HASHEN */ -#define RCC_AHB2ENR_RNGEN (1 << 6) /* RCC AHB2ENR: RNGEN */ -#define RCC_AHB2ENR_SDMMC2EN (1 << 9) /* RCC AHB2ENR: SDMMC2EN */ -#define RCC_AHB2ENR_SRAM1EN (1 << 29) /* RCC AHB2ENR: SRAM1EN */ -#define RCC_AHB2ENR_SRAM2EN (1 << 30) /* RCC AHB2ENR: SRAM2EN */ -#define RCC_AHB2ENR_SRAM3EN (1 << 31) /* RCC AHB2ENR: SRAM3EN */ +#define RCC_AHB2ENR_CAMITFEN (1 << 0) /* RCC AHB2ENR: CAMITFEN */ +#define RCC_AHB2ENR_CRYPTEN (1 << 4) /* RCC AHB2ENR: CRYPTEN */ +#define RCC_AHB2ENR_HASHEN (1 << 5) /* RCC AHB2ENR: HASHEN */ +#define RCC_AHB2ENR_RNGEN (1 << 6) /* RCC AHB2ENR: RNGEN */ +#define RCC_AHB2ENR_SDMMC2EN (1 << 9) /* RCC AHB2ENR: SDMMC2EN */ +#define RCC_AHB2ENR_SRAM1EN (1 << 29) /* RCC AHB2ENR: SRAM1EN */ +#define RCC_AHB2ENR_SRAM2EN (1 << 30) /* RCC AHB2ENR: SRAM2EN */ +#define RCC_AHB2ENR_SRAM3EN (1 << 31) /* RCC AHB2ENR: SRAM3EN */ /* AHB4 Peripheral Clock enable register */ -#define RCC_AHB4ENR_GPIOAEN (1 << 0) /* RCC AHB4ENR: GPIOAEN */ -#define RCC_AHB4ENR_GPIOBEN (1 << 1) /* RCC AHB4ENR: GPIOBEN */ -#define RCC_AHB4ENR_GPIOCEN (1 << 2) /* RCC AHB4ENR: GPIOCEN */ -#define RCC_AHB4ENR_GPIODEN (1 << 3) /* RCC AHB4ENR: GPIODEN */ -#define RCC_AHB4ENR_GPIOEEN (1 << 4) /* RCC AHB4ENR: GPIOEEN */ -#define RCC_AHB4ENR_GPIOFEN (1 << 5) /* RCC AHB4ENR: GPIOFEN */ -#define RCC_AHB4ENR_GPIOGEN (1 << 6) /* RCC AHB4ENR: GPIOGEN */ -#define RCC_AHB4ENR_GPIOHEN (1 << 7) /* RCC AHB4ENR: GPIOHEN */ -#define RCC_AHB4ENR_GPIOIEN (1 << 8) /* RCC AHB4ENR: GPIOIEN */ -#define RCC_AHB4ENR_GPIOJEN (1 << 9) /* RCC AHB4ENR: GPIOJEN */ -#define RCC_AHB4ENR_GPIOKEN (1 << 10) /* RCC AHB4ENR: GPIOKEN */ -#define RCC_AHB4ENR_CRCEN (1 << 19) /* RCC AHB4ENR: CRCEN */ -#define RCC_AHB4ENR_BDMAEN (1 << 21) /* RCC AHB4ENR: BDMAEN and DMAMUX2 */ -#define RCC_AHB4ENR_ADC3EN (1 << 24) /* RCC AHB4ENR: ADC3EN */ -#define RCC_AHB4ENR_HSEMEN (1 << 25) /* RCC AHB4ENR: HSEMEN */ -#define RCC_AHB4ENR_BKPSRAMEN (1 << 28) /* RCC AHB4ENR: BKPRAMEN */ +#define RCC_AHB4ENR_GPIOAEN (1 << 0) /* RCC AHB4ENR: GPIOAEN */ +#define RCC_AHB4ENR_GPIOBEN (1 << 1) /* RCC AHB4ENR: GPIOBEN */ +#define RCC_AHB4ENR_GPIOCEN (1 << 2) /* RCC AHB4ENR: GPIOCEN */ +#define RCC_AHB4ENR_GPIODEN (1 << 3) /* RCC AHB4ENR: GPIODEN */ +#define RCC_AHB4ENR_GPIOEEN (1 << 4) /* RCC AHB4ENR: GPIOEEN */ +#define RCC_AHB4ENR_GPIOFEN (1 << 5) /* RCC AHB4ENR: GPIOFEN */ +#define RCC_AHB4ENR_GPIOGEN (1 << 6) /* RCC AHB4ENR: GPIOGEN */ +#define RCC_AHB4ENR_GPIOHEN (1 << 7) /* RCC AHB4ENR: GPIOHEN */ +#define RCC_AHB4ENR_GPIOIEN (1 << 8) /* RCC AHB4ENR: GPIOIEN */ +#define RCC_AHB4ENR_GPIOJEN (1 << 9) /* RCC AHB4ENR: GPIOJEN */ +#define RCC_AHB4ENR_GPIOKEN (1 << 10) /* RCC AHB4ENR: GPIOKEN */ +#define RCC_AHB4ENR_CRCEN (1 << 19) /* RCC AHB4ENR: CRCEN */ +#define RCC_AHB4ENR_BDMAEN (1 << 21) /* RCC AHB4ENR: BDMAEN and DMAMUX2 */ +#define RCC_AHB4ENR_ADC3EN (1 << 24) /* RCC AHB4ENR: ADC3EN */ +#define RCC_AHB4ENR_HSEMEN (1 << 25) /* RCC AHB4ENR: HSEMEN */ +#define RCC_AHB4ENR_BKPSRAMEN (1 << 28) /* RCC AHB4ENR: BKPRAMEN */ /* APB3 Peripheral Clock enable register */ -#define RCC_APB3ENR_LTDCEN (1 << 3) /* RCC APB3ENR: LTDCEN */ -#define RCC_APB3ENR_WWDG1EN (1 << 6) /* RCC APB3ENR: WWDG1EN */ +#define RCC_APB3ENR_LTDCEN (1 << 3) /* RCC APB3ENR: LTDCEN */ +#define RCC_APB3ENR_WWDG1EN (1 << 6) /* RCC APB3ENR: WWDG1EN */ /* APB1 L Peripheral Clock enable register */ @@ -936,215 +940,215 @@ /* APB1 H Peripheral Clock enable register */ - /* Bit 0: Reserved */ -#define RCC_APB1HENR_CRSEN (1 << 1) /* RCC APB1HENR: CRSEN */ -#define RCC_APB1HENR_SWPEN (1 << 2) /* RCC APB1HENR: SWPEN */ - /* Bit 3: Reserved */ -#define RCC_APB1HENR_OPAMPEN (1 << 4) /* RCC APB1HENR: OPAMPEN */ -#define RCC_APB1HENR_MDIOSEN (1 << 5) /* RCC APB1HENR: MDIOSEN */ - /* Bits 6-7: Reserved */ -#define RCC_APB1HENR_FDCANEN (1 << 8) /* RCC APB1HENR: FDCANEN */ - /* Bits 9-31: Reserved */ + /* Bit 0: Reserved */ +#define RCC_APB1HENR_CRSEN (1 << 1) /* RCC APB1HENR: CRSEN */ +#define RCC_APB1HENR_SWPEN (1 << 2) /* RCC APB1HENR: SWPEN */ + /* Bit 3: Reserved */ +#define RCC_APB1HENR_OPAMPEN (1 << 4) /* RCC APB1HENR: OPAMPEN */ +#define RCC_APB1HENR_MDIOSEN (1 << 5) /* RCC APB1HENR: MDIOSEN */ + /* Bits 6-7: Reserved */ +#define RCC_APB1HENR_FDCANEN (1 << 8) /* RCC APB1HENR: FDCANEN */ + /* Bits 9-31: Reserved */ /* APB2 Peripheral Clock enable register */ -#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: RCC APB2ENR: TIM1EN */ -#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: RCC APB2ENR: TIM8EN */ - /* Bits 2-3: Reserved */ -#define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: RCC APB2ENR: USART1EN */ -#define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: RCC APB2ENR: USART6EN */ - /* Bits 6-11: Reserved */ -#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: RCC APB2ENR: SPI1EN */ -#define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: RCC APB2ENR: SPI4EN */ - /* Bits 14-15: Reserved */ -#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: RCC APB2ENR: TIM15EN */ -#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: RCC APB2ENR: TIM16EN */ -#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: RCC APB2ENR: TIM17EN */ -#define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: RCC APB2ENR: SPI5EN */ - /* Bit 21: Reserved */ -#define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: RCC APB2ENR: SAI1EN */ -#define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: RCC APB2ENR: SAI2EN */ -#define RCC_APB2ENR_SAI3EN (1 << 24) /* Bit 24: RCC APB2ENR: SAI3EN */ - /* Bits 25-27: Reserved */ -#define RCC_APB2ENR_DFSDM1EN (1 << 28) /* Bit 28: RCC APB2ENR: DFSDM1EN */ -#define RCC_APB2ENR_HRTIMEN (1 << 29) /* Bit 29: RCC APB2ENR: HRTIMEN */ - /* Bits 30-31: Reserved */ +#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: RCC APB2ENR: TIM1EN */ +#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: RCC APB2ENR: TIM8EN */ + /* Bits 2-3: Reserved */ +#define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: RCC APB2ENR: USART1EN */ +#define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: RCC APB2ENR: USART6EN */ + /* Bits 6-11: Reserved */ +#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: RCC APB2ENR: SPI1EN */ +#define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: RCC APB2ENR: SPI4EN */ + /* Bits 14-15: Reserved */ +#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: RCC APB2ENR: TIM15EN */ +#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: RCC APB2ENR: TIM16EN */ +#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: RCC APB2ENR: TIM17EN */ +#define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: RCC APB2ENR: SPI5EN */ + /* Bit 21: Reserved */ +#define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: RCC APB2ENR: SAI1EN */ +#define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: RCC APB2ENR: SAI2EN */ +#define RCC_APB2ENR_SAI3EN (1 << 24) /* Bit 24: RCC APB2ENR: SAI3EN */ + /* Bits 25-27: Reserved */ +#define RCC_APB2ENR_DFSDM1EN (1 << 28) /* Bit 28: RCC APB2ENR: DFSDM1EN */ +#define RCC_APB2ENR_HRTIMEN (1 << 29) /* Bit 29: RCC APB2ENR: HRTIMEN */ + /* Bits 30-31: Reserved */ /* APB4 Peripheral Clock enable register */ - /* Bit 0: Reserved */ -#define RCC_APB4ENR_SYSCFGEN (1 << 1) /* Bit 1: RCC APB4ENR: SYSCFGEN */ - /* Bit 2: Reserved */ -#define RCC_APB4ENR_LPUART1EN (1 << 3) /* Bit 3: RCC APB4ENR: LPUART1EN */ - /* Bit 4: Reserved */ -#define RCC_APB4ENR_SPI6EN (1 << 5) /* Bit 5: RCC APB4ENR: SPI6EN */ - /* Bit 6: Reserved */ -#define RCC_APB4ENR_I2C4EN (1 << 7) /* Bit 7: RCC APB4ENR: I2C4EN */ - /* Bit 8: Reserved */ -#define RCC_APB4ENR_LPTIM2EN (1 << 9) /* Bit 9: RCC APB4ENR: LPTIM2EN */ -#define RCC_APB4ENR_LPTIM3EN (1 << 10) /* Bit 10: RCC APB4ENR: LPTIM3EN */ -#define RCC_APB4ENR_LPTIM4EN (1 << 11) /* Bit 11: RCC APB4ENR: LPTIM4EN */ -#define RCC_APB4ENR_LPTIM5EN (1 << 12) /* Bit 12: RCC APB4ENR: LPTIM5EN */ - /* Bit 13: Reserved */ -#define RCC_APB4ENR_COMP12EN (1 << 14) /* Bit 14: RCC APB4ENR: COMP12EN */ -#define RCC_APB4ENR_VREFEN (1 << 15) /* Bit 15: RCC APB4ENR: VREFEN */ -#define RCC_APB4ENR_RTCAPBEN (1 << 16) /* Bit 16: RCC APB4ENR: RTCAPBEN */ - /* Bits 17-20: Reserved */ -#define RCC_APB4ENR_SAI4EN (1 << 21) /* Bit 21: RCC APB4ENR: SAI4EN */ - /* Bit2 22-31: Reserved */ + /* Bit 0: Reserved */ +#define RCC_APB4ENR_SYSCFGEN (1 << 1) /* Bit 1: RCC APB4ENR: SYSCFGEN */ + /* Bit 2: Reserved */ +#define RCC_APB4ENR_LPUART1EN (1 << 3) /* Bit 3: RCC APB4ENR: LPUART1EN */ + /* Bit 4: Reserved */ +#define RCC_APB4ENR_SPI6EN (1 << 5) /* Bit 5: RCC APB4ENR: SPI6EN */ + /* Bit 6: Reserved */ +#define RCC_APB4ENR_I2C4EN (1 << 7) /* Bit 7: RCC APB4ENR: I2C4EN */ + /* Bit 8: Reserved */ +#define RCC_APB4ENR_LPTIM2EN (1 << 9) /* Bit 9: RCC APB4ENR: LPTIM2EN */ +#define RCC_APB4ENR_LPTIM3EN (1 << 10) /* Bit 10: RCC APB4ENR: LPTIM3EN */ +#define RCC_APB4ENR_LPTIM4EN (1 << 11) /* Bit 11: RCC APB4ENR: LPTIM4EN */ +#define RCC_APB4ENR_LPTIM5EN (1 << 12) /* Bit 12: RCC APB4ENR: LPTIM5EN */ + /* Bit 13: Reserved */ +#define RCC_APB4ENR_COMP12EN (1 << 14) /* Bit 14: RCC APB4ENR: COMP12EN */ +#define RCC_APB4ENR_VREFEN (1 << 15) /* Bit 15: RCC APB4ENR: VREFEN */ +#define RCC_APB4ENR_RTCAPBEN (1 << 16) /* Bit 16: RCC APB4ENR: RTCAPBEN */ + /* Bits 17-20: Reserved */ +#define RCC_APB4ENR_SAI4EN (1 << 21) /* Bit 21: RCC APB4ENR: SAI4EN */ + /* Bit2 22-31: Reserved */ /* AHB3 low power mode peripheral clock enable register */ -#define RCC_AHB3LPENR_MDMALPEN (1 << 0) /* RCC AHB3LPENR: MDMALPEN */ -#define RCC_AHB3LPENR_DMA2DLPEN (1 << 4) /* RCC AHB3LPENR: DMA2DLPEN */ -#define RCC_AHB3LPENR_JPGDECLPEN (1 << 5) /* RCC AHB3LPENR: JPGDECLPEN */ -#define RCC_AHB3LPENR_FLITFLPEN (1 << 8) /* RCC AHB3LPENR: FLITFLPEN */ -#define RCC_AHB3LPENR_FMCLPEN (1 << 12) /* RCC AHB3LPENR: FMCLPEN */ -#define RCC_AHB3LPENR_QSPILPEN (1 << 14) /* RCC AHB3LPENR: QSPILPEN */ -#define RCC_AHB3LPENR_SDMMC1LPEN (1 << 16) /* RCC AHB3LPENR: SDMMC1LPEN */ -#define RCC_AHB3LPENR_D1DTCM1LPEN (1 << 28) /* RCC AHB3LPENR: D1DTCM1LPEN */ -#define RCC_AHB3LPENR_DTCM2LPEN (1 << 29) /* RCC AHB3LPENR: DTCM2LPEN */ -#define RCC_AHB3LPENR_ITCMLPEN (1 << 30) /* RCC AHB3LPENR: ITCMLPEN */ -#define RCC_AHB3LPENR_AXISRAMLPEN (1 << 31) /* RCC AHB3LPENR: AXISRAMLPEN */ +#define RCC_AHB3LPENR_MDMALPEN (1 << 0) /* RCC AHB3LPENR: MDMALPEN */ +#define RCC_AHB3LPENR_DMA2DLPEN (1 << 4) /* RCC AHB3LPENR: DMA2DLPEN */ +#define RCC_AHB3LPENR_JPGDECLPEN (1 << 5) /* RCC AHB3LPENR: JPGDECLPEN */ +#define RCC_AHB3LPENR_FLITFLPEN (1 << 8) /* RCC AHB3LPENR: FLITFLPEN */ +#define RCC_AHB3LPENR_FMCLPEN (1 << 12) /* RCC AHB3LPENR: FMCLPEN */ +#define RCC_AHB3LPENR_QSPILPEN (1 << 14) /* RCC AHB3LPENR: QSPILPEN */ +#define RCC_AHB3LPENR_SDMMC1LPEN (1 << 16) /* RCC AHB3LPENR: SDMMC1LPEN */ +#define RCC_AHB3LPENR_D1DTCM1LPEN (1 << 28) /* RCC AHB3LPENR: D1DTCM1LPEN */ +#define RCC_AHB3LPENR_DTCM2LPEN (1 << 29) /* RCC AHB3LPENR: DTCM2LPEN */ +#define RCC_AHB3LPENR_ITCMLPEN (1 << 30) /* RCC AHB3LPENR: ITCMLPEN */ +#define RCC_AHB3LPENR_AXISRAMLPEN (1 << 31) /* RCC AHB3LPENR: AXISRAMLPEN */ /* AHB1 low power mode peripheral clock enable register */ -#define RCC_AHB1LPENR_DMA1LPEN (1 << 0) /* RCC AHB1LPENR: DMA1LPEN */ -#define RCC_AHB1LPENR_DMA2LPEN (1 << 1) /* RCC AHB1LPENR: DMA2LPEN */ -#define RCC_AHB1LPENR_ADC12LPEN (1 << 5) /* RCC AHB1LPENR: ADC12LPEN */ -#define RCC_AHB1LPENR_ETH1MACLPEN (1 << 15) /* RCC AHB1LPENR: ETH1MACLPEN */ -#define RCC_AHB1LPENR_ETH1TXLPEN (1 << 16) /* RCC AHB1LPENR: ETH1TXLPEN */ -#define RCC_AHB1LPENR_ETH1RXLPEN (1 << 17) /* RCC AHB1LPENR: ETH1RXLPEN */ -#define RCC_AHB1LPENR_OTGHSLPEN (1 << 25) /* RCC AHB1LPENR: OTGHSLPEN */ -#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 26) /* RCC AHB1LPENR: OTGHSULPILPEN */ -#define RCC_AHB1LPENR_OTGFSLPEN (1 << 27) /* RCC AHB1LPENR: OTGFSLPEN */ +#define RCC_AHB1LPENR_DMA1LPEN (1 << 0) /* RCC AHB1LPENR: DMA1LPEN */ +#define RCC_AHB1LPENR_DMA2LPEN (1 << 1) /* RCC AHB1LPENR: DMA2LPEN */ +#define RCC_AHB1LPENR_ADC12LPEN (1 << 5) /* RCC AHB1LPENR: ADC12LPEN */ +#define RCC_AHB1LPENR_ETH1MACLPEN (1 << 15) /* RCC AHB1LPENR: ETH1MACLPEN */ +#define RCC_AHB1LPENR_ETH1TXLPEN (1 << 16) /* RCC AHB1LPENR: ETH1TXLPEN */ +#define RCC_AHB1LPENR_ETH1RXLPEN (1 << 17) /* RCC AHB1LPENR: ETH1RXLPEN */ +#define RCC_AHB1LPENR_OTGHSLPEN (1 << 25) /* RCC AHB1LPENR: OTGHSLPEN */ +#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 26) /* RCC AHB1LPENR: OTGHSULPILPEN */ +#define RCC_AHB1LPENR_OTGFSLPEN (1 << 27) /* RCC AHB1LPENR: OTGFSLPEN */ /* AHB2 low power mode peripheral clock enable register */ -#define RCC_AHB2LPENR_CAMITFLPEN (1 << 0) /* RCC AHB2LPENR: CAMITFLPEN */ -#define RCC_AHB2LPENR_CRYPTLPEN (1 << 4) /* RCC AHB2LPENR: CRYPTLPEN */ -#define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* RCC AHB2LPENR: HASHLPEN */ -#define RCC_AHB2LPENR_SDMMC2LPEN (1 << 6) /* RCC AHB2LPENR: SDMMC2LPEN */ -#define RCC_AHB2LPENR_RNGLPEN (1 << 9) /* RCC AHB2LPENR: RNGLPEN */ -#define RCC_AHB2LPENR_SRAM1LPEN (1 << 29) /* RCC AHB2LPENR: SRAM1LPEN */ -#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* RCC AHB2LPENR: SRAM2LPEN */ -#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* RCC AHB2LPENR: SRAM3LPEN */ +#define RCC_AHB2LPENR_CAMITFLPEN (1 << 0) /* RCC AHB2LPENR: CAMITFLPEN */ +#define RCC_AHB2LPENR_CRYPTLPEN (1 << 4) /* RCC AHB2LPENR: CRYPTLPEN */ +#define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* RCC AHB2LPENR: HASHLPEN */ +#define RCC_AHB2LPENR_SDMMC2LPEN (1 << 6) /* RCC AHB2LPENR: SDMMC2LPEN */ +#define RCC_AHB2LPENR_RNGLPEN (1 << 9) /* RCC AHB2LPENR: RNGLPEN */ +#define RCC_AHB2LPENR_SRAM1LPEN (1 << 29) /* RCC AHB2LPENR: SRAM1LPEN */ +#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* RCC AHB2LPENR: SRAM2LPEN */ +#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* RCC AHB2LPENR: SRAM3LPEN */ /* AHB4 low power mode peripheral clock enable register */ -#define RCC_AHB4LPENR_GPIOALPEN (1 << 0) /* RCC AHB4LPENR: GPIOALPEN */ -#define RCC_AHB4LPENR_GPIOBLPEN (1 << 1) /* RCC AHB4LPENR: GPIOBLPEN */ -#define RCC_AHB4LPENR_GPIOCLPEN (1 << 2) /* RCC AHB4LPENR: GPIOCLPEN */ -#define RCC_AHB4LPENR_GPIODLPEN (1 << 3) /* RCC AHB4LPENR: GPIODLPEN */ -#define RCC_AHB4LPENR_GPIOELPEN (1 << 4) /* RCC AHB4LPENR: GPIOELPEN */ -#define RCC_AHB4LPENR_GPIOFLPEN (1 << 5) /* RCC AHB4LPENR: GPIOFLPEN */ -#define RCC_AHB4LPENR_GPIOGLPEN (1 << 6) /* RCC AHB4LPENR: GPIOGLPEN */ -#define RCC_AHB4LPENR_GPIOHLPEN (1 << 7) /* RCC AHB4LPENR: GPIOHLPEN */ -#define RCC_AHB4LPENR_GPIOILPEN (1 << 8) /* RCC AHB4LPENR: GPIOILPEN */ -#define RCC_AHB4LPENR_GPIOJLPEN (1 << 9) /* RCC AHB4LPENR: GPIOJLPEN */ -#define RCC_AHB4LPENR_GPIOKLPEN (1 << 10) /* RCC AHB4LPENR: GPIOKLPEN */ -#define RCC_AHB4LPENR_CRCLPEN (1 << 19) /* RCC AHB4LPENR: CRCLPEN */ -#define RCC_AHB4LPENR_BDMALPEN (1 << 21) /* RCC AHB4LPENR: BDMALPEN */ -#define RCC_AHB4LPENR_ADC3LPEN (1 << 24) /* RCC AHB4LPENR: ADC3LPEN */ -#define RCC_AHB4LPENR_BKPRAMLPEN (1 << 28) /* RCC AHB4LPENR: BKPRAMLPEN */ -#define RCC_AHB4LPENR_SRAM4LPEN (1 << 29) /* RCC AHB4LPENR: SRAM4LPEN */ +#define RCC_AHB4LPENR_GPIOALPEN (1 << 0) /* RCC AHB4LPENR: GPIOALPEN */ +#define RCC_AHB4LPENR_GPIOBLPEN (1 << 1) /* RCC AHB4LPENR: GPIOBLPEN */ +#define RCC_AHB4LPENR_GPIOCLPEN (1 << 2) /* RCC AHB4LPENR: GPIOCLPEN */ +#define RCC_AHB4LPENR_GPIODLPEN (1 << 3) /* RCC AHB4LPENR: GPIODLPEN */ +#define RCC_AHB4LPENR_GPIOELPEN (1 << 4) /* RCC AHB4LPENR: GPIOELPEN */ +#define RCC_AHB4LPENR_GPIOFLPEN (1 << 5) /* RCC AHB4LPENR: GPIOFLPEN */ +#define RCC_AHB4LPENR_GPIOGLPEN (1 << 6) /* RCC AHB4LPENR: GPIOGLPEN */ +#define RCC_AHB4LPENR_GPIOHLPEN (1 << 7) /* RCC AHB4LPENR: GPIOHLPEN */ +#define RCC_AHB4LPENR_GPIOILPEN (1 << 8) /* RCC AHB4LPENR: GPIOILPEN */ +#define RCC_AHB4LPENR_GPIOJLPEN (1 << 9) /* RCC AHB4LPENR: GPIOJLPEN */ +#define RCC_AHB4LPENR_GPIOKLPEN (1 << 10) /* RCC AHB4LPENR: GPIOKLPEN */ +#define RCC_AHB4LPENR_CRCLPEN (1 << 19) /* RCC AHB4LPENR: CRCLPEN */ +#define RCC_AHB4LPENR_BDMALPEN (1 << 21) /* RCC AHB4LPENR: BDMALPEN */ +#define RCC_AHB4LPENR_ADC3LPEN (1 << 24) /* RCC AHB4LPENR: ADC3LPEN */ +#define RCC_AHB4LPENR_BKPRAMLPEN (1 << 28) /* RCC AHB4LPENR: BKPRAMLPEN */ +#define RCC_AHB4LPENR_SRAM4LPEN (1 << 29) /* RCC AHB4LPENR: SRAM4LPEN */ /* APB3 low power mode peripheral clock enable register */ -#define RCC_APB3LPENR_LTDCLPEN (1 << 3) /* RCC APB3LPENR: LTDCLPEN */ -#define RCC_APB3LPENR_WWDG1LPEN (1 << 6) /* RCC APB3LPENR: WWDG1LPEN */ +#define RCC_APB3LPENR_LTDCLPEN (1 << 3) /* RCC APB3LPENR: LTDCLPEN */ +#define RCC_APB3LPENR_WWDG1LPEN (1 << 6) /* RCC APB3LPENR: WWDG1LPEN */ /* APB1 L low power mode peripheral clock enable register */ -#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* RCC APB1LLPENR: TIM2LPEN */ -#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* RCC APB1LLPENR: TIM3LPEN */ -#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* RCC APB1LLPENR: TIM4LPEN */ -#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* RCC APB1LLPENR: TIM5LPEN */ -#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* RCC APB1LLPENR: TIM6LPEN */ -#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* RCC APB1LLPENR: TIM7LPEN */ -#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* RCC APB1LLPENR: TIM12LPEN */ -#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* RCC APB1LLPENR: TIM13LPEN */ -#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* RCC APB1LLPENR: TIM14LPEN */ -#define RCC_APB1LLPENR_LPTIM1LPEN (1 << 9) /* RCC APB1LLPENR: LPTIM1LPEN */ -#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* RCC APB1LLPENR: SPI2LPEN */ -#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* RCC APB1LLPENR: SPI3LPEN */ -#define RCC_APB1LLPENR_SPDIFRXLPEN (1 << 16) /* RCC APB1LLPENR: SPDIFRXLPEN */ -#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* RCC APB1LLPENR: USART2LPEN */ -#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* RCC APB1LLPENR: USART3LPEN */ -#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* RCC APB1LLPENR: UART4LPEN */ -#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* RCC APB1LLPENR: UART5LPEN */ -#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* RCC APB1LLPENR: I2C1LPEN */ -#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* RCC APB1LLPENR: I2C2LPEN */ -#define RCC_APB1LLPENR_I2C3LPEN (1 << 23) /* RCC APB1LLPENR: I2C3LPEN */ -#define RCC_APB1LLPENR_HDMICECLPEN (1 << 27) /* RCC APB1LLPENR: HDMICECLPEN */ -#define RCC_APB1LLPENR_DAC1LPEN (1 << 29) /* RCC APB1LLPENR: DAC1LPEN */ -#define RCC_APB1LLPENR_UART7LPEN (1 << 30) /* RCC APB1LLPENR: UART7LPEN */ -#define RCC_APB1LLPENR_UART8LPEN (1 << 31) /* RCC APB1LLPENR: UART8LPEN */ +#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* RCC APB1LLPENR: TIM2LPEN */ +#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* RCC APB1LLPENR: TIM3LPEN */ +#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* RCC APB1LLPENR: TIM4LPEN */ +#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* RCC APB1LLPENR: TIM5LPEN */ +#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* RCC APB1LLPENR: TIM6LPEN */ +#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* RCC APB1LLPENR: TIM7LPEN */ +#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* RCC APB1LLPENR: TIM12LPEN */ +#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* RCC APB1LLPENR: TIM13LPEN */ +#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* RCC APB1LLPENR: TIM14LPEN */ +#define RCC_APB1LLPENR_LPTIM1LPEN (1 << 9) /* RCC APB1LLPENR: LPTIM1LPEN */ +#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* RCC APB1LLPENR: SPI2LPEN */ +#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* RCC APB1LLPENR: SPI3LPEN */ +#define RCC_APB1LLPENR_SPDIFRXLPEN (1 << 16) /* RCC APB1LLPENR: SPDIFRXLPEN */ +#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* RCC APB1LLPENR: USART2LPEN */ +#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* RCC APB1LLPENR: USART3LPEN */ +#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* RCC APB1LLPENR: UART4LPEN */ +#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* RCC APB1LLPENR: UART5LPEN */ +#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* RCC APB1LLPENR: I2C1LPEN */ +#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* RCC APB1LLPENR: I2C2LPEN */ +#define RCC_APB1LLPENR_I2C3LPEN (1 << 23) /* RCC APB1LLPENR: I2C3LPEN */ +#define RCC_APB1LLPENR_HDMICECLPEN (1 << 27) /* RCC APB1LLPENR: HDMICECLPEN */ +#define RCC_APB1LLPENR_DAC1LPEN (1 << 29) /* RCC APB1LLPENR: DAC1LPEN */ +#define RCC_APB1LLPENR_UART7LPEN (1 << 30) /* RCC APB1LLPENR: UART7LPEN */ +#define RCC_APB1LLPENR_UART8LPEN (1 << 31) /* RCC APB1LLPENR: UART8LPEN */ /* APB1 H low power mode peripheral clock enable register */ -#define RCC_APB1HLPENR_CRSLPEN (1 << 1) /* RCC APB1HLPENR: CRSLPEN */ -#define RCC_APB1HLPENR_SWPLPEN (1 << 2) /* RCC APB1HLPENR: SWPLPEN */ -#define RCC_APB1HLPENR_OPAMPLPEN (1 << 4) /* RCC APB1HLPENR: OPAMPLPEN */ -#define RCC_APB1HLPENR_MDIOSLPEN (1 << 5) /* RCC APB1HLPENR: MDIOSLPEN */ -#define RCC_APB1HLPENR_FDCANLPEN (1 << 8) /* RCC APB1HLPENR: FDCANLPEN */ +#define RCC_APB1HLPENR_CRSLPEN (1 << 1) /* RCC APB1HLPENR: CRSLPEN */ +#define RCC_APB1HLPENR_SWPLPEN (1 << 2) /* RCC APB1HLPENR: SWPLPEN */ +#define RCC_APB1HLPENR_OPAMPLPEN (1 << 4) /* RCC APB1HLPENR: OPAMPLPEN */ +#define RCC_APB1HLPENR_MDIOSLPEN (1 << 5) /* RCC APB1HLPENR: MDIOSLPEN */ +#define RCC_APB1HLPENR_FDCANLPEN (1 << 8) /* RCC APB1HLPENR: FDCANLPEN */ /* APB2 low power mode peripheral clock enable register */ -#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* RCC APB2LPENR: TIM1LPEN */ -#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* RCC APB2LPENR: TIM8LPEN */ -#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* RCC APB2LPENR: USART1LPEN */ -#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* RCC APB2LPENR: USART6LPEN */ -#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* RCC APB2LPENR: SPI1LPEN */ -#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* RCC APB2LPENR: SPI4LPEN */ -#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* RCC APB2LPENR: TIM15LPEN */ -#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* RCC APB2LPENR: TIM16LPEN */ -#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* RCC APB2LPENR: TIM17LPEN */ -#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* RCC APB2LPENR: SPI5LPEN */ -#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* RCC APB2LPENR: SAI1LPEN */ -#define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* RCC APB2LPENR: SAI2LPEN */ -#define RCC_APB2LPENR_SAI3LPEN (1 << 24) /* RCC APB2LPENR: SAI3LPEN */ -#define RCC_APB2LPENR_DFSDM1LPEN (1 << 28) /* RCC APB2LPENR: DFSDM1LPEN */ -#define RCC_APB2LPENR_HRTIMLPEN (1 << 29) /* RCC APB2LPENR: HRTIMLPEN */ +#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* RCC APB2LPENR: TIM1LPEN */ +#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* RCC APB2LPENR: TIM8LPEN */ +#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* RCC APB2LPENR: USART1LPEN */ +#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* RCC APB2LPENR: USART6LPEN */ +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* RCC APB2LPENR: SPI1LPEN */ +#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* RCC APB2LPENR: SPI4LPEN */ +#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* RCC APB2LPENR: TIM15LPEN */ +#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* RCC APB2LPENR: TIM16LPEN */ +#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* RCC APB2LPENR: TIM17LPEN */ +#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* RCC APB2LPENR: SPI5LPEN */ +#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* RCC APB2LPENR: SAI1LPEN */ +#define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* RCC APB2LPENR: SAI2LPEN */ +#define RCC_APB2LPENR_SAI3LPEN (1 << 24) /* RCC APB2LPENR: SAI3LPEN */ +#define RCC_APB2LPENR_DFSDM1LPEN (1 << 28) /* RCC APB2LPENR: DFSDM1LPEN */ +#define RCC_APB2LPENR_HRTIMLPEN (1 << 29) /* RCC APB2LPENR: HRTIMLPEN */ /* APB4 low power mode peripheral clock enable register */ -#define RCC_APB4LPENR_SYSCFGLPEN (1 << 1) /* RCC APB4LPENR: SYSCFGLPEN */ -#define RCC_APB4LPENR_LPUART1LPEN (1 << 3) /* RCC APB4LPENR: LPUART1LPEN */ -#define RCC_APB4LPENR_SPI6LPEN (1 << 5) /* RCC APB4LPENR: SPI6LPEN */ -#define RCC_APB4LPENR_I2C4LPEN (1 << 7) /* RCC APB4LPENR: I2C4LPEN */ -#define RCC_APB4LPENR_LPTIM2LPEN (1 << 9) /* RCC APB4LPENR: LPTIM2LPEN */ -#define RCC_APB4LPENR_LPTIM3LPEN (1 << 10) /* RCC APB4LPENR: LPTIM3LPEN */ -#define RCC_APB4LPENR_LPTIM4LPEN (1 << 11) /* RCC APB4LPENR: LPTIM4LPEN */ -#define RCC_APB4LPENR_LPTIM5LPEN (1 << 12) /* RCC APB4LPENR: LPTIM5LPEN */ -#define RCC_APB4LPENR_COMP12LPEN (1 << 14) /* RCC APB4LPENR: COMP12LPEN */ -#define RCC_APB4LPENR_VREFLPEN (1 << 15) /* RCC APB4LPENR: VREFLPEN */ -#define RCC_APB4LPENR_RTCAPBLPEN (1 << 16) /* RCC APB4LPENR: RTCAPBLPEN */ -#define RCC_APB4LPENR_SAI4LPEN (1 << 21) /* RCC APB4LPENR: SAI4LPEN */ +#define RCC_APB4LPENR_SYSCFGLPEN (1 << 1) /* RCC APB4LPENR: SYSCFGLPEN */ +#define RCC_APB4LPENR_LPUART1LPEN (1 << 3) /* RCC APB4LPENR: LPUART1LPEN */ +#define RCC_APB4LPENR_SPI6LPEN (1 << 5) /* RCC APB4LPENR: SPI6LPEN */ +#define RCC_APB4LPENR_I2C4LPEN (1 << 7) /* RCC APB4LPENR: I2C4LPEN */ +#define RCC_APB4LPENR_LPTIM2LPEN (1 << 9) /* RCC APB4LPENR: LPTIM2LPEN */ +#define RCC_APB4LPENR_LPTIM3LPEN (1 << 10) /* RCC APB4LPENR: LPTIM3LPEN */ +#define RCC_APB4LPENR_LPTIM4LPEN (1 << 11) /* RCC APB4LPENR: LPTIM4LPEN */ +#define RCC_APB4LPENR_LPTIM5LPEN (1 << 12) /* RCC APB4LPENR: LPTIM5LPEN */ +#define RCC_APB4LPENR_COMP12LPEN (1 << 14) /* RCC APB4LPENR: COMP12LPEN */ +#define RCC_APB4LPENR_VREFLPEN (1 << 15) /* RCC APB4LPENR: VREFLPEN */ +#define RCC_APB4LPENR_RTCAPBLPEN (1 << 16) /* RCC APB4LPENR: RTCAPBLPEN */ +#define RCC_APB4LPENR_SAI4LPEN (1 << 21) /* RCC APB4LPENR: SAI4LPEN */ /* Backup domain control register */ -#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ -#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 4:3: LSE oscillator Drive selection */ +#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ +#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 4:3: LSE oscillator Drive selection */ #define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) # define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Low driving capability */ # define RCC_BDCR_LSEDRV_MEDHI (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium high driving capability */ # define RCC_BDCR_LSEDRV_MEDLO (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium low driving capability */ # define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: High driving capability */ -#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: LSE clock security system enable */ -#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: LSE clock security system failure detection */ - /* Bit 7: Reserved */ -#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ +#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: LSE clock security system enable */ +#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: LSE clock security system failure detection */ + /* Bit 7: Reserved */ +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ #define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) # define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ # define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ - /* Bits 10-15: Reserved */ -#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ -#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ - /* Bits 17-31: Reserved */ + /* Bits 10-15: Reserved */ +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ +#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ + /* Bits 17-31: Reserved */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_RCC_H */ diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c index 1cce672abc..cc56ae8a5e 100644 --- a/arch/arm/src/stm32h7/stm32_allocateheap.c +++ b/arch/arm/src/stm32h7/stm32_allocateheap.c @@ -60,33 +60,57 @@ #include "hardware/stm32_memorymap.h" #include "stm32_mpuinit.h" #include "stm32_dtcm.h" +#include "stm32_fmc.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Internal SRAM is available in all members of the STM32 family. The - * following definitions must be provided to specify the size and - * location of internal(system) SRAM: +/* At startup the kernel will invoke up_addregion() so that platform code + * may register available memories for use as part of system heap. + * The global configuration option CONFIG_MM_REGIONS defines the maximal + * number of non-contiguous memory ranges that may be registered with the + * system heap. You must make sure it is large enough to hold all memory + * regions you intend to use. * - * In addition to internal SRAM, external RAM may also be available through - * the FMC. In order to use FMC RAM, the following additional things need - * to be present in the NuttX configuration file: + * The following memory types can be used for heap on STM32H7 platform: * - * CONFIG_STM32H7_FMC=y : Enables the FMC - * CONFIG_STM32H7_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC. - * Either of these autoselects - * CONFIG_ARCH_HAVE_HEAP2 which is what we - * are interested in here. - * CONFIG_HEAP2_BASE : The base address of the external RAM in - * the FMC address space - * CONFIG_HEAP2_SIZE : The size of the external RAM in the FMC - * address space - * CONFIG_MM_REGIONS : Must be set to a large enough value to - * include the FMC external RAM (as determined - * by the rules provided below) + * - AXI SRAM is a 512kb memory area. This will be automatically registered + * with the system heap in up_allocate_heap, all the other memory + * regions will be registered in up_addregion(). + * So, CONFIG_MM_REGIONS must be at least 1 to use AXI SRAM. * - * CONFIG_STM32H7_DTCMEXCLUDE : Set to exclude the DTCM from heap + * - Internal SRAM is available in all members of the STM32 family. + * This is always registered with system heap. + * There are two contiguous regions of internal SRAM: + * SRAM1+SRAM2+SRAM3 and SRAM4 at a separate address. + * So, add 2 more to CONFIG_MM_REGIONS. + * + * - Tightly Coupled Memory (TCM RAM), we can use Data TCM (DTCM) for system + * heap. Note that DTCM has a number of limitations, for example DMA + * transfers to/from DTCM are limited. + * Define CONFIG_STM32H7_DTCMEXCLUDE to exclude the DTCM from heap. + * +1 to CONFIG_MM_REGIONS if you want to use DTCM. + * + * - External SDRAM can be connected to the FMC peripherial. Initialization + * of FMC is done as up_addregion() will invoke stm32_fmc_init(). + * Please read the comment in stm32_fmc.c how to initialize FMC + * correctly. + * + * Then, up to two regions of SDRAM may be registered with the heap: + * + * - BOARD_SDRAM1_SIZE, if defined, declares the size of SDRAM + * at address STM32_FMC_BANK5. +1 to CONFIG_MM_REGIONS. + * - BOARD_SDRAM2_SIZE, if defined, declares the size of SDRAM + * at address STM32_FMC_BANK6. +1 to CONFIG_MM_REGIONS. + * + * - Additionaly, you may use the following options to add one more region + * of memory to system heap: + * + * - CONFIG_ARCH_HAVE_HEAP2=y + * - CONFIG_HEAP2_BASE=base address of memory area. + * - CONFIG_HEAP2_SIZE=size of memory area. + * - +1 to CONFIG_MM_REGIONS */ /* Set the start and end of the SRAMs */ @@ -114,28 +138,6 @@ # undef HAVE_DTCM #endif -/* There are possible heap configurations: - * - * Configuration 1. System SRAM (only) - * CONFIG_MM_REGIONS == 1 - * Configuration 2. System SRAM and SRAM123 - * CONFIG_MM_REGIONS == 2 - * Configuration 3. System SRAM and SRAM123 and DTCM - * CONFIG_MM_REGIONS == 3 - * HAVE_DTCM defined - * Configuration 4. System SRAM and SRAM123 and DTCM and SRAM4 - * CONFIG_MM_REGIONS == 4 - * HAVE_DTCM defined - * Configuration 5. System SRAM and SRAM123 and DTCM and SRAM4 and FMC RAM - * CONFIG_MM_REGIONS == 5 - * HAVE_DTCM defined - * - * TODO .... - * - * Let's make sure that all definitions are consistent before doing - * anything else - */ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -204,7 +206,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = SRAM123_END - ubase; int log2; @@ -246,6 +249,10 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) up_heap_color(*heap_start, *heap_size); #endif + + /* Display memory ranges to help debugging */ + + minfo("%uKb of SRAM at %p\n", *heap_size / 1024, *heap_start); } /**************************************************************************** @@ -266,7 +273,8 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = SRAM123_END - ubase; int log2; @@ -292,6 +300,38 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) } #endif +/**************************************************************************** + * Name: addregion + * + * Description: + * Make a range of memory available for allocation from system heap. + * If debug is disabled, compiler should optimize out the "desc" strings. + * + ****************************************************************************/ + +static void addregion (uintptr_t start, uint32_t size, const char *desc) +{ + /* Display memory ranges to help debugging */ + + minfo("%uKb of %s at %p\n", size / 1024, desc, (FAR void *)start); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + + /* Allow user-mode access to the SRAM123 heap */ + + stm32_mpu_uheap(start, size); + +#endif + + /* Colorize the heap for debug */ + + up_heap_color((FAR void *)start, size); + + /* Add the SRAM123 user heap region. */ + + kumm_addregion((FAR void *)start, size); +} + /**************************************************************************** * Name: up_addregion * @@ -301,81 +341,51 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * ****************************************************************************/ -#if CONFIG_MM_REGIONS > 1 void up_addregion(void) { -# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + addregion (SRAM123_START, SRAM123_END - SRAM123_START, "SRAM1,2,3"); - /* Allow user-mode access to the SRAM123 heap */ + unsigned mm_regions = 1; - stm32_mpu_uheap((uintptr_t)SRAM123_START, SRAM123_END - SRAM123_START); + if (mm_regions < CONFIG_MM_REGIONS) + { + addregion (SRAM4_START, SRAM4_END - SRAM4_START, "SRAM4"); + mm_regions++; + } -# endif - - /* Colorize the heap for debug */ - - up_heap_color((FAR void *)SRAM123_START, SRAM123_END - SRAM123_START); - - /* Add the SRAM123 user heap region. */ - - kumm_addregion((FAR void *)SRAM123_START, SRAM123_END - SRAM123_START); - -# if CONFIG_MM_REGIONS > 2 -# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) - - /* Allow user-mode access to the SRAM4 user heap memory */ - - stm32_mpu_uheap((uintptr_t)SRAM4_START, SRAM4_END - SRAM4_START); - -# endif - - /* Colorize the heap for debug */ - - up_heap_color((FAR void *)SRAM4_START, SRAM4_END - SRAM4_START); - - /* Add the external SRAM4 user heap region. */ - - kumm_addregion((FAR void *)SRAM4_START, SRAM4_END - SRAM4_START); -# endif - -# if CONFIG_MM_REGIONS > 3 -# ifdef HAVE_DTCM -# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) - - /* Allow user-mode access to the DTCM heap */ - - stm32_mpu_uheap((uintptr_t)DTCM_START, DTCM_END - DTCM_START); - -# endif - - /* Colorize the heap for debug */ - - up_heap_color((FAR void *)DTCM_START, DTCM_END - DTCM_START); - - /* Add the DTCM user heap region. */ - - kumm_addregion((FAR void *)DTCM_START, DTCM_END - DTCM_START); -# endif -# endif - -# if CONFIG_MM_REGIONS > 4 -# ifdef CONFIG_ARCH_HAVE_HEAP2 -# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) - - /* Allow user-mode access to the FMC RAM user heap memory */ - - stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); - -# endif - - /* Colorize the heap for debug */ - - up_heap_color((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); - - /* Add the external FMC RAM user heap region. */ - - kumm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); -# endif -# endif -} +#ifdef HAVE_DTCM + if (mm_regions < CONFIG_MM_REGIONS) + { + addregion (DTCM_START, DTCM_END - DTCM_START, "DTCM"); + mm_regions++; + } #endif + +#ifdef CONFIG_STM32H7_FMC + stm32_fmc_init(); +#endif + +#ifdef BOARD_SDRAM1_SIZE + if (mm_regions < CONFIG_MM_REGIONS) + { + addregion (STM32_FMC_BANK5, BOARD_SDRAM1_SIZE, "SDRAM1"); + mm_regions++; + } +#endif + +#ifdef BOARD_SDRAM2_SIZE + if (mm_regions < CONFIG_MM_REGIONS) + { + addregion (STM32_FMC_BANK6, BOARD_SDRAM2_SIZE, "SDRAM2"); + mm_regions++; + } +#endif + +#ifdef CONFIG_ARCH_HAVE_HEAP2 + if (mm_regions < CONFIG_MM_REGIONS) + { + addregion (CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE, "HEAP2"); + mm_regions++; + } +#endif +} diff --git a/arch/arm/src/stm32h7/stm32_fmc.c b/arch/arm/src/stm32h7/stm32_fmc.c index f40e0ca87f..e5364c115f 100644 --- a/arch/arm/src/stm32h7/stm32_fmc.c +++ b/arch/arm/src/stm32h7/stm32_fmc.c @@ -39,40 +39,410 @@ #include +#if defined(CONFIG_STM32H7_FMC) + #include "stm32.h" -#if defined(CONFIG_STM32H7_FMC) +#include + +#include +#include + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +/**************************************************************************** + * To use FMC, you must first enable it in configuration: + * + * CONFIG_STM32H7_FMC=y + * + * FMC is statically configured at startup. Its configuration is adjusted + * using BOARD_XXX macros described below, which should be declared + * in your board.h file. + * + * The BOARD_FMC_CLK macro can be defined to select the clock source for FMC. + * This can be one of RCC_D1CCIPR_FMCSEL_xxx macros, and defaults to + * RCC_D1CCIPR_FMCSEL_PLL2 (which means PLL2R). + * + * + * To correctly initialize GPIO pins the macro BOARD_FMC_GPIO_CONFIGS should + * define a list of 32-bit GPIO configuration bitmasks. Example: + * + * #define BOARD_FMC_GPIO_CONFIGS GPIO_FMC_A0,GPIO_FMC_A1,\ + * GPIO_FMC_A2,...,GPIO_FMC_D0,...,GPIO_FMC_NBL0,... + * + * + * For SRAM/NOR-Flash memories FMC defines 4 x 64Mb sub-banks at addresses + * 0x60000000, 0x64000000, 0x68000000, 0x6C000000. The following macros + * can be defined in board.h to initialize FMC for use with SRAM/NOR-Flash: + * + * *** CURRENTLY SRAM/NOR-FLASH SUPPORT IS NOT IMPLEMENTED *** + * + * BOARD_FMC_BCR[1..4] - Initial value for control registers + * for subbanks 1-4. + * BOARD_FMC_BTR[1..4] - Initial value for SRAM/NOR-Flash timing registers + * for subbanks 1-4. + * BOARD_FMC_BWTR[1..4] - Initial value for SRAM/NOR-Flash write timing + * registers for subbanks 1-4. + * + * + * For NAND flash memories FMC reserves 64Mb at 0x80000000. Define the + * following macros in your board.h file to initialize FMC for this type + * of memory: + * + * *** CURRENTLY NAND FLASH SUPPORT IS NOT IMPLEMENTED *** + * + * BOARD_FMC_PCR - Initial value for NAND flash control register. + * BOARD_FMC_PMEM - Initial value for NAND flash common memory space timing + * register. + * BOARD_FMC_PATT - Initial value for NAND flash attribute memory space + * timing register. + * + * + * For SDRAM memory FMC reserves 2 x 256Mb address ranges at 0xC0000000 + * and 0xD0000000. Define the following macros to initialize FMC to work + * with SDRAM: + * + * BOARD_FMC_SDCR[1..2] - Initial value for SDRAM control registers for SDRAM + * bank 1-2. Note that some bits in SDCR1 influence both SDRAM banks and + * are unused in SDCR2! + * BOARD_FMC_SDTR[1..2] - Initial value for SDRAM timing registeres for SDRAM + * bank 1-2. Note that some bits in SDTR1 influence both SDRAM banks and + * are unused in SDTR2! + * BOARD_FMC_SDRAM_REFR_PERIOD - The SDRAM refresh rate period in FMC clocks, + * OR + * BOARD_FMC_SDRAM_REFR_CYCLES and BOARD_FMC_SDRAM_REFR_PERIOD can be used to + * automatically compute refresh counter using data from SDRAM datasheet + * (cycles usually is 4096, 8192 and such, and typical period is 64 ms) + * and knowing FMC clock frequency. + * BOARD_FMC_SDRAM_AUTOREFRESH may be defined to a number between 1 and 16 to + * issue given number of SDRAM auto-refresh cycles before using it. This + * defaults to 3. + * + * + * Special notes: + * - FMC bank remapping (FMC_BCR_BMAP*) is not currently supported. + * + * + * Here's a working example of a configured IS42S16320D SDRAM on a particular + * board: + * + *#define BOARD_SDRAM1_SIZE (64*1024*1024) + * + *#define BOARD_FMC_SDCR1 \ + * (FMC_SDCR_COLBITS_10 | FMC_SDCR_ROWBITS_13 | FMC_SDCR_WIDTH_16 |\ + * FMC_SDCR_BANKS_4 | FMC_SDCR_CASLAT_2 | FMC_SDCR_SDCLK_2X |\ + * FMC_SDCR_BURST_READ | FMC_SDCR_RPIPE_1) + *#define BOARD_FMC_SDTR1 \ + * (FMC_SDTR_TMRD(2) | FMC_SDTR_TXSR(7) | FMC_SDTR_TRAS(4) | \ + * FMC_SDTR_TRC(7) | FMC_SDTR_TWR(4) | FMC_SDTR_TRP(2) | \ + * FMC_SDTR_TRCD(2)) + *#define BOARD_FMC_SDRAM_REFR_CYCLES 8192 + *#define BOARD_FMC_SDRAM_REFR_PERIOD 64 + *#define BOARD_FMC_SDRAM_MODE \ + * FMC_SDCMR_MRD_BURST_LENGTH_8 | \ + * FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL | \ + * FMC_SDCMR_MRD_CAS_LATENCY_2 + * + *#define BOARD_FMC_GPIO_CONFIGS \ + * GPIO_FMC_A0,GPIO_FMC_A1,GPIO_FMC_A2,GPIO_FMC_A3,GPIO_FMC_A4,\ + * GPIO_FMC_A5,GPIO_FMC_A6,GPIO_FMC_A7,GPIO_FMC_A8,GPIO_FMC_A9,\ + * GPIO_FMC_A10,GPIO_FMC_A11,GPIO_FMC_A12,\ + * GPIO_FMC_D0,GPIO_FMC_D1,GPIO_FMC_D2,GPIO_FMC_D3,GPIO_FMC_D4,\ + * GPIO_FMC_D5,GPIO_FMC_D6,GPIO_FMC_D7,GPIO_FMC_D8,GPIO_FMC_D9,\ + * GPIO_FMC_D10,GPIO_FMC_D11,GPIO_FMC_D12,GPIO_FMC_D13,\ + * GPIO_FMC_D14,GPIO_FMC_D15,\ + * GPIO_FMC_NBL0,GPIO_FMC_NBL1,GPIO_FMC_BA0,GPIO_FMC_BA1,\ + * GPIO_FMC_SDNWE_2,GPIO_FMC_SDNCAS,GPIO_FMC_SDNRAS,\ + * GPIO_FMC_SDNE0_1,GPIO_FMC_SDCKE0_1,GPIO_FMC_SDCLK + * + ****************************************************************************/ + +#ifndef BOARD_FMC_CLK +/* Clock FMC from PLL2R by default */ + +# define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_PLL2 +#endif + +/* A couple of macros to know if user uses SDRAM1 and/or SDRAM2 */ + +#if defined BOARD_FMC_SDCR1 && ((BOARD_FMC_SDCR1 & FMC_SDCR_CASLAT_MASK) != 0) +# define HAVE_FMC_SDRAM1 1 +#endif +#if defined BOARD_FMC_SDCR2 && ((BOARD_FMC_SDCR2 & FMC_SDCR_CASLAT_MASK) != 0) +# define HAVE_FMC_SDRAM2 1 +#endif + +#if defined HAVE_FMC_SDRAM1 || defined HAVE_FMC_SDRAM2 +# define HAVE_FMC_SDRAM 1 +#endif + +/* Number of auto-refresh cycles to issue at SDRAM initialization */ + +#ifndef BOARD_FMC_SDRAM_AUTOREFRESH +# define BOARD_FMC_SDRAM_AUTOREFRESH 3 +#endif + +/* Find out the clock frequency for FMC */ + +#if BOARD_FMC_CLK == RCC_D1CCIPR_FMCSEL_HCLK +# define FMC_CLK_FREQUENCY STM32_HCLK_FREQUENCY +#elif BOARD_FMC_CLK == RCC_D1CCIPR_FMCSEL_PLL1 +# define FMC_CLK_FREQUENCY STM32_PLL1Q_FREQUENCY +#elif BOARD_FMC_CLK == RCC_D1CCIPR_FMCSEL_PLL2 +# define FMC_CLK_FREQUENCY STM32_PLL2R_FREQUENCY +#elif BOARD_FMC_CLK == RCC_D1CCIPR_FMCSEL_PER +# define FMC_CLK_FREQUENCY STM32_PER_FREQUENCY +#else +# error "BOARD_FMC_CLK has unknown value!" +#endif + +/* Compute the refresh rate in clocks */ + +#ifndef BOARD_FMC_SDRAM_REFR_PERIOD + +# if !defined(BOARD_FMC_SDRAM_REFR_CYCLES) || !defined(BOARD_FMC_SDRAM_REFR_PERIOD) +# error "Both BOARD_FMC_SDRAM_REFR_CYCLES and BOARD_FMC_SDRAM_REFR_PERIOD have to be defined to compute BOARD_FMC_SDRAM_REFR_PERIOD!" +# else + /* Take care not to overflow on 32-bit arithmetic */ + +# define BOARD_FMC_SDRAM_REFR_PERIOD ((uint32_t)((uint64_t)BOARD_FMC_SDRAM_REFR_PERIOD * FMC_CLK_FREQUENCY / BOARD_FMC_SDRAM_REFR_CYCLES - 20)) +# endif + +#endif /* BOARD_FMC_SDRAM_REFR_PERIOD */ + +/* The bits in FMC_SDCR we will alter at initialization */ + +#define FMC_SDCR_MASK (FMC_SDCR_COLBITS_MASK | FMC_SDCR_ROWBITS_MASK | \ + FMC_SDCR_WIDTH_MASK | FMC_SDCR_BANKS_MASK | FMC_SDCR_CASLAT_MASK | FMC_SDCR_WP | \ + FMC_SDCR_SDCLK_MASK | FMC_SDCR_BURST_READ | FMC_SDCR_RPIPE_MASK) + +/* The bits in FMC_SDTR we will alter at initialization */ + +#define FMC_SDTR_MASK (FMC_SDTR_TMRD_MASK | FMC_SDTR_TXSR_MASK | \ + FMC_SDTR_TRAS_MASK | FMC_SDTR_TRC_MASK | FMC_SDTR_TWR_MASK | FMC_SDTR_TRP_MASK | \ + FMC_SDTR_TRCD_MASK) + +/* The timeout while waiting for SDRAM controller to initialize, in us */ + +#define SDRAM_INIT_TIMEOUT (1000) + +/**************************************************************************** + * Private data + ****************************************************************************/ + +static uint32_t fmc_gpios[] = +{ + BOARD_FMC_GPIO_CONFIGS +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void stm32_fmc_sdram_init(void); +static int stm32_fmc_sdram_wait(unsigned timeout); /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32_fmc_enable + * Name: stm32_fmc_init * * Description: - * Enable clocking to the FMC. + * Initialize the FMC peripherial. Because FMC initialization is highly + * dependent on the used parts, definition of the initial values for FMC + * registers is mostly left to board designer. + * + * Typically called from up_addregion(). * ****************************************************************************/ -void stm32_fmc_enable_clk(void) +void stm32_fmc_init(void) { - modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FMCEN); + uint32_t regval; + + /* Reset the FMC on the AHB3 bus */ + + regval = getreg32(STM32_RCC_AHB3RSTR); + regval |= RCC_AHB3RSTR_FMCRST; + putreg32(regval, STM32_RCC_AHB3RSTR); + + /* Leave reset state */ + + regval &= ~RCC_AHB3RSTR_FMCRST; + putreg32(regval, STM32_RCC_AHB3RSTR); + + /* Set FMC clocking */ + + modreg32 (BOARD_FMC_CLK, RCC_D1CCIPR_FMCSEL_MASK, STM32_RCC_D1CCIPR); + + /* Set up FMC GPIOs */ + + for (regval = 0; regval < ARRAY_SIZE(fmc_gpios); regval++) + stm32_configgpio(fmc_gpios[regval]); + + /* Set up FMC registers */ + +#ifdef BOARD_FMC_SDCR1 + modreg32(BOARD_FMC_SDCR1, FMC_SDCR_MASK, STM32_FMC_SDCR1); +#endif +#ifdef BOARD_FMC_SDCR2 + modreg32(BOARD_FMC_SDCR2, FMC_SDCR_MASK, STM32_FMC_SDCR2); +#endif + +#ifdef BOARD_FMC_SDTR1 + modreg32(BOARD_FMC_SDTR1, FMC_SDTR_MASK, STM32_FMC_SDTR1); +#endif +#ifdef BOARD_FMC_SDTR2 + modreg32(BOARD_FMC_SDTR2, FMC_SDTR_MASK, STM32_FMC_SDTR2); +#endif + + /* Enable the FMC peripherial */ + + modreg32(FMC_BCR_FMCEN, FMC_BCR_FMCEN, STM32_FMC_BCR1); + + /* Initialize the SDRAM chips themselves */ + +#ifdef HAVE_FMC_SDRAM + stm32_fmc_sdram_init(); +#endif + + /* Set up SDRAM refresh timings */ + +#ifdef BOARD_FMC_SDRAM_REFR_PERIOD + /* ... The programmed COUNT value must not be equal to the sum of the + * following timings: TWR+TRP+TRC+TRCD+4 memory clock cycles + */ + +#ifdef BOARD_FMC_SDTR1 + DEBUGASSERT (BOARD_FMC_SDRAM_REFR_PERIOD != + (4 + + (1 + ((BOARD_FMC_SDTR1 & FMC_SDTR_TWR_MASK) >> FMC_SDTR_TWR_SHIFT)) + + (1 + ((BOARD_FMC_SDTR1 & FMC_SDTR_TRP_MASK) >> FMC_SDTR_TRP_SHIFT)) + + (1 + ((BOARD_FMC_SDTR1 & FMC_SDTR_TRC_MASK) >> FMC_SDTR_TRC_SHIFT)) + + (1 + ((BOARD_FMC_SDTR1 & FMC_SDTR_TRCD_MASK) >> FMC_SDTR_TRCD_SHIFT)))); +#endif +#ifdef BOARD_FMC_SDTR2 + DEBUGASSERT (BOARD_FMC_SDRAM_REFR_PERIOD != + (4 + + (1 + ((BOARD_FMC_SDTR2 & FMC_SDTR_TWR_MASK) >> FMC_SDTR_TWR_SHIFT)) + + (1 + ((BOARD_FMC_SDTR2 & FMC_SDTR_TRP_MASK) >> FMC_SDTR_TRP_SHIFT)) + + (1 + ((BOARD_FMC_SDTR2 & FMC_SDTR_TRC_MASK) >> FMC_SDTR_TRC_SHIFT)) + + (1 + ((BOARD_FMC_SDTR2 & FMC_SDTR_TRCD_MASK) >> FMC_SDTR_TRCD_SHIFT)))); +#endif + + stm32_fmc_sdram_set_refresh_rate(BOARD_FMC_SDRAM_REFR_PERIOD); +#endif /* BOARD_FMC_SDRTR */ +} + +#ifdef HAVE_FMC_SDRAM + +/**************************************************************************** + * Name: stm32_fmc_sdram_init + * + * Description: + * Initialize the SDRAM chips. + * + ****************************************************************************/ + +#if defined HAVE_FMC_SDRAM1 && defined HAVE_FMC_SDRAM2 +# define FMC_SDCMR_CTB FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2 +#elif defined HAVE_FMC_SDRAM1 +# define FMC_SDCMR_CTB FMC_SDCMR_CTB1 +#else +# define FMC_SDCMR_CTB FMC_SDCMR_CTB2 +#endif + +void stm32_fmc_sdram_init(void) +{ + /* What is happening here: + * ... A 100μs delay is required prior to issuing any command [...] + * a PRECHARGE command should be applied once the 100μs delay has been + * satisfied. + * + * All banks must be precharged. This will leave all banks in an idle + * state after which at least two AUTO REFRESH cycles must be performed. + * After the AUTO REFRESH cycles are complete, the SDRAM is then ready + * for mode register programming. + * + * The mode register should be loaded prior to applying any operational + * command because it will power up in an unknown state. + */ + + up_udelay(100); + + /* Clock Configuration Enable */ + + stm32_fmc_sdram_command(FMC_SDCMR_CTB | FMC_SDCMR_MODE_CLK_ENABLE); + + /* Wait for clock to stabilize */ + + up_mdelay(1); + + /* Precharge all banks */ + + stm32_fmc_sdram_wait(SDRAM_INIT_TIMEOUT); + stm32_fmc_sdram_command(FMC_SDCMR_CTB | FMC_SDCMR_MODE_PALL); + + /* Auto refresh */ + + stm32_fmc_sdram_wait(SDRAM_INIT_TIMEOUT); + stm32_fmc_sdram_command(FMC_SDCMR_CTB | FMC_SDCMR_MODE_AUTO_REFRESH | + FMC_SDCMR_NRFS(BOARD_FMC_SDRAM_AUTOREFRESH)); + + /* Program the SDRAM mode register */ + + /* If using two SDRAM chips, this will write same mode for both. + * If different mode is required for every chip (why?), it would be + * needed to split code into two separate LOAD_MODE commands, + * one for every SDRAM chip. + */ + + stm32_fmc_sdram_wait(SDRAM_INIT_TIMEOUT); + stm32_fmc_sdram_command(FMC_SDCMR_CTB | FMC_SDCMR_MODE_LOAD_MODE | + BOARD_FMC_SDRAM_MODE); } /**************************************************************************** - * Name: stm32_fmc_disable + * Name: stm32_fmc_sdram_wait * * Description: - * Disable clocking to the FMC. + * Wait until SDRAM controller is ready for all configured SDRAM banks. + * + * Parameters: + * timeout - number of microseconds before giving up waiting. + * + * Returns: + * 0 if all configured SDRAM banks are ready, -1 on timeout * ****************************************************************************/ -void stm32_fmc_disable(void) +int stm32_fmc_sdram_wait(unsigned timeout) { - modifyreg32(STM32_RCC_AHB3ENR, RCC_AHB3ENR_FMCEN, 0); + /* Wait until the SDRAM controller is ready */ + + for (; timeout; timeout--) + { + uint32_t sdsr = getreg32(STM32_FMC_SDSR); + if (1 +#if defined HAVE_FMC_SDRAM1 + && ((sdsr & FMC_SDSR_MODES1_MASK) == FMC_SDSR_MODES1_NORMAL) +#endif +#if defined HAVE_FMC_SDRAM2 + && ((sdsr & FMC_SDSR_MODES2_MASK) == FMC_SDSR_MODES2_NORMAL) +#endif + ) + return 0; + + up_udelay(1); + } + + return -1; } +#endif + /**************************************************************************** * Name: stm32_fmc_sdram_write_protect * @@ -92,11 +462,11 @@ void stm32_fmc_sdram_write_protect(int bank, bool state) val = getreg32(sdcr); if (state) { - val |= FMC_SDRAM_CR_WRITE_PROTECT; /* wp == 1 */ + val |= FMC_SDCR_WP; /* wp == 1 */ } else { - val &= ~FMC_SDRAM_CR_WRITE_PROTECT; /* wp == 0 */ + val &= ~FMC_SDCR_WP; /* wp == 0 */ } putreg32(val, sdcr); @@ -112,10 +482,8 @@ void stm32_fmc_sdram_write_protect(int bank, bool state) void stm32_fmc_sdram_set_refresh_rate(int count) { - uint32_t val; - DEBUGASSERT(count <= 0x1fff && count >= 0x29); - putreg32(count << 1, STM32_FMC_SDRTR); + putreg32(FMC_SDRTR_COUNT(count), STM32_FMC_SDRTR); } /**************************************************************************** @@ -132,11 +500,11 @@ void stm32_fmc_sdram_set_timing(int bank, uint32_t timing) uint32_t sdtr; DEBUGASSERT((bank == 1) || (bank == 2)); - DEBUGASSERT((timing & FMC_SDRAM_TR_RESERVED) == 0); + DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0); sdtr = (bank == 1) ? STM32_FMC_SDTR1 : STM32_FMC_SDTR2; val = getreg32(sdtr); - val &= FMC_SDRAM_TR_RESERVED; /* preserve reserved bits */ + val &= FMC_SDTR_RESERVED; /* preserve reserved bits */ val |= timing; putreg32(val, sdtr); } @@ -170,11 +538,11 @@ void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl) uint32_t sdcr; DEBUGASSERT((bank == 1) || (bank == 2)); - DEBUGASSERT((ctrl & FMC_SDRAM_CR_RESERVED) == 0); + DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0); sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2; val = getreg32(sdcr); - val &= FMC_SDRAM_CR_RESERVED; /* preserve reserved bits */ + val &= FMC_SDCR_RESERVED; /* preserve reserved bits */ val |= ctrl; putreg32(val, sdcr); } @@ -189,7 +557,7 @@ void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl) void stm32_fmc_sdram_command(uint32_t cmd) { - DEBUGASSERT((cmd & FMC_SDRAM_CMD_RESERVED) == 0); + DEBUGASSERT((cmd & FMC_SDCMR_RESERVED) == 0); putreg32(cmd, STM32_FMC_SDCMR); } diff --git a/arch/arm/src/stm32h7/stm32_fmc.h b/arch/arm/src/stm32h7/stm32_fmc.h index 9f0ccea2a9..3473f82e60 100644 --- a/arch/arm/src/stm32h7/stm32_fmc.h +++ b/arch/arm/src/stm32h7/stm32_fmc.h @@ -45,10 +45,6 @@ #include "chip.h" #include "hardware/stm32_fmc.h" -/**************************************************************************** - * Public Functions - ****************************************************************************/ - #ifndef __ASSEMBLY__ #undef EXTERN @@ -61,14 +57,22 @@ extern "C" #endif /**************************************************************************** - * Name: stm32_fmc_sdram_wait + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_fmc_init * * Description: - * Wait for the SDRAM controller to be ready. + * Initialize the FMC peripherial. Because FMC initialization is highly + * dependent on the used parts, definition of the initial values for FMC + * registers is mostly left to board designer. + * + * Typically called from up_addregion(). * ****************************************************************************/ -void stm32_fmc_sdram_wait(void); +void stm32_fmc_init(void); /**************************************************************************** * Name: stm32_fmc_enable diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index b1881e42c0..274ee03807 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -298,6 +298,12 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_SDMMC1EN; #endif +#ifdef CONFIG_STM32H7_FMC + /* Flexible static memory controller module clock enable */ + + regval |= RCC_AHB3ENR_FMCEN; +#endif + /* TODO: ... */ putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ @@ -775,7 +781,7 @@ static void stm32_stdclockconfig(void) } #endif - /* Ww must write the lower byte of the PWR_CR3 register is written once + /* We must write the lower byte of the PWR_CR3 register is written once * after POR and it shall be written before changing VOS level or * ck_sys clock frequency. No limitation applies to the upper bytes. * diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c index 4ba1348d6f..e15cfbe6c4 100644 --- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c @@ -142,8 +142,8 @@ static inline void rcc_reset(void) putreg32(regval, STM32_RCC_CR); #if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR) - /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to data - * read corruption. See ES0392 Rev 6. + /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to + * data read corruption. See ES0392 Rev 6. */ putreg32(AXI_TARG_READ_ISS_OVERRIDE, STM32_AXI_TARG7_FN_MOD); @@ -298,6 +298,12 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_SDMMC1EN; #endif +#ifdef CONFIG_STM32H7_FMC + /* Flexible static memory controller module clock enable */ + + regval |= RCC_AHB3ENR_FMCEN; +#endif + /* TODO: ... */ putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ @@ -775,16 +781,16 @@ static void stm32_stdclockconfig(void) } #endif - /* Ww must write the lower byte of the PWR_CR3 register is written once - * after POR and it shall be written before changing VOS level or ck_sys - * clock frequency. No limitation applies to the upper bytes. + /* We must write the lower byte of the PWR_CR3 register is written once + * after POR and it shall be written before changing VOS level or + * ck_sys clock frequency. No limitation applies to the upper bytes. * * Programming data corresponding to an invalid combination of * LDOEN and BYPASS bits will be ignored: data will not be written, * the written-once mechanism will lock the register and any further * write access will be ignored. The default supply configuration will - * be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) - * will go on indicating invalid voltage levels. + * be kept and the ACTVOSRDY bit in PWR control status register 1 + * (PWR_CSR1) will go on indicating invalid voltage levels. * * N.B. The system shall be power cycled before writing a new value. */