arch/risc-v/litex: Allow FDT to be passed from previous boot change.

Allows a flattened device tree to be passed from either openSBI or the LiteX bios. The FDT is registered can be used, if supported.

Documentation/platforms/risc-v/litex/cores/vexriscv/index.rst

@@ -22,7 +22,8 @@ Booting
 Create a file, 'boot.json' in the Nuttx root directory, with the following content::
 
   {
-    "nuttx.bin": "0x40000000"
+    "nuttx.bin": "0x40000000",
+    "board.dtb": "0x41ec0000"
   }
 
 Load the application over serial with::

Documentation/platforms/risc-v/litex/cores/vexriscv_smp/index.rst

@@ -45,6 +45,7 @@ Create a file, 'boot.json' in the Nuttx root directory, with the following conte
   {
     "romfs.img":   "0x40C00000",
     "nuttx.bin":   "0x40000000",
+    "board.dtb":   "0x41ec0000",
     "opensbi.bin": "0x40f00000"
   }
 

Documentation/platforms/risc-v/litex/index.rst

@@ -59,6 +59,26 @@ the source can be obtained from https://github.com/riscv-collab/riscv-gnu-toolch
    
 Check the linked github repository for other options, including building with multilib enabled.
 
+Device tree support
+=========================
+
+Currently, the litex port requires that the memory mapped peripheral addresses and IRQ numbers
+match those generated by LiteX. Although, this approach is being phased-out in favour of
+using a flattened device tree (FDT) to dynamically instantiate drivers.
+
+Generating and compiling the device tree::
+
+   $ ./litex/tools/litex_json2dts_linux.py path/to/built/gateware/csr.json > board.dts
+   $ dtc -@ -I dts -O dtb board.dts -o board.dtb
+
+Ensure the board.dtb is placed in the NuttX root directory.
+
+If a peripheral isn't working with the LiteX generated gateware, consider checking
+the addresses and IRQ numbers in
+
+ - arch/risc-v/src/litex/hardware/litex_memorymap.h
+ - arch/risc-v/include/litex/irq.h
+
 Core specific information
 =========================
 

arch/risc-v/Kconfig

@@ -46,6 +46,8 @@ config ARCH_CHIP_LITEX
 	select ARCH_DCACHE
 	select ARCH_HAVE_TICKLESS
 	select ARCH_HAVE_RESET
+	select LIBC_FDT
+	select DEVICE_TREE
 	---help---
 		Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA).
 

arch/risc-v/src/litex/Kconfig

@@ -18,6 +18,10 @@ config LITEX_COHERENT_DMA
 		Select this option if the soft core was build with coherent DMA. When selected,
 		dcache is considered coherent and not invalidated before DMA transfers.
 
+config LITEX_FDT_MEMORY_ADDRESS
+	hex "Location of the FDT in memory"
+	default 0x41ec0000
+
 menu "LITEX Peripheral Support"
 
 # These "hidden" settings determine whether a peripheral option is available

arch/risc-v/src/litex/litex_start.c

@@ -26,6 +26,7 @@
 
 #include <stdint.h>
 
+#include <nuttx/fdt.h>
 #include <nuttx/init.h>
 #include <arch/board/board.h>
 
@@ -75,8 +76,11 @@ uintptr_t g_idle_topstack = LITEX_IDLESTACK_TOP;
  * Name: __litex_start
  ****************************************************************************/
 
-void __litex_start(void)
+void __litex_start(int hart_index, const void * fdt, int arg)
 {
+  (void)hart_index;
+  (void)arg;
+
   const uint32_t *src;
   uint32_t *dest;
 
@@ -104,6 +108,17 @@ void __litex_start(void)
       *dest++ = *src++;
     }
 
+  /* Assume the FDT address was passed in if not NULL */
+
+  if (fdt)
+    {
+      fdt_register(fdt);
+    }
+  else
+    {
+      fdt_register((const char *)CONFIG_LITEX_FDT_MEMORY_ADDRESS);
+    }
+
 #ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
   riscv_percpu_add_hart(0);
 #endif