From 4049f690af9088b03a0486e05b821c2de8816e7c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 21 Mar 2019 14:41:03 -0600 Subject: [PATCH] arch/arm/src/stm32/stm32_dfumode.c: Will work only for STM32 F2 and F4. --- arch/arm/src/stm32/stm32_dfumode.c | 10 +++++++--- arch/arm/src/stm32/stm32_dfumode.h | 2 ++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/stm32/stm32_dfumode.c b/arch/arm/src/stm32/stm32_dfumode.c index 1bdb7ba336..28c2d8f661 100644 --- a/arch/arm/src/stm32/stm32_dfumode.c +++ b/arch/arm/src/stm32/stm32_dfumode.c @@ -58,14 +58,17 @@ * * https://community.st.com/s/question/0D50X00009XkhAzSAJ/calling-stm32429ieval-bootloader * - * REVISIT: STM32_SYSMEM_BASE is not 0x1fff000 for all STM32's. Fof F3's + * REVISIT: STM32_SYSMEM_BASE is not 0x1fff000 for all STM32's. For F3's * The SYSMEM base is at 0x1fffd800 * - * REVISIT: RCC_APB2ENR_SYSCFGEN is not bit bit 14 for all STM32's. For - * F3's and L15's, it is bit 0. + * REVISIT: RCC_APB2ENR_SYSCFGEN is not bit 14 for all STM32's. For F3's + * and L15's, it is bit 0. + * + * REVISIT: STM32 F3's do not support the SYSCFG_MEMRMP register. * ****************************************************************************/ +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) void stm32_dfumode(void) { #ifdef CONFIG_DEBUG_WARN @@ -86,3 +89,4 @@ void stm32_dfumode(void) __builtin_unreachable(); /* Tell compiler we will not return */ } +#endif /* CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ diff --git a/arch/arm/src/stm32/stm32_dfumode.h b/arch/arm/src/stm32/stm32_dfumode.h index c06397b1c0..0edfd169da 100644 --- a/arch/arm/src/stm32/stm32_dfumode.h +++ b/arch/arm/src/stm32/stm32_dfumode.h @@ -56,6 +56,8 @@ * ****************************************************************************/ +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) void stm32_dfumode(void) noreturn_function; +#endif #endif /* __ARCH_ARM_SRC_STM32_DFUMODE_H */