PIC32MZ: Most related to start up file a FLASH device configuration setup
This commit is contained in:
Gregory Nutt
parent
c1da98fb57
commit
40f40dad5a
@ -54,53 +54,28 @@
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/* Clocking *****************************************************************/
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/* Crystal frequencies */
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#define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */
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#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
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#define BOARD_POSC_FREQ 24000000 /* Primary OSC XTAL frequency (24MHz) */
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#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
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/* Oscillator modes */
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#define BOARD_FNOSC_POSCPLL 1 /* Use primary oscillator w/PLL */
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#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */
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#define BOARD_FNOSC_POSC 1 /* Use primary oscillator */
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#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */
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/* PLL configuration and resulting CPU clock.
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* CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV
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*/
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#define BOARD_PLL_INPUT BOARD_POSC_FREQ
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#define BOARD_PLL_IDIV 2 /* PLL input divider */
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#define BOARD_PLL_MULT 20 /* PLL multiplier */
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#define BOARD_PLL_ODIV 1 /* PLL output divider */
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#define BOARD_PLL_IDIV 3 /* PLL input divider */
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#define BOARD_PLL_MULT 50 /* PLL multiplier */
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#define BOARD_PLL_ODIV 2 /* PLL output divider */
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#define BOARD_CPU_CLOCK 80000000 /* CPU clock (80MHz = 8MHz * 20 / 2) */
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/* USB PLL configuration.
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* USB_CLOCK = ((POSC_XTAL / IDIV) * 24) / 2
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*/
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#define BOARD_UPLL_IDIV 2 /* USB PLL divider (revisit) */
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#define BOARD_USB_CLOCK 48000000 /* USB clock (8MHz / 2) * 24 / 2) */
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/* Peripheral clock is divided down from CPU clock.
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* PBCLOCK = CPU_CLOCK / PBDIV
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*/
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#define BOARD_PBDIV 2 /* Peripheral clock divisor (PBDIV) */
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#define BOARD_PBCLOCK 40000000 /* Peripheral clock (PBCLK = 80MHz/2) */
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#define BOARD_CPU_CLOCK 200000000 /* CPU clock: 200MHz = (24MHz / 3) * 50 / 2) */
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/* Watchdog pre-scaler (re-visit) */
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#define BOARD_WD_ENABLE 0 /* Watchdog is disabled */
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#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */
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/* Ethernet MII clocking.
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*
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* The clock divider used to create the MII Management Clock (MDC). The MIIM
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* module uses the SYSCLK as an input clock. According to the IEEE 802.3
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* Specification this should be no faster than 2.5 MHz. However, some PHYs
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* support clock rates up to 12.5 MHz.
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*/
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#define BOARD_EMAC_MIIM_DIV 32 /* Ideal: 80MHz/32 = 2.5MHz */
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#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */
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/* LED definitions **********************************************************/
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/* LED Configuration ********************************************************/
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@ -143,41 +143,30 @@ CONFIG_PIC32MZ_UART1=y
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# CONFIG_PIC32MZ_ETHERNET is not set
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# CONFIG_PIC32MZ_CTMU is not set
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#
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# PIC32MZ Peripheral Interrupt Priorities
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#
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CONFIG_PIC32MZ_CTPRIO=16
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CONFIG_PIC32MZ_CS0PRIO=16
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CONFIG_PIC32MZ_CS1PRIO=16
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CONFIG_PIC32MZ_INT0PRIO=16
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CONFIG_PIC32MZ_INT1PRIO=16
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CONFIG_PIC32MZ_INT2PRIO=16
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CONFIG_PIC32MZ_INT3PRIO=16
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CONFIG_PIC32MZ_INT4PRIO=16
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CONFIG_PIC32MZ_T1PRIO=16
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CONFIG_PIC32MZ_UART1PRIO=16
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#
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# Device Configuration 0 (DEVCFG0)
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#
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CONFIG_PIC32MZ_DEBUGGER=2
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CONFIG_PIC32MZ_ICESEL=1
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CONFIG_PIC32MZ_PROGFLASHWP=0xff
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CONFIG_PIC32MZ_BOOTFLASHWP=1
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CONFIG_PIC32MZ_CODEWP=1
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# CONFIG_PIC32MZ_DEBUGGER_ENABLE is not set
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CONFIG_PIC32MZ_JTAG_ENABLE=y
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# CONFIG_PIC32MZ_ICESEL_CH2 is not set
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# CONFIG_PIC32MZ_TRACE_ENABLE is not set
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#
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# Device Configuration 1 (DEVCFG1)
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#
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CONFIG_CONFIG_PIC32MZ_OSCIOFNC=0
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# CONFIG_PIC32MZ_WDTENABLE is not set
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#
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# Device Configuration 3 (DEVCFG3)
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#
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CONFIG_PIC32MZ_USBIDO=0
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CONFIG_PIC32MZ_VBUSIO=0
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# CONFIG_PIC32MZ_WDENABLE is not set
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CONFIG_PIC32MZ_FETHIO=0
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CONFIG_PIC32MZ_USERID=0x584e
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CONFIG_PIC32MZ_FMIIEN=0
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CONFIG_PIC32MZ_PGL1WAY=0
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CONFIG_PIC32MZ_PMDL1WAY=0
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CONFIG_PIC32MZ_IOL1WAY=0
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CONFIG_PIC32MZ_FETHIO=0
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CONFIG_PIC32MZ_FUSBIDIO=1
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#
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# Architecture Options
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@ -59,7 +59,8 @@ MEMORY
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* JTAG 0x1fc00480 KSEG1 16 1168
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* Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb)
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* Debug code 0x1fc02000 KSEG1 4096-16 12272
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* DEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
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* ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
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* DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb)
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*
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* Exceptions assume:
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*
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@ -77,7 +78,8 @@ MEMORY
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kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
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kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168
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kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
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kseg1_devcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 192
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kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128
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kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128
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/* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb
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* of data memory at physical address 0x00000000. Since the PIC32MZ
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@ -159,6 +161,11 @@ SECTIONS
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.dbg_code = ORIGIN(kseg1_dbgcode);
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.adevcfg :
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{
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KEEP (*(.adevcfg))
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} > kseg1_adevcfg
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.devcfg :
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{
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KEEP (*(.devcfg))
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@ -59,7 +59,8 @@ MEMORY
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* JTAG 0x1fc00480 KSEG1 16 1168
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* Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb)
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* Debug code 0x1fc02000 KSEG1 4096-16 12272
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* DEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
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* ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
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* DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb)
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*
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* Exceptions assume:
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*
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@ -77,7 +78,8 @@ MEMORY
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kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
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kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168
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kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
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kseg1_devcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 192
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kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128
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kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128
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/* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb
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* of data memory at physical address 0x00000000. Since the PIC32MZ
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@ -159,6 +161,11 @@ SECTIONS
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.dbg_code = ORIGIN(kseg1_dbgcode);
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.adevcfg :
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{
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KEEP (*(.adevcfg))
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} > kseg1_adevcfg
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.devcfg :
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{
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KEEP (*(.devcfg))
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