diff --git a/configs/pic32mz-starterkit/include/board.h b/configs/pic32mz-starterkit/include/board.h index 1bc4f48a38..0783095490 100644 --- a/configs/pic32mz-starterkit/include/board.h +++ b/configs/pic32mz-starterkit/include/board.h @@ -54,53 +54,28 @@ /* Clocking *****************************************************************/ /* Crystal frequencies */ -#define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */ -#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */ +#define BOARD_POSC_FREQ 24000000 /* Primary OSC XTAL frequency (24MHz) */ +#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */ /* Oscillator modes */ -#define BOARD_FNOSC_POSCPLL 1 /* Use primary oscillator w/PLL */ -#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */ +#define BOARD_FNOSC_POSC 1 /* Use primary oscillator */ +#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */ /* PLL configuration and resulting CPU clock. * CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV */ #define BOARD_PLL_INPUT BOARD_POSC_FREQ -#define BOARD_PLL_IDIV 2 /* PLL input divider */ -#define BOARD_PLL_MULT 20 /* PLL multiplier */ -#define BOARD_PLL_ODIV 1 /* PLL output divider */ +#define BOARD_PLL_IDIV 3 /* PLL input divider */ +#define BOARD_PLL_MULT 50 /* PLL multiplier */ +#define BOARD_PLL_ODIV 2 /* PLL output divider */ -#define BOARD_CPU_CLOCK 80000000 /* CPU clock (80MHz = 8MHz * 20 / 2) */ - -/* USB PLL configuration. - * USB_CLOCK = ((POSC_XTAL / IDIV) * 24) / 2 - */ - -#define BOARD_UPLL_IDIV 2 /* USB PLL divider (revisit) */ -#define BOARD_USB_CLOCK 48000000 /* USB clock (8MHz / 2) * 24 / 2) */ - -/* Peripheral clock is divided down from CPU clock. - * PBCLOCK = CPU_CLOCK / PBDIV - */ - -#define BOARD_PBDIV 2 /* Peripheral clock divisor (PBDIV) */ -#define BOARD_PBCLOCK 40000000 /* Peripheral clock (PBCLK = 80MHz/2) */ +#define BOARD_CPU_CLOCK 200000000 /* CPU clock: 200MHz = (24MHz / 3) * 50 / 2) */ /* Watchdog pre-scaler (re-visit) */ -#define BOARD_WD_ENABLE 0 /* Watchdog is disabled */ -#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */ - -/* Ethernet MII clocking. - * - * The clock divider used to create the MII Management Clock (MDC). The MIIM - * module uses the SYSCLK as an input clock. According to the IEEE 802.3 - * Specification this should be no faster than 2.5 MHz. However, some PHYs - * support clock rates up to 12.5 MHz. - */ - -#define BOARD_EMAC_MIIM_DIV 32 /* Ideal: 80MHz/32 = 2.5MHz */ +#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */ /* LED definitions **********************************************************/ /* LED Configuration ********************************************************/ diff --git a/configs/pic32mz-starterkit/nsh/defconfig b/configs/pic32mz-starterkit/nsh/defconfig index 73d288a580..e9c1d04428 100644 --- a/configs/pic32mz-starterkit/nsh/defconfig +++ b/configs/pic32mz-starterkit/nsh/defconfig @@ -143,41 +143,30 @@ CONFIG_PIC32MZ_UART1=y # CONFIG_PIC32MZ_ETHERNET is not set # CONFIG_PIC32MZ_CTMU is not set -# -# PIC32MZ Peripheral Interrupt Priorities -# -CONFIG_PIC32MZ_CTPRIO=16 -CONFIG_PIC32MZ_CS0PRIO=16 -CONFIG_PIC32MZ_CS1PRIO=16 -CONFIG_PIC32MZ_INT0PRIO=16 -CONFIG_PIC32MZ_INT1PRIO=16 -CONFIG_PIC32MZ_INT2PRIO=16 -CONFIG_PIC32MZ_INT3PRIO=16 -CONFIG_PIC32MZ_INT4PRIO=16 -CONFIG_PIC32MZ_T1PRIO=16 -CONFIG_PIC32MZ_UART1PRIO=16 - # # Device Configuration 0 (DEVCFG0) # -CONFIG_PIC32MZ_DEBUGGER=2 -CONFIG_PIC32MZ_ICESEL=1 -CONFIG_PIC32MZ_PROGFLASHWP=0xff -CONFIG_PIC32MZ_BOOTFLASHWP=1 -CONFIG_PIC32MZ_CODEWP=1 +# CONFIG_PIC32MZ_DEBUGGER_ENABLE is not set +CONFIG_PIC32MZ_JTAG_ENABLE=y +# CONFIG_PIC32MZ_ICESEL_CH2 is not set +# CONFIG_PIC32MZ_TRACE_ENABLE is not set # # Device Configuration 1 (DEVCFG1) # +CONFIG_CONFIG_PIC32MZ_OSCIOFNC=0 +# CONFIG_PIC32MZ_WDTENABLE is not set # # Device Configuration 3 (DEVCFG3) # -CONFIG_PIC32MZ_USBIDO=0 -CONFIG_PIC32MZ_VBUSIO=0 -# CONFIG_PIC32MZ_WDENABLE is not set -CONFIG_PIC32MZ_FETHIO=0 +CONFIG_PIC32MZ_USERID=0x584e CONFIG_PIC32MZ_FMIIEN=0 +CONFIG_PIC32MZ_PGL1WAY=0 +CONFIG_PIC32MZ_PMDL1WAY=0 +CONFIG_PIC32MZ_IOL1WAY=0 +CONFIG_PIC32MZ_FETHIO=0 +CONFIG_PIC32MZ_FUSBIDIO=1 # # Architecture Options diff --git a/configs/pic32mz-starterkit/scripts/c32-release.ld b/configs/pic32mz-starterkit/scripts/c32-release.ld index b385bc21a9..e19fc073f6 100644 --- a/configs/pic32mz-starterkit/scripts/c32-release.ld +++ b/configs/pic32mz-starterkit/scripts/c32-release.ld @@ -59,7 +59,8 @@ MEMORY * JTAG 0x1fc00480 KSEG1 16 1168 * Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb) * Debug code 0x1fc02000 KSEG1 4096-16 12272 - * DEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb) + * ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb) + * DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb) * * Exceptions assume: * @@ -77,7 +78,8 @@ MEMORY kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16 kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168 kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16 - kseg1_devcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 192 + kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128 + kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128 /* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb * of data memory at physical address 0x00000000. Since the PIC32MZ @@ -159,6 +161,11 @@ SECTIONS .dbg_code = ORIGIN(kseg1_dbgcode); + .adevcfg : + { + KEEP (*(.adevcfg)) + } > kseg1_adevcfg + .devcfg : { KEEP (*(.devcfg)) diff --git a/configs/pic32mz-starterkit/scripts/mips-release.ld b/configs/pic32mz-starterkit/scripts/mips-release.ld index 94ed775a4a..cc51d43fe0 100644 --- a/configs/pic32mz-starterkit/scripts/mips-release.ld +++ b/configs/pic32mz-starterkit/scripts/mips-release.ld @@ -59,7 +59,8 @@ MEMORY * JTAG 0x1fc00480 KSEG1 16 1168 * Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb) * Debug code 0x1fc02000 KSEG1 4096-16 12272 - * DEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb) + * ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb) + * DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb) * * Exceptions assume: * @@ -77,7 +78,8 @@ MEMORY kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16 kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168 kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16 - kseg1_devcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 192 + kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128 + kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128 /* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb * of data memory at physical address 0x00000000. Since the PIC32MZ @@ -159,6 +161,11 @@ SECTIONS .dbg_code = ORIGIN(kseg1_dbgcode); + .adevcfg : + { + KEEP (*(.adevcfg)) + } > kseg1_adevcfg + .devcfg : { KEEP (*(.devcfg))