Add SYSCFG definitions for STM32L152; Add board support STM32L-Discovery
This commit is contained in:
Gregory Nutt
parent
0ccea89f32
commit
4124f55382
@ -480,6 +480,11 @@ config STM32_ADC4
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select STM32_ADC
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depends on STM32_STM32F30XX
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config STM32_COMP
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bool "COMP"
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default n
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depends on STM32_STM32L15XX
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config STM32_BKP
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bool "BKP"
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default n
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@ -626,7 +631,7 @@ config STM32_SPI2
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config STM32_SPI3
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bool "SPI3"
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default n
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depends on STM32_CONNECTIVITYLINE || STM32_STM32F20XX || STM32_STM32F40XX || (STM32_VALUELINE && STM32_HIGHDENSITY)
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depends on STM32_CONNECTIVITYLINE || STM32_STM32L15XX || STM32_STM32F20XX || STM32_STM32F40XX || (STM32_VALUELINE && STM32_HIGHDENSITY)
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select SPI
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select STM32_SPI
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@ -654,7 +659,7 @@ config STM32_SPI6
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config STM32_SYSCFG
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bool "SYSCFG"
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default y
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depends on STM32_STM32F30XX || STM32_STM32F20XX || STM32_STM32F40XX
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depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F20XX || STM32_STM32F40XX
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config STM32_TIM1
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bool "TIM1"
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@ -693,17 +698,17 @@ config STM32_TIM8
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config STM32_TIM9
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bool "TIM9"
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default n
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depends on STM32_STM32F20XX || STM32_STM32F40XX
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depends on STM32_STM32L15XX || STM32_STM32F20XX || STM32_STM32F40XX
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config STM32_TIM10
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bool "TIM10"
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default n
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depends on STM32_STM32F20XX || STM32_STM32F40XX
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depends on STM32_STM32L15XX || STM32_STM32F20XX || STM32_STM32F40XX
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config STM32_TIM11
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bool "TIM11"
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default n
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depends on STM32_STM32F20XX || STM32_STM32F40XX
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depends on STM32_STM32L15XX || STM32_STM32F20XX || STM32_STM32F40XX
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config STM32_TIM12
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bool "TIM12"
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@ -797,7 +802,7 @@ config STM32_UART8
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config STM32_USB
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bool "USB Device"
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default n
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depends on (STM32_STM32F10XX && !STM32_VALUELINE) || STM32_STM32F30XX
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depends on (STM32_STM32F10XX && !STM32_VALUELINE) || STM32_STM32L15XX || STM32_STM32F30XX
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select USBDEV
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config STM32_WWDG
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@ -1,5 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32f30xx_rcc.h
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* For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
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* 32-bit MCUs
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -80,10 +80,10 @@
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/* SYSCFG memory remap register */
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#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */
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#define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_SHIFT)
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# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_SHIFT) /* 00: Main Flash at 0x00000000 */
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# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_SHIFT) /* 01: System Flash at 0x00000000 */
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# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_SHIFT) /* 11: Embedded SRAM at 0x00000000 */
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#define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_MEMMODE_SHIFT)
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# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */
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# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */
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# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */
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#define SYSCFG_CFGR1_USB_ITRMP (1 << 5) /* Bit 5: USB interrupt remap */
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#define SYSCFG_CFGR1_TIM1_ITR3RMP (1 << 6) /* Bit 6: Timer 1 ITR3 selection */
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#define SYSCFG_CFGR1_DAC_TRIGRMP (1 << 7) /* Bit 7: DAC trigger remap (when TSEL = 001) */
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@ -428,14 +428,18 @@
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/* Bits 2-7: Reserved */
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#define RCC_CSR_LSEON (1 << 8) /* Bit 8: External Low Speed oscillator enable */
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#define RCC_CSR_LSERDY (1 << 9) /* Bit 9: External Low Speed oscillator Ready */
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#define RCC_CSR_LSEBYP (1 << 10) /* Bit 10: External Low Speed oscillator Ready */
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#define RCC_CSR_LSECSSON (1 << 11) /* Bit 11: External Low Speed oscillator Ready */
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#define RCC_CSR_LSECSSD (1 << 12) /* Bit 12: External Low Speed oscillator Ready */
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#define RCC_CSR_LSEBYP (1 << 10) /* Bit 10: External low-speed oscillator bypass */
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#define RCC_CSR_LSECSSON (1 << 11) /* Bit 11: CSS on LSE enable */
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#define RCC_CSR_LSECSSD (1 << 12) /* Bit 12: CSS on LSE failure Detection */
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/* Bits 13-15: Reserved */
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#define RCC_CSR_RTCSEL_SHIFT (16) /* Bits 16-17: */
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#define RCC_CSR_RTCSEL_SHIFT (16) /* Bits 16-17: RTC and LCD clock source selection */
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#define RCC_CSR_RTCSEL_MASK (3 << RCC_CSR_RTCSEL_SHIFT)
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#define RCC_CSR_RTCEN (1 << 22) /* Bit 22: */
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#define RCC_CSR_RTCRST (1 << 23) /* Bit 23: */
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# define RCC_CSR_RTCSEL_NONE (0 << RCC_CSR_RTCSEL_SHIFT) /* 00: No clock */
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# define RCC_CSR_RTCSEL_LSE (1 << RCC_CSR_RTCSEL_SHIFT) /* 01: LSE oscillator clock is RTC/LCD clock */
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# define RCC_CSR_RTCSEL_LSI (2 << RCC_CSR_RTCSEL_SHIFT) /* 10: LSI oscillator clock is RTC/LCD clock */
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# define RCC_CSR_RTCSEL_HSE (3 << RCC_CSR_RTCSEL_SHIFT) /* 11: Divided HSE oscillator clock is RTC/LCD clock */
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#define RCC_CSR_RTCEN (1 << 22) /* Bit 22: RTC clock enable */
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#define RCC_CSR_RTCRST (1 << 23) /* Bit 23: RTC software reset */
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#define RCC_CSR_RMVF (1 << 24) /* Bit 24: Remove reset flag */
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#define RCC_CSR_OBLRSTF (1 << 25) /* Bit 25: Option byte loader reset flag */
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#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */
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159
arch/arm/src/stm32/chip/stm32l15xxx_syscfg.h
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159
arch/arm/src/stm32/chip/stm32l15xxx_syscfg.h
Normal file
@ -0,0 +1,159 @@
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/****************************************************************************************************
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* arch/arm/src/stm32/chip/stm32l15xxx_syscfg.h
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* For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
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* 32-bit MCUs
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_SYSCFG_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_SYSCFG_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Register Offsets *********************************************************************************/
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#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
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#define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */
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#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
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#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
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#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
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#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
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#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
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/* Register Addresses *******************************************************************************/
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#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
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#define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET)
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#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
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#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
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#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
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#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
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#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
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/* Register Bitfield Definitions ********************************************************************/
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/* SYSCFG memory remap register */
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#define SYSCFG_MEMRMP_MEMMODE_SHIFT (0) /* Bits 0-1: Memory mapping selection */
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#define SYSCFG_MEMRMP_MEMMODE_MASK (3 << SYSCFG_MEMRMP_MEMMODE_SHIFT)
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# define SYSCFG_MEMRMP_MEMMODE_FLASH (0 << SYSCFG_MEMRMP_MEMMODE_SHIFT) /* 00: Main Flash memory mapped at 0x00000000 */
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# define SYSCFG_MEMRMP_MEMMODE_SYSTEM (1 << SYSCFG_MEMRMP_MEMMODE_SHIFT) /* 01: System Flash memory mapped at 0x00000000 */
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# define SYSCFG_MEMRMP_MEMMODE_FSMC (2 << SYSCFG_MEMRMP_MEMMODE_SHIFT) /* 10: FSMC */
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# define SYSCFG_MEMRMP_MEMMODE_SRAM (3 << SYSCFG_MEMRMP_MEMMODE_SHIFT) /* 11: SRAM mapped at 0x00000000 */
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/* Bits 2-7: Reserved */
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#define SYSCFG_MEMRMP_BOOTMODE_SHIFT (0) /* Bits 8-9: Boot mode selected by the boot pins */
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#define SYSCFG_MEMRMP_BOOTMODE_MASK (3 << SYSCFG_MEMRMP_BOOTMODE_SHIFT)
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# define SYSCFG_MEMRMP_BOOTMODE_FLASH (0 << SYSCFG_MEMRMP_BOOTMODE_SHIFT) /* 00: Main Flash memory boot mode */
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# define SYSCFG_MEMRMP_BOOTMODE_SYSTEM (1 << SYSCFG_MEMRMP_BOOTMODE_SHIFT) /* 01: System Flash memory boot mode */
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# define SYSCFG_MEMRMP_BOOTMODE_SRAM (3 << SYSCFG_MEMRMP_BOOTMODE_SHIFT) /* 11: Embedded SRAM boot mode */
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/* Bits 10-31: Reserved */
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/* SYSCFG peripheral mode configuration register */
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#define SYSCFG_PMC_USBPU (1 << 0) /* Bit 0: USB pull-up enable on DP line */
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#define SYSCFG_PMC_LCDCAPA_SHIFT (1) /* Bits 1-5: LCD decoupling capacitance connection */
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#define SYSCFG_PMC_LCDCAPA_MASK (0x1f << SYSCFG_PMC_LCDCAPA_SHIFT)
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# define SYSCFG_PMC_LCDCAPA_PB2 (0x01 << SYSCFG_PMC_LCDCAPA_SHIFT) /* Bit 1: Controls VLCDrail2 on PB2/LCD_VCAP2 */
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# define SYSCFG_PMC_LCDCAPA_PB12 (0x02 << SYSCFG_PMC_LCDCAPA_SHIFT) /* Bit 2: Controls VLCDrail1 on PB12/LCD_VCAP1 */
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# define SYSCFG_PMC_LCDCAPA_PB0 (0x04 << SYSCFG_PMC_LCDCAPA_SHIFT) /* Bit 3: Controls VLCDrail3 on PB0/LCD_VCAP3 */
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# define SYSCFG_PMC_LCDCAPA_PE11 (0x08 << SYSCFG_PMC_LCDCAPA_SHIFT) /* Bit 4: Controls VLCDrail1 on PE11/LCD_VCAP1 */
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# define SYSCFG_PMC_LCDCAPA_PE12 (0x10 << SYSCFG_PMC_LCDCAPA_SHIFT) /* Bit 5: Controls VLCDrail3 on PE12/LCD_VCAP3 */
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/* Bits 6-31: Reserved */
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/* SYSCFG external interrupt configuration register 1-4 */
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#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
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#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
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#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
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#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
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#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
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#define SYSCFG_EXTICR_PORTH (5) /* 0101: PH[x] pin */
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#define SYSCFG_EXTICR_PORTF (6) /* 0110: PF[x] pin */
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#define SYSCFG_EXTICR_PORTG (7) /* 0111: PG[x] pin */
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#define SYSCFG_EXTICR_PORT_MASK (15)
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#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
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#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
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#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */
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#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
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#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */
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#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
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#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */
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#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
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#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */
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#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
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/* Bits 16-31: Reserved */
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#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */
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#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
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#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */
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#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
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#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */
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#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
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#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */
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#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
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/* Bits 16-31: Reserved */
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#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */
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#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
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#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */
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#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
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#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */
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#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
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#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */
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#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
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/* Bits 16-31: Reserved */
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#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */
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#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
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#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */
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#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
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#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */
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#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
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#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */
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#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
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/* Bits 16-31: Reserved */
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_SYSCFG_H */
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@ -291,7 +291,7 @@
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#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */
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#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT)
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#if define(CONFIG_STM32_STM32L15XX)
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#if defined(CONFIG_STM32_STM32L15XX)
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# define GPIO_SPEED_400KHz (0 << GPIO_SPEED_SHIFT) /* 400 kHz Very low speed output */
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# define GPIO_SPEED_2MHz (1 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
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# define GPIO_SPEED_10MHz (2 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */
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@ -43,7 +43,9 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32_STM32F20XX)
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#if defined(CONFIG_STM32_STM32L15XX)
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# include "chip/stm32l15xxx_syscfg.h"
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#elif defined(CONFIG_STM32_STM32F20XX)
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# include "chip/stm32f20xxx_syscfg.h"
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#elif defined(CONFIG_STM32_STM32F30XX)
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# include "chip/stm32f30xxx_syscfg.h"
|
||||
|
||||
@ -53,7 +53,7 @@
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_uart.h"
|
||||
#else
|
||||
# error "Unsupported STM32 memory map"
|
||||
# error "Unsupported STM32 UART"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
Loading…
Reference in New Issue
Block a user